SU1238088A1 - Interface for linking computer with using equipment - Google Patents

Abstract

The invention relates to the field of computer technology, in particular to devices for interfacing subscribers with a computer, and can be used in transmission systems, and as a rule. The aim of the invention is to increase the speed of the device. The device contains a group of buffer registers, two pulse distributors, two elements OR, a reversible counter, a single pulse shaper, a synchronization node, a group of elements AND, a decoder, a counter. 3 Il.

Description

one

The invention relates to computer technology, in particular to devices for interfacing subscribers with a computer, and can be used in data transmission systems.

The aim of the invention is to increase the speed of the device.

FIG. 1 is a block diagram of the device; in fig. 2 - synchronization node, an embodiment; in fig. FIG. 3 - timing diagram of the synchronization node.

The device contains (Fig. 1) a group of buffer registers t, the second and third pulse distributors 2 and 3, the first element OR 4, the reversible counter 5, the second element OR 6, the single pulse generator 7, the synchronization node 8, the group of elements AND 9, the decoder 10-, counter 11.

FIG. 1 also denotes a device synchronization input 12 from a computer, a device synchronization input 13 from a subscriber, information input 14 of a device from a computer, information output 15 devices to a subscriber, information inputs 16, recording inputs 17, control inputs 18 and readout inputs 19 of the buffer register group 1, the output 20 of the device in the computer, the output 21 of the readiness of the device to the subscriber, summing 2-2 and subtracting 23 inputs of the reversible counter 5, first 24 and second 25 inputs of the synchronization node 8, counting 26 and setting 27 inputs of the counter 11.

The synchronization unit 8 contains (FIG. 2) four D-flip-flops 28-31, two one-shot 32 and 33, two ele. COP NOT 34 and 35.

The serial connection of the outputs of registers 1 to the output 15 of the interface device is carried out via wired OR, which is controlled via inputs 18 of buffer registers 1 with distributor 3, pulse distributor 2 is intended to record information using a parallel code from a computer through input 14 of the device to buffer registers 1 , the control of reading information from the buffer registers 1 is carried out through the inputs 19 from the elements AND 9, the reversible counter 5 is designed to issue information about the number of free buffer re- gistrov in the computer, as well as for forming through the element Or signal Readiness for subscribers380882

so, the synchronization node 8 is designed to synchronize the addition and subtraction pulses at the inputs of the reversible counter, the counter 11 and the decoder 5 tor 10 are intended to highlight

K-th pulse required to connect the next register to issue an information word with a sequential code to the subscriber.

10 The device operates as follows.

By turning on the power in the device, an impulse is generated: a general reset, which brings all the memory elements to the initial state t5, e, e. buffer registers 1, valves 2 and 3, counters 5 and 11, a single pulse shaper 7, node 8 synchronization.

The computer 20, according to the state of the outputs 20 of the interface device, determines that all buffer registers 1 are free and you can begin to transmit information words to the subscriber. Subscriber through

25, device output 21 determines that all buffer registers 1 are free.

The information word intended for issuing from the computer to the subscriber enters through the input 14 of the device

30 interfaces to the input 16 of the buffer registers 1. The first clock pulse (SI) from the computer through the input 12 of the device enters through the synchronization unit 8 to the input of the pulse distributor 2, exciting the first bit of this distributor.

The impulse from the excited discharge goes to the input 17 of the corresponding buffer register 1, providing to it a record of the information tnoBa. In addition, the first MI from the first output of the synchronization node goes to the summing input 22 of the reversible counter 5, increasing its state by one, as well as to the input of the single pulse generator 7, which forms one pulse during the entire operation of the interface device. This one pulse through the element OR 6 is fed to the input

50 of the distributor 3, excitation of the first discharge of this distributor, which through the input 18 of the corresponding buffer register 1 provides the removal from its output of the third state and

55 connecting this buffer register via OR to output 15 of the interface. The result of adding from the outputs of the reversible counter35

40

45

ka 5 through output 20 of the device in binary code enters the computer, which monitors the number of free buffer registers 1, so that there is no loss of the information word or. malfunctions of the interface device From output 21, according to the result of the state of the reversible counter 5, through the IPI 4 element, the subscriber is ready, according to which the subscriber is allowed to apply for information to the interface device. From the input 13 of the device, the request pulses (FROM) are transmitted through the elements AND 9 to the input 19 of reading only that buffer register 1, which is currently connected to the output of the device 15, issuing an information word to the subscriber in a sequential code. In addition, FROM are sent to the counting input 26 of counter 11, which calculates the FROM necessary for the K-bit information word to the subscriber.

The decoder 10 selects the K-th OF which arrives at the input 27 of the installation of the counter 11 to its initial state and through the second input of the synchronization node 8 to the input 23 of the reversible counter 5, reducing by that its connection by one and the second input of the element OR 6, from the output of which to the input of the distributor 3, thereby exciting the next discharge of the distributor 3 and connecting the next buffer register 1 via OR to the output 15 of the device, thereby preparing it. To the next information word in the subscriber.

FIG. 3 shows the cyclogram of the synchronizer.

The synchronization node works in the following way.

With the simultaneous arrival of signals to the inputs 24 and 25 of the synchronization node, D-flip-flops 28 and 29 are set to one state, since the D-inputs of these flip-flops are connected to logic 1. After overwriting the states of flip-flops 28 and 29 into the next pair of D-flip-flops performed on the leading edge of the synchronization frequency in the D-flip-flop 31 and on the falling edge of the synchronization frequency in the D-flip-flop 30.

Single vibrators generate pulses of the required duration for reliable operation of the reversing account

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5, 10 th f5 20 -25 JQ.

- 50 55

35

chnka. The impulse from the odouralizer 32 is fed to the input of the addition of a reversible counter, as well as to the inputs of the installation in O of D-flip-flops 28 and 30.

The pulse from the one-shot 33 is fed to the input of the subtraction of the reversible counter, as well as to the inputs of the installation in the O D-flip-flops 29 and 31.

FIG. Figure 3 shows the sequence diagram of the operation: the synchronizer with different combinations of input signals. Regarding the synchronization frequency.

Thus, the positive effect of the use of the proposed device in comparison with the known one is to increase the device performance by approximately 25%, which is achieved due to the possibility of reallocating the subscriber's working cycle and reducing the loss of the subscriber's working time to waiting for an exchange. In addition, the use of three-state buffer registers permits a reduction in the equipment of the device, and the introduction of a reversible counter simplifies the control device. The introduction of the AND element allows the subscriber to monitor the status of the buffer registers. This ensures that the subscriber receives reliable information and increases the reliability of the exchange device. The introduction of a synchronization node for a reversible counter allows the device to operate at any frequency ratios between the computer and the subscriber.

Claims (1)

Formula A device for interfacing an electronic computer with a subscriber, containing a group of buffer registers, two pulse distributors, a reversible counter, two OR elements, a single pulse former, a decoder, a counter, a counter count input connected to the subscriber synchronization output, the output of the first element OR connected to the input is ready. subscriber's output, the outputs of the buffer registers of the group are connected to the information input of the subscriber, the information inputs of the buffer registers of the group are connected to the information output of the the computational computer, the group of outputs of the reversible counter is connected to the group of outputs of the first element OR and connected to the information input of the electronic computer, the group of outputs of the counter is connected to the group of inputs of the decoder whose output is connected to the installation input of the counter, the output of the former HMnyJibca is connected to the first the input of the second OR element, the output of which is connected to the clock input of the first pulse distributor, the group of outputs of which is connected to the control inputs group registers whose recording inputs are connected to the output group of the second pulse distributor, characterized in that, in order to increase speed, a synchronization node and a group of elements And are entered into it, the first clock input of the synchronization node is connected to the synchronization output of the electronic computer, the decoder output connected to the second clock input of the synchronization node, the first output of which is connected to the clock input of the second pulse distributor, the input of a single pulse shaper, summing to Odom down counter, subtractor 10 whose input is connected to the second input of the second OR element and the second output of the synchronization node, the subscriber's synchronization output is connected to the first inputs of the AND elements of the group, J5 whose second inputs are connected to the output group of the first pulse distributor, the read inputs of the buffer registers of the group are connected to the outputs of the corresponding elements 20 And groups. FI.1 dzie.g Phie. J