SU1751859A1 - Multichannel converter of series-to-parallel code - Google Patents

Abstract

The invention relates to computing and can be used in multi-channel digital information processing systems. The purpose of the invention is to expand the field of application of the converter. The converter contains a zero potential bus, a counter, triggers, de-multiplexers, multiplexers, NOT elements, summing unit, switch, register, decoder, distributor, element. The invention relates to computing technology and can be used in multichannel digital information processing systems. A serial to parallel converter is known that contains a clock pulse generator, counters, flip-flops, a register, distributors, pulse shapers, elements I. And elements, OR element, parity control unit. Signals of the beginning of the message, accompaniment, and sequential information are sent from the channels, respectively, to the triggers, which are polled by the counter via multiplexers. When sampling the channel, the counter addresses the corresponding cells in the registers and includes a pulse distributor that records the bits in the register and counts the received bits of the given channel using the sum block. , switch and register The accumulation of bytes in a parallel code is provided in another register, the contents of which is checked for parity by a con block The decoder detects the number of bits equal to the byte, and, via the elements, issues information readiness signals or an error signal. At the end of the channel bit processing cycle, the corresponding triggers are reset to zero through the demultiplexers to ensure that the following channel polling cycles are performed. A disadvantage of the known device is that it provides conversion of codes from only one channel, which limits the functionality and the area when device changes The closest to the invention is a serial to parallel converter that contains registers, a parity check block, a trigger, and

Description

counters, decoder, elements OR NOT, element NOT, multiplexer.

The known device is a single channel device that converts serial codes into parallel ones from only one direction of information transfer. For the use of the well-known device in multichannel systems, in which serial codes are transmitted in several directions, a known code converter is connected to each channel of the multichannel system. In this case, the overall information processing complex becomes much more complex, its reliability decreases, and hardware costs and costs increase. Thus, a disadvantage of the known code converter is the limited scope of its application.

The aim of the invention is to expand the field of application of the converter by converting serial codes into parallel, transmitted over several channels.

FIG. 1 shows a functional diagram of a multi-channel converter; in fig. 2 - distributor circuit; in fig. 3 - time diagrams of work.

The device contains a bus 1 zero potential, the first group of triggers 3, counter 2, the first demultiplexer A, the second group of triggers 5i-5n, the second demultiplexer b, the third group of triggers 7i-7n, the first, second and third multiplexers 8,9,10, element OR NOT 11, first element NOT 12, adder 13, switch 14, first register 15, decoder 16, distributor 17, first element AND 18, fourth multiplexer 19, element OR 20, second and third elements AND 21, 22, second register 23, parity check block 24, the second and third elements are NOT 25.26, the fourth and fifth elements S 27.28, message start inputs 29i-29n, tracking signals inputs 30i-30n, serial information inputs 31i-31n, inputs 32i-32 n of information receiving signals, converter address outputs 33, parallel information outputs 34, byte number outputs 35 , the output 36 readiness information, the output 37 of the error signal, the clock input 38 of the Converter.

The distributor 17 (FIG. 2) contains a decoder 39, a switch 40, a HE element 41 and a counter 42.

Blocks and device elements can be implemented, for example, on the following microcircuits: triggers 3,5,7 564ТМ2, sensor 2.38 - 564ИН1С multiplexers 8,9,10,19. demultiplexers 4,6 564KP2, decoders 16.39 - 564ID1, parity control block 24 - 564CA1, adder 13 - 564IM1, registers 15.23 - 564IR11, the other logic elements - on the 564th series chips. The switch 14 is made similar to the switch 40 of the distributor 17 (Fig. 2).

The device works as follows.

Each of the n channels served by the device has a specific trigger in the trigger groups 3,5,7, for example, the first channel triggers 3-1.5-1.7-1, the n-th channel triggers Зn, 5-n , 7-p. Each channel, before the start of the transmission of serial information, generates a pulse signal of the beginning of a message on the corresponding input 29. Each bit of the serial information of the channel is followed

a pulse signal - a request for a service channel, which is fed to its corresponding input 30. Information bits are log 0 or log. 1 - arrive at the corresponding inputs 31

In the initial state, the triggers are 3.5,

counter 2 is set to zero (the initial installation circuit is not shown in the diagram). In the absence of signals at the outputs of the trigger 3.5 no signals

at the outputs of multiplexers 8.9. In this case, a single signal is generated at the output of the OR-NOT 11 element, which enables the counting of pulses in the counter 2 from the clock input 38 and keeps in the zero state

the distributor counter 42 17. After applying the clock pulses to the input 38, the counter 2 begins to operate in a cyclic counting mode, and the outputs are multiplied through the multiplexers 8.9 and 10

triggers 2 5 and 7 respectively. When converting information, for example, the n-th channel, the latter exposes a pulse signal of the beginning of a message on input 29-n and turns on the corresponding trigger H-n. With

connected to the triggered trigger of the Zp multiplexer 8, a single signal is generated at the output of the latter, which prepares the opening element AND 18 and closes the element OR NOT 11.

the further counting in the counter 8, which maintains the state corresponding to the n-th channel number, is forbidden, and the signal from the reset input of the counter 38 of the distributor 17 is removed. In addition, the signal from the output

multiplexer 8 through the element 12 closes the switch 14 and sends a zero signal to the first input of the summing unit 13. Counter 2 connects multiplexer 9 to the 5-p trigger, multiplexer 10 to the trigger

7-p and addresses the inputs W and R in the registers

15,23 cells corresponding to the n-th channel. The summing unit 13 together with the switch 14 and the register 15 provide counting the number of bits for each channel. Register 15 is a group register, each channel in it corresponds to a certain cell, addressed by counter 2 to the W / R input and acting as a bit counter of this channel. The increment of the number of bits of this channel is carried out by summing the contents of this cell with the unit in one cycle using the summing unit 13, the sum of the bits is written into the cell through the switch 14 by a clock pulse fed to the C input of the register 15c of the second output of the distributor 17. the initial setting of the n-th channel cell, a zero code is written into it, which is ensured by locking the switch 14. Thus, the signal of the beginning of the n-th channel message sets to zero the corresponding cell of the number of register bits 15. After s minute signal from counter 42 outputs the reset valve 17 is turned on, performing the one-bit loop information. The counter 42 is filled with clock pulses from input 1. The state of counter 42 is decoded by the decoder 39 and selected through the switch 40 by inverse clock pulses from the output of the HE element 41. Since the nth channel has not yet set the information, the 5-n trigger is not on, at the output of the multiplexer 9, the signal is absent, the elements And 21, 22 are closed. The first pulse of the distributor 17 does not pass through the element 22, the second pulse arrives at the C-input of the register 15 and writes the zero code to the cell addressed by counter 2. The third pulse of the distributor 17 through the element 18 goes to the information input of the demultiplexer 4, which is addressed by the counter 2 to the trigger input trigger 3-p. The trigger 3-n on the front of the third pulse of the distributor 17 is set to zero, since its D-input is supplied with a zero signal from the common bus. After resetting the 3-p trigger to zero, a single output signal of the multiplexer 8 is removed, the OR-NOT 11 element is opened. At that, the distributor 17 is set to the zero state, and the counter 2 switches back to the clock counting mode and continues polling the triggers 3.5, 7 Similarly, the start signals of other channels are processed. Channel P through time T p Tr, where T is the period between the bits of the serial codes, n is the number of channels served by the device, Tr is the duration of one cycle of the distributor 17, sets the first bit of the serial code information according to

the input is 31-n and with a shift in time a tracking pulse along the input 30-n. The tracking impulse sets the trigger to 5 / n in one state, and the corresponding trigger 7-p is set to the log on the tracking pulse edge. About or log. 1 depending on the value of the nth channel information bit. When polling the enabled flip-flop 5-n, a single signal is generated at the output of multiplexer 9, which prepares the AND 21, 22 elements for opening and starts the distributor 17 through the OR-NOT 11 element and opens counter 2, which addresses the nth channel. Counter 2 connects the demultiplexer b to the C-input trigger 5-p. In this case, And 18 is closed by a zero signal from the output of multiplexer 8 and to the inputs of summing unit 13 and the control input of switch 4 is fed a single signal from the output of element NO 12. The first distributor pulse 17 goes through element And 22 to the clock input of group register 23. Register 23 serves for accumulation of parallel codes bytes for all channels, similarly to register 15, contains for each channel a cell addressed by counter 2 to the inputs W and R and intended for accumulation of the information byte of this channel. Due to the fuzzy connection with the output of register 23 to a group of its information inputs shifted by one bit, information is shifted by bits of this cell of the register in the process of its bit-by-bit recording and, thus, the conversion of serial information into parallel. Thus, for example, the first bit is recorded in the first bit of a cell. By the time the second bit is written, the first bit in the feedback circuit is fed from the first output of register 23 to the input of its second bit. When the second bit arrives, it is recorded in the first bit, and in the second bit, the first bit. In the next cycle, the third bit is written to the first bit, the second bit to the second bit, the first bit to the third bit, and so on. When the n-channel address is fed from counter 2 to the inputs and the P register 23, the n-th cell is sampled to simultaneously write code to it and read this code. The code is recorded in the cell by a pulse, which is fed to the C input of the register 23 from the output of the device element 22. Thus, the first pulse of the distributor 17 writes the current bit of the n-th channel and the resulting shifted byte into the corresponding cell of the register 23. The second pulse of the distributor 17 is fed to the C-input of the register 15, in which the counter of the n-th channel containing the zero

code. This code is fed to the inputs of the summing unit 13, which sums it with the unit supplied from the output of the element NOT 12. The sum with the output of the unit 13 through the switch 14 is fed to the D-inputs of the register 15 and the second pulse of the distributor 17 forms in the n-th cell of the register 15 the number of bits to receive on the nth channel (in this case, one bit).

Three lower bits with a register 15 output that determine the number of bits in a byte (8 bits) are continuously analyzed by the decoder 16. As long as the number of bits equal to a byte is not received on the nth channel, the output of the decoder the zero signal that closes the AND 27.28 elements and through the NOT 26 element prepares the AND 21 element for opening. The third distributor pulse 17 through the AND 21, OR 20 elements, demultiplexer 6 is fed to the clock input of the trigger 5 and sets it to zero. After resetting the flip-flop 5-p, the signal at the output of multiplexer 9 is removed, the distributor 17 is set to zero, and counter 2 again enters the counting mode. This completes the processing cycle of one bit of the n-th channel. The device works similarly when processing the subsequent bits of the l-ro and other channels.

After accumulating a byte in the nth cell of the register 23 for the nth channel and the number of bits equal to a byte, a signal is generated in the nth cell of the register 15 at the output of the decoder 16, which through the element HE closes the element 21 and prepares the element for opening And 27.28. The accumulated byte with the output of register 23 is checked for parity by block 24. At the correct parity of the byte, a signal is generated at the output of block 24, which opens the element 27 and the element NOT 25 closes the element 28 at the output. The information is ready, which is polled by all channels. Simultaneously with the output 33 of the device, the channel number is output, from the outputs 35 - the converted byte number, from the outputs 34 - the parallel information byte code. After receiving the parallel information byte of the nth channel, the corresponding input 32p issues an Information received signal, which through multiplexer 19 , the element OR 20, the demultiplexer 6 is applied to the clock input of the trigger 5n and sets it to zero. After that, the device, similarly to the one described, enters the polling mode of triggers 3,5,7.

If for some reason the channel has not set a signal for the received information, in the current operation cycle

five

0

five

0

the divider 17 at the fourth output after a certain threshold time, a signal is generated, which through the element OR 20, the demultiplexer 6 sets the zero trigger to zero, and the device continues polling for the triggers 3,5,7.

In the case of incorrect parity of the accumulated byte of information in the n-th cell of the register 23, the block 2-4 does not generate an output signal.

In this case, element 27 is closed, element 28 is opened through element 25, and an error signal is output on output 37, which is identified by the channel number outputs 33 and outputs 35 of the byte number. In this case, the channel can repeat the feeding of a serial byte code for its new conversion.

Thus, in the proposed converter, serial codes are converted into parallel, arriving through several channels serviced by the device in series, which simplifies the multichannel system scheme, reduces hardware costs and costs during its design and manufacture, and expands the device application area.

Claims (1)

Invention Formula A multichannel serial to parallel converter that contains a counter, the clock input of which is the clock input of the converter, the switch, the outputs of which are connected to the corresponding information inputs of the first register, the decoder, the parity check block, the second register, the OR-NOT element and the first element NOT, characterized in that in order to expand the scope of the converter, he introduced the trigger group distributor, demultiplexers, multiplexers, adder, AND elements, IL element AND, the second and third elements are NOT, the counter outputs are connected to the address inputs of multiplexers and demultiplexers, the write and read inputs of the first and the second registers and are the address outputs of the converter, the outputs of the first, second and third group triggers are connected to the information inputs of the first, second and third, respectively multiplexers, the information inputs of the fourth multiplexer are the signal inputs of the converter, the output is connected to the first input of the OR element, the output of the first multiplexer is connected to the first element NO, to the first the inputs of the OR-NOT element and the first AND element, the output of which is connected to the information input of the first demultiplexer, whose outputs are connected to the clock inputs of the first group triggers, the single inputs of which are the corresponding inputs of the beginning of the converter message, the output of the second multiplexer is connected to the second input of the OR element- Not both the first inputs of the second and third elements AND, the output of the second element AND connected to the second input of the element OR, the output of which is connected to the information input of the second demultipl An Xora whose outputs are connected to the clock inputs of the second group of flip-flops, the single inputs of which are combined with the clock inputs of the third group of the same trigger and are the corresponding inputs of the converter tracking signals, the information inputs of the first and second group triggers are connected to the third group trigger inputs are the inputs of the serial converter codes, the output of the third demultiplexer is connected to the first information input of the second register and the outputs of which are connected with its corresponding second data inputs, with an input control block and the parity are the respective data outputs of the transducer, the output of unit the parity check is connected to the first inputs of the fourth element itself AND, and through the second element of NOT - the fifth element AND whose outputs are respectively the information readiness signal output and the converter error signal output, the first register outputs are connected to the corresponding decoder inputs and the first inputs of the adder and are the byte number of the converter, the output of the first element is NOT connected to the control input of the switch and the second input of the adder, the outputs of which connected to the corresponding information inputs of the switch, the output of the decoder is connected directly to the second inputs of the fourth and fifth elements And through the third element NOT to the second input of the second element And the first to fourth outputs of the distributor are connected respectively to the second input of the third element And clock input of the first register combined second the input of the first element And the third input of the second element AND and the third input of the OR element, the output of the third element AND is connected to the clock input of the second register, the output of the OR element is NOT connected to the control input of the counter and the start input of the distributor, the clock input of which is connected to the clock input of the converter.  i & l