RU2034401C1 - Threshold element - Google Patents

Abstract

FIELD: automatic control and computer engineering. SUBSTANCE: threshold element has clock generator, 2p-channel scanning multiplexer, half-adder, pulse counter, p binary-code adder, threshold shaping unit, OR gate. In addition, threshold element is provided with p binary-code and threshold shaping unit and count pulse shapers are made in the form of half-adders. EFFECT: improved speed. 2 cl, 1 dwg

Description

 The invention relates to automation and computer technology and can be used to build various devices for processing discrete information.

 A threshold element is known that contains an output unit, a scanning multiplexer, connected by a counting input to a clock generator, information inputs with buses of unit positive weight, and an input with a counting input of a counting unit, a scanning multiplexer contains a p-channel parallel-to-serial code converter (p 1) a reversible drive, groups (p-1) of AND elements, an OR element, and a trigger, while the p-th output of the p-channel parallel-to-serial converter is connected to the r-th input of the ele OR, each i-th output of the p-channel parallel-to-serial code converter (i 1,2, p-1) is connected to the summing input of the i-th reversing drive, the first output of which is connected to the first input of the i-th AND element, the output connected to the subtracting input of the i-th reverse drive and to the i-th input of the OR element, the output of which is the output of the scanning multiplexer.

 This threshold element allows you to implement threshold functions with unit weights of the input variables. Its disadvantage is the low speed.

 The closest in technical essence and functionality to the claimed one is a threshold element [1] containing a clock pulse generator, a counting unit, a trigger and an OR element, a 2p + k-channel scanning multiplexer, p + k-1 drives, two groups of And elements, ( p-1) a block for generating counting pulses, two AND elements, two additional OR elements and a shaper of counting pulses, a 2p + k-channel scanning multiplexer connected to information inputs with input information buses, a clock input with a generator output torus of clock pulses, a stop output with a trigger input, a first output with an OR element input, an i-th output (i 2, p) with a first input of the (i-1) th counting pulse generation unit, (p + 1) -th output with the input of the first additional OR element, (p + i) -th with the output with the second input of the (i-1) -th block of the formation of counting pulses, the first and second outputs of the i-th block of the formation of counting pulses (i 1,2, p- 1) are connected respectively to the summing and subtracting counting inputs of the i-th drive, the first and second outputs of which are connected respectively to the inputs of the i-th element ntov And the second and first groups of elements And, the output of the i-th element And the first group is connected to the input of the second OR element and the third input of the i-th block of the formation of the counting pulses, and the outputs with the output of the clock pulse generator, the trigger output and the second outputs of the drives from the first to the (i-1) th, the output of the i-th AND element of the second group is connected to the input of the first OR element and the fourth input of the i-th counting pulse generation unit, and the inputs with the output of the clock pulse generator, trigger, and the first drives outputs from the first to (i-1) output The first and second OR elements are connected respectively to the first and second inputs of the counting pulse generator, the first and second outputs of which are connected to the summing and subtracting counting inputs of the drive, the output of which is connected to the output bus.

 This threshold element allows you to implement threshold functions with unit positive and negative weights. Its disadvantage is the low speed, especially when implementing threshold functions with unit positive weights.

 The aim of the invention is to increase the performance of the threshold logic element.

 This goal is achieved by the fact that, into a threshold logic element containing a clock pulse generator, connected by the output to the clock input of a 2p-channel scanning multiplexer, the information inputs of which are connected to the input information buses, the i-th output (i 1, p) with the first input i-th counter pulse generator, (p + i) -th output with the second input of the i-th counter pulse generator, p pulse counters and an OR element, the output of which is the output of the end of the device, an adder p of binary codes and a block of a threshold, and the counting pulse generators are made in the form of half-adders, the sum and transfer outputs are connected to the counting inputs of the first and second bits of the corresponding pulse counter, the outputs of the pulse counters are connected to the inputs of the adder p of binary codes, connected by the outputs to the inputs of the threshold forming unit, the output of which is connected with the information output of the threshold element and the input of the OR element, the second input of which is connected to the stop output of the scanning multiplexer, and the output with the output of the end of work stroystva.

 All the characteristics indicated in the characterizing part of the claims are new and significant, since in the known technical solutions there are no signs distinguishing the claimed technical solution.

 The introduction of the adder r of binary codes and the threshold generation unit allows the result to be generated without recounting the contents of the counters from the second to the rth to the first counter, which improves performance, since the formation of the result is carried out no later than at the end of the 2p-channel scanning multiplexer, t .e. the operation cycle of the device does not exceed n / 2p cycles, where n is the number of inputs of the device, while in the prototype device the operation cycle reaches n / 2p + (p-1) ˙n / 2p.

 The drawing shows a structural diagram of a threshold logic element.

 The threshold element contains a clock pulse generator 1, a 2p-channel scanning multiplexer 2, and half-adders 3.1-3.r. counters 4,1-4.p pulses, adder p of binary codes 5, threshold forming unit 6, OR element 7, input information buses 8, information output 9, output 10 of the end of operation.

 The scanning multiplexer 2 is connected by information inputs with input information buses 8, a clock input with the output of a clock pulse generator 1, the ith output (i 1,2, p) with the first input of the i-th half-adder 3.i, (p + i) - m output with the second input of the i-th half-adder, the output of the sum of the i-th half-adder is connected to the counting input of the counter 4.i, and the transfer output with the counting input of the second bit of the counter 4.i, the outputs of which are connected to the group of inputs of the adder 5 binary codes 5, connected by outputs to the inputs of block 6 of the formation of the threshold, the output of which is Inonii 9 with data output device and an input of the OR gate 7 whose second input is connected to the output stop of the scanning of the multiplexer, and the output from the output end of the device.

 The multi-channel scanning multiplexer can be implemented as a prototype device in the form of a pulse distributor, the outputs of which are connected to the first inputs of the elements And 2p groups (2p the number of channels of the multiplexer), the second inputs of the elements And of each group are the inputs of the device of the corresponding group (multiplexer channel), and the outputs are connected to the inputs of the OR element, the output of which is the corresponding output of the scanning multiplexer, the clock input of the pulse distributor is the clock input of the scanning mul typlexer, and the output of the last bit of the pulse distributor is the stop output of the scanning multiplexer.

 The multi-channel scanning multiplexer can also be made in the form of 2p shift registers connected by information inputs to the information inputs of the scanning multiplexer, clock inputs with its clock input, and transfer outputs with the outputs of the scanning multiplexer, the inverse outputs of each shift register are connected to the inputs of its element And, and the outputs of the latter with the inputs of the element And, the output of which is the stop output of the scanning multiplexer, the recording permission entries of the shift registers are connected to the input write multiplexer scanning.

разрядов. Он может иметь любую известную схемную реализацию счетчика (см. например, Букреев И.Н. Мансуров Б.М. и Горячев В.И. Микроэлектронные схемы цифровых устройств. М. Сов. радио, 1975, с.162-175). Отличием используемого счетчика является наличие второго счетного входа, подключаемого к счетному входу второго разряда счетчика параллельного переносу из первого разряда. Такой счетчик может быть выполнен, например, на Т_t триггерах, соединенных последовательно, причем выход переноса каждого триггера соединен с входом переноса следующего триггера (см. с.170, рис. 5.6 указанной книги), выход переноса первого триггера соединен с входом переноса (счетным входом) второго триггера через элемент ИЛИ, второй вход которого является вторым счетным входом счетчика.Each counter 4.i is a summing counter on ≅ [log ₂ (K) +1] k =

discharges. It can have any known counter circuit implementation (see, for example, Bukreev I.N. Mansurov B.M. and Goryachev V.I. Microelectronic circuits of digital devices. M. Sov. Radio, 1975, p.162-175). The difference between the used counter is the presence of a second counting input connected to the counting input of the second category of the counter parallel to the transfer from the first category. Such a counter can be performed, for example, on T _t triggers connected in series, with the transfer output of each trigger connected to the transfer input of the next trigger (see p. 170, Fig. 5.6 of this book), the transfer output of the first trigger is connected to the transfer input ( counter input) of the second trigger through the OR element, the second input of which is the second counter input of the counter.

The adder p of binary codes can be made in the form of log ₂ p [groups of series-connected adders of binary numbers, the width of the adders of the ith group is [log ₂ (k) +1] + i-1. The inputs of the adders of the first group are connected to the outputs of the pairs of counters 4, the inputs of the adders of the i-th group (i 2, log ₂ p [) are connected to the corresponding outputs of the two adders of the previous groups, the outputs of the adder of the last group are the outputs of the block.

 In addition, the adder p of binary codes can have any of the known circuit implementations, for example, as a device according to a.s. 920707.

2^i-1α_i i 1, 2,u.The threshold forming unit 6 implements a threshold function with weights of the inputs 2 ⁱ and a threshold A ^l ≥ A, where A is the threshold of the threshold equilibrium function realized by the device. Let the binary representation of the threshold And ^l is equal to
A ′ =

2 ^i-1 α _i i 1, 2, u.

Let α ₁ α ₂ α _e-1 0, and α _e 1. The inputs of the block, starting from the e-th to the j-th, such that α _e α _{e + 1} α _j 1, and α _{j + 1} 0, connected to the inputs of the element And, the output of which, as well as the inputs of the block, starting from the (j + 1) th to the i th, such that α _{j + 1} α _{j + 2} α _i 0, and α _{i + 1} 1 are connected to the inputs of the OR element, the output of which, as well as the inputs of the block, starting from the (i + 1) th to the l th, such that α _{i + 1} α _{i + 2} α _l 1 and α _{l + 1} 0 are connected to the inputs of the AND element, the output of which, as well as the inputs of the block, starting from the (l + 1) th and ending with the input with number t, such that α _{l + 1} α _{l + 2} α _t 0, and α _{t + 1} 1, connected to the inputs of the OR element, and so on, until all inputs are combined block 6 of the formation of the threshold. If α _u 1, the last element is AND, if α _u 0, the last is the element OR. In the particular case of A ^l 2 ^p , the threshold formation block is made in the form of an OR element connected by inputs to the inputs of the block from (p + 1) th to u th. In the particular case of α ₁ α ₂ α _p-1 0а α, _р α _{p + 1} α _u 1, the threshold formation block is made in the form of an AND element connected by inputs to the inputs of the block from the rth to the uth. With A ^l 2 ^u-1 , the threshold 6 block is made in the form of a communication line from its u-th input to the output.

 The functioning of the proposed threshold element is as follows.

/. При выполнении 2р-канального сканирующего мультиплексора на регистрах сдвига входной код с входных шин 8 записан в регистры сдвига путем подачи разрешающего сигнала на вход разрешения записи мультиплексора 2. Блок формирования порога реализует пороговую функцию с порогом A′= A+

q_i.In the initial state, a 2p-channel scanning multiplexer 2 and counters 4.1-4. p reset. Moreover, the code of the number q _i / 0 ≅ q _i <2 ^[log 2 ^{(] n / p [) + 1]} -

/. When executing a 2p-channel scanning multiplexer on the shift registers, the input code from the input buses 8 is written into the shift registers by supplying an enable signal to the write enable input of the multiplexer 2. The threshold generating unit implements the threshold function with the threshold A ′ = A +

q _i .

 Upon receipt of clock pulses from the output of the clock generator 1 to the clock input of the 2p-channel scanning multiplexer 2, the latter converts the parallel code supplied from the input information buses 8.i to the information inputs of the ith and (p + i) -th group (scanning channels multiplexer) in the sequence of pulses at its ith and (p + 1) -th outputs. Moreover, during the operation of the 2p-channel scanning multiplexer 2, the number of pulses is formed at its i-th output (i 1,2, 2p), equal to the number of unit signals at the corresponding group of inputs.

x_i < A. При этом по окончании работы 2р-канального сканирующего мультиплексора 2 на его выходе останова появляется единичный сигнал, который поступает через элемент ИЛИ 7 на выход 10 конца работы порогового элемента. Результат снимается с информационного выхода 9 порогового элемента, на котором при этом будет нулевой сигнал, поскольку сумма кодов на выходах счетчиков 4.i равна

q_i +

x_i < A^l, что вызывает на выходе блока 6 формирования порога нулевой сигнал.The pulses from the outputs of the i-th and (p + i) -th scanning multiplexer 2 are fed to the inputs of the half-adder 3.i. If a pulse arrives at one of its inputs, this causes a pulse at its output of the sum connected to the counting input of the first digit of the counter 4.i, to the contents of which a unit is added. If pulses arrive at both inputs of the half-adder 3.i, this causes a pulse at its transfer output connected to the counting input of the second discharge of counter 4. i, to the content of which is added the number two. The work continues in this way until the polling of all input information buses, which requires n / 2p [clock cycles, where n is the number of inputs of the threshold element, if

x _i <A. At the same time, at the end of the 2p-channel scanning multiplexer 2, a single signal appears at its stop output, which enters through the OR element 7 to the output 10 of the end of the threshold element. The result is taken from the information output 9 of the threshold element, on which there will be a zero signal, since the sum of the codes at the outputs of the counters 4.i is

q _i +

x _i <A ^l , which causes the output of the block 6 of the formation of the threshold zero signal.

x_i≥ A, то работа порогового элемента происходит в описанном выше порядке до тех пор, пока на выходах сканирующего мультиплексора 2 не будет сформировано не менее А импульсов, т.е. на опрошенных входных информационных шинах 8 имеется не менее А единичных логических сигналов. При этом в счетчиках 4. i будет записан код числа (N_i + q_i), где N_i число импульсов, сформированных на выходах i и (P+ i) сканирующего мультиплексора 2 за время его работы. Коды чисел с выходов счетчиков 4.i суммируются сумматором р двоичных чисел 5, на выходе которого будет код числа

N_i +

q_i≥ A^l, что вызовет на выходе блока 6 формирования порога единичный сигнал, поступающий на информационный выход 9 порогового элемента и через элемент ИЛИ 7 на выход конца работы 10.If

x _i ≥ A, then the operation of the threshold element occurs in the order described above until at least A pulses are generated at the outputs of the scanning multiplexer 2, i.e. on the polled input information buses 8 there are at least A single logical signals. Moreover, the counters 4. i will record the code of the number (N _i + q _i ), where N _{i is the} number of pulses generated at the outputs i and (P + i) of the scanning multiplexer 2 during its operation. The codes of the numbers from the outputs of the counters 4.i are summed by the adder p of binary numbers 5, the output of which will be the code of the number

N _i +

q _i ≥ A ^l , which will cause a single signal at the output of the threshold forming unit 6, which arrives at the information output 9 of the threshold element and through the OR element 7 to the output of the end of work 10.

x_i< A на выходе порогового элемента формируется нулевой логический сигнал, а при

x_i ≥ A единичный.Thus, with

x _i <A at the output of the threshold element, a zero logic signal is generated, and when

x _i ≥ A is single.

x_i< A сигнал на выходе 10 конца работы устройства формируется только в течение тактового импульса или тактового импульса и последующей паузы в зависимости от выполнения распределителя импульсов и используемого в качестве выхода останова выхода распределителя.The result is read from the output of the 9th threshold element during the duration of the clock pulse and the subsequent pause until the arrival of the next clock pulse, if the 2p-channel scanning multiplexer is made on the pulse distributor. If the scanning multiplexer is made on shift registers, then the reading time is not limited, since at the end of the operation cycle the shift registers are zeroed and there will be a single signal at its stop output. When performing a 2p-channel scanning multiplexer on the pulse distributor, then at

x _i <A, the signal at the output 10 of the end of the device operation is generated only during a clock pulse or a clock pulse and subsequent pause, depending on the execution of the pulse distributor and the distributor output used as a stop output.

 In both cases, the execution of the 2p-channel scanning multiplexer 2, the signals at its outputs connected to the inputs of the half adders 3.i take place during the duration of the clock pulses at the output of the generator 1, and upon completion of the survey of all input buses, i.e. through n / p2 [clock cycles, the scanning multiplexer 2 will self-block and then generate no pulses at its outputs.

 To resume the cycle of operation of the threshold element, all blocks must be reset.

 Thus, the cycle of the proposed threshold element does not exceed n / p2 [cycles, which is significantly less than in the prototype device. Therefore, the proposed threshold element has a higher performance.

N_i ^-, где N_i ^- число входных информационных шин отрицательного веса, а значение A^l для блока 6 формирования порога выбирается равным A^l A + N^- +

q_i.The proposed threshold element allows you to implement threshold functions with unit positive and negative input weights. In this case, input information buses of negative weight are fed to the information inputs of the 2p-channel scanning multiplexer 2 through inverters, and q _i codes are recorded in the initial state 4. _i , and N ^-

N _i ^- , where N _i ^{is the} number of input information buses of negative weight, and the value of A ^l for the threshold forming unit 6 is chosen equal to A ^l A + N ^- +

q _i .

Claims (1)

 A THRESHOLD ELEMENT containing a clock generator connected to the clock input of a 2p-channel scanning multiplexer, the information inputs of which are connected to the input information buses, the i-th output (i 1,2, p) with the first input of the i-th count pulse generator, (p + i) -th output with the second input of the i-th counting pulse shaper, p pulse counters and an OR element, the output of which is the element termination output, characterized in that, in order to improve performance, an adder P of binary codes is introduced into it and a threshold generation unit, wherein the counting pulse generators are made in the form of half-adders, the sum and transfer outputs of which are connected to the counting inputs of the first and second bits of the corresponding pulse counter, the outputs of the pulse counters are connected to the inputs of the adder P of binary codes, connected by the outputs to the inputs of the threshold forming unit, the output of which is connected to the information output of the threshold element and the input of the OR element, the second input of which is connected to the stop output of the 2p-channel scanning multiplex litter.

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