RU2374672C1 - Device for construction of programmable digital microprocessor systems - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: device for construction of programmable digital microprocessor systems, comprising input unit, receiving signals from sensors and generating binary code at its outlet, output unit for recording and storage of received values of binary codes coming from multichannel operational and switching-computing units, where arithmetical and logical operations are performed over binary codes, programmable unit for storage of device operation program, main memory unit, unit of synchronisation, providing for stable operation of device, system of communication for matching of input and output signals between according units, logical module, providing for operation of cyclic shift of binary codes, where unit of program selection is introduced, comprising three electronic switches, permanent memory, multidigit pulse counter, decoder, elements AND, OR with according connections, and scheme fragments F1…Fn are introduced into multichannel operational unit by number of logical channels, elements OR or EXCLUSIVE OR with defined connections.

EFFECT: device simplification, improvement of its functional resources and efficiency.

14 dwg

Description

The proposed device is used to build programmable controllers and systems of logic-program control and regulation of technological objects in various industries and in transport, as well as means of solving logical problems.

A device is known that contains an input unit that receives signals from sensors and generates a specific binary code at its output, an output unit for recording and storing the results obtained from multichannel operational and switching-computing units, a program unit where the program of the device’s operation is stored, an operational unit memory for storing intermediate results of calculations, synchronization block, conditional transition block [1].

The disadvantage of this device is the functional limitedness and relatively low speed due to the large number of necessary clock cycles and the lack of accelerated transfer when calculating arithmetic functions.

The most technically closest is a device containing an input unit that receives signals from sensors and generates a specific code at its output, an output unit for storing the results received from a multi-channel operating and switching-computing units, a program unit where the device’s program of work is stored, an operational unit memory for storing intermediate results of calculations, a synchronization unit, an accelerated transfer unit with corresponding links [2].

The disadvantage of this device is its relatively complex structure, functional limitations due to the impossibility of accessing repetitive operations depending on the results of previous calculations, and relatively low speed due to the large number of clock cycles required for arithmetic and other operations.

The aim of the invention is to simplify the device, increase its functionality and speed.

,

,

, где

и

являются входами логического модуля ЛМ и связаны с соответствующими командными шинами программного блока, а С', С'', С°, С''' - это выходы логического модуля ЛМ и соединены выходом С''' с первым входом шестого элемента ИЛИ многоканального операционного блока, а также с соответствующими входами модулей сдвига разрядов МСР в каждом логическом канале, причем модуль сдвига разрядов МСР1 находится во всех логических каналах, кроме первого и последнего, и реализует логические функции

,

, где У'1 и У'2 являются выходами модуля МСР1 и связаны с третьим и четвертым входами первого элемента ИЛИ данного и последующего логических каналов, переменные b', b'', С', C'', t1 являются входными сигналами для МСР1, причем b',b'' поступают с выходов первых счетных триггеров данного и последующего логических каналов. С' и C'' поступают с выходов логического модуля ЛМ, t1 поступает с выхода элемента ИЛИ-НЕ многоканального операционного блока, модуль МСР2 в первом логическом канале реализует логические функции

,

и

где У1, У2 и У3 служат выходами модуля МСР2 и связаны с третьим и четвертым входами первого элемента ИЛИ первого логического канала и с четвертым входом первого элемента ИЛИ второго логического канала, а b1, b2, С', С'', С°, t1 являются входами модуля МСР2 и соединены с выходами первых счетных триггеров первого и второго логических каналов, с тремя выходами логического модуля ЛМ и с выходом элемента ИЛИ-НЕ многоканального операционного блока, модуль МСР3 вычисляет логические функции У1'''=bn·С''·t1 где сигнал У1''' поступает с выхода модуля МСР3 на третий вход первого элемента ИЛИ последнего логического канала, сигналы bn, С'', t1, поступают на входы модуля МСР3 соответственно с выхода первого счетного триггера последнего логического канала, с выхода логического модуля ЛМ и с выхода элемента ИЛИ-НЕ многоканального операционного блока, где управляющий вход электронного выключателя связан с выходом седьмого элемента ИЛИ, три входа которого подключены к двум соответствующим выходам первого дешифратора и к определенному выходу дешифратора блока выбора программ, второй вход шестого элемента ИЛИ связан с командной шиной программного блока, выход девятого элемента И соединен с первыми входами четвертых элементов И в каждом логическом канале вторые входы четвертых элементов И каждого логического канала вместе с информационными выходами электронного выключателя многоканального операционного блока связаны с общими шинами системы связи, а выходы четвертых элементов И в каждом логическом канале соединены с первыми входами элементов ИСКЛЮЧАЮЩЕЕ ИЛИ, общие шины также подключены к выходам первого и второго электронных ключей системы связи и к соответствующим входам блока оперативной памяти и выходного блока, входы первого и второго электронных ключей связаны с определенными выходами входного блока и блока оперативной памяти, управляющие входы первого и второго электронных ключей, блока оперативной памяти и выходного блока соединены с соответствующими выходами логического элемента системы связи, три входа которого объединены с соответствующими тремя входами первого дешифратора многоканального операционного блока и с тремя выходами программного блока, в коммутационно-вычислительном блоке входы элемента И-НЕ соединены с пятым выходом дешифратора и прямым выходом ячейки памяти, а выход связан с третьими входами четвертых элементов И всех логических каналов и с третьим входом первого элемента И блока оперативной памяти, а также с третьим входом элемента И выходного блока, шестой элемент И подключен входами к шестому выходу дешифратора и прямому выходу ячейки памяти, а выходом к первому входу элемента И счетчика импульсов программного блока, второй вход указанного последним элемента И связан с соответствующим выходом блока синхронизации, а выход подключен к управляющему входу электронного ключа счетчика импульсов блока программ, первый счетный триггер в каждом логическом канале имеет одинаковую схему и содержит ячейку памяти, первый и второй элементы ИЛИ, первый и второй элементы И, причем выходы первого и второго элементов И связаны с входами первого элемента ИЛИ, выход которого соединен с информационным входом ячейки памяти, инверсный выход последней подключен к первому входу второго элемента И, второй вход которого соединен с выходом второго элемента ИЛИ, входы последнего связаны с входом элемента ИЛИ-НЕ многоканального операционного блока и с соответствующей командной шиной программного блока, входы первого элемента И первого счетного триггера подключены к определенной командной шине программного блока и к выходу третьего элемента ИЛИ многоканального операционного блока, прямые выходы ячейки памяти во всех счетных триггерах являются их выходами и связаны с определенными входами модулей сдвига разрядов МСР1, МСР2 и МСР3 в соответствующих логических каналах, вход управления ячейки памяти первого счетного триггера является его счетным входом и соединен с выходом третьего элемента И в каждом логическом канале, а вход сброса в «0» указанной ячейки памяти одновременно служит входом сброса в «0» первого счетного триггера и подключен во всех логических каналах к выходу пятого элемента И многоканального операционного блока, вновь введены в многоканальный операционный блок элемент ИСКЛЮЧАЮЩЕЕ ИЛИ и восьмой элемент ИЛИ, который первым и вторым входами связан с вторым и третьим выходами второго дешифратора, а выходом соединен с первым входом шестого элемента И, входы элемента ИСКЛЮЧАЮЩЕЕ ИЛИ подключены к определенной командной шине и к первой Т1 шине из числа общих шин системы связи, а выход связан с вторым входом пятого элемента ИЛИ, n одинаковых схемных фрагментов Ф1…Фn по числу логических каналов, каждый схемный фрагмент связан с соответствующим логическим каналом и содержит два логических элемента ИЛИ и ИСКЛЮЧАЮЩЕЕ ИЛИ, причем первый, второй и третий входы элемента ИЛИ связаны с выходом первого элемента ИЛИ многоканального операционного блока, с вторым входом второго элемента И соответствующего логического канала и с соответствующим выходом дешифратора коммутационно-вычислительного блока, а выход соединен с первым входом элемента ИСКЛЮЧАЮЩЕЕ ИЛИ, второй вход которого подключен к выходу первого счетного триггера соответствующего логического канала, а выходы элементов ИСКЛЮЧАЮЩЕЕ ИЛИ являются выходами соответствующих схемных фрагментов и соединены с информационными входами электронного выключателя и управляемого элемента многоканального операционного блока, второй управляющий вход управляемого элемента связан с определенным выходом программного блока, введен блок выбора программ состоящий из первого, второго и третьего электронных ключей, многоразрядного счетчика импульсов, постоянного запоминающего устройства ПЗУ, первого и второго элементов И, дешифратора, элемента ИЛИ, причем первый электронный ключ соединен информационными входами с общими шинами Т1…Tn системы связи, а своими выходами с установочными входами многоразрядного счетчика импульсов, выходы которого подключены к соответствующим входам постоянного запоминающего устройства ПЗУ, своими выходами связанного с информационными входами второго и третьего электронных ключей, выходы которых соединены соответственно с командными и адресными шинами программного блока, входы первого элемента И связаны с первым выходом дешифратора и с определенным выходом блока синхронизации, а выход соединен с управляющим входом первого электронного ключа, входы второго элемента И подключены к выходу элемента ИЛИ и к определенному выходу блока синхронизации, а выход связан со счетным входом многоразрядного счетчика импульсов, входы элемента ИЛИ соединены с вторым и третьим выходами дешифратора, которые подключены и к управляющим входам соответственно второго и третьего электронных ключей, три входа дешифратора соединены с двумя определенными командными шинами программного блока и с прямым выходом ячейки памяти коммутационно-вычислительного блока.To this end, a device for constructing programmable microprocessor systems containing an input unit that receives signals from sensors and generates a specific code at its output, an output unit for recording the values of codes coming from all logical channels to memory cells, and transmitting them through digital-to-analog converters to electronic devices and electric drive mechanisms, a program unit, a RAM unit, a synchronization unit and a switching and computing unit consisting of AND-OR elements, an EXCLUSIVE element MORE OR, of five AND elements, memory cells, OR and NOT elements, while the first inputs of two AND AND-OR elements are connected respectively to the third and fourth outputs of the decoder, and the second inputs are connected to the output of the input block connected by the first and second groups of inputs with by the group of information outputs of the control object and with the group of address outputs of the program block, as well as to the output of the RAM block, the output of the AND-OR element is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to a specific output of of the gram block, the output of the EXCLUSIVE OR element is connected to the first input of the third AND element, connected by the second input to the corresponding output of the synchronization unit, and by the output to the control input of the memory cell, the information input of which is connected to the output of the OR element, the second input of the last connected to the output of the fifth AND element , the second input of which is connected to a certain bus of the program unit, the first input of the fifth AND element is connected to the output of the NOT element, and the input of the latter is connected to the second input of the fourth AND element and with bus, the first input of the fourth AND element is connected to the inverse output of the memory cell, and its output is connected to the first input of the OR element, the direct output of the memory cell is connected to the information inputs of the output block and the RAM block, the first inputs of the first and second elements AND are connected to the first and second outputs of the decoder, their second inputs are combined and connected to the corresponding outputs of the synchronization block, and the outputs are connected to the corresponding inputs of the output block and the RAM block for board for recording information, a multi-channel operating unit containing a controlled element, nine AND elements, seven OR elements, the first and second decoders, a controlled memory cell, a controlled trigger, an electronic switch, OR-NOT, NOT elements, an EXCLUSIVE OR element and n parallel logical channels having the same structure, each of which contains an EXCLUSIVE OR element, four AND elements, two OR elements, two countable triggers, while in each logical channel of a multichannel operational block the output of the EXCLUSIVE OR logic element is connected to the first input of the first OR element, the second input of which is connected to the output of the second AND element, connected by the second input to the first input of the first AND element, and the output of the first OR element is connected to the first input of the third AND element, the output of the last by the counting input of the first counting trigger, the output of which is connected to the second input of the first AND element and to the counting input of the second counting trigger, the output of the latter is connected to the first input of the second OR element, the second input of which o is connected to the output of the first AND element, while in the multi-channel operating unit the output of the first OR element is connected to the second inputs of the EXCLUSIVE OR logical channels, the first and second inputs of the first OR element are connected respectively to the outputs of the first and seventh AND elements, and two inputs of the first element And connected to one of the outputs of the second decoder and the output of the third OR element, the inputs of which are connected to two corresponding outputs of the first decoder, the first and second inputs of the second AND element are connected with one of the outputs of the synchronization unit and with a specific output of the first decoder, and the output is connected to the control input of the controlled trigger, the first input of the second OR element is connected to the output of the first EXCLUSIVE OR element, and the second input is connected to the output of the third AND element, the inputs of which are connected to the corresponding the output of the second decoder and the output of the first element NOT, whose input is connected to the output of the third element OR, the first input of the seventh element And is connected to the corresponding output of the second decoder, and the second the inputs of the sixth and seventh AND elements are associated respectively with direct and inverse outputs of the controlled memory cell, the information input of which is connected to the output of the second OR element of the discrete DM module, and the control input of the controlled memory cell is connected with the output of the fourth AND element, the first input of which is connected together with the first the inputs of the second elements AND of all logical channels to the corresponding command bus of the program unit, the second input of the fourth element And together with the second inputs of the third elements AND of all x channels are connected to a specific output of the synchronization block, in the multi-channel operation block, the information input of the controlled trigger is connected to the direct output of the controlled memory cell, the inverse output of the controlled trigger is connected through one of the common buses of the communication system to the output block, the control input of the controlled element is connected to a specific command bus program block and with the first input of the fifth element OR, the output of the latter is connected to the first input of the ninth element AND, in the switching and computing unit ne the first inputs of the third and fourth elements AND of the AND-OR element are connected to the corresponding two outputs of the first decoder, and the second inputs are connected to the output of the managed element of the multichannel operational block and the output of the second OR element of the last logical channel, the inputs of the first and second decoders of the multichannel operational block are connected to corresponding command buses of the software unit, the output of the second OR element of the first logical channel is connected to the second input of the second element AND of the second logical Nala, the output of the second OR gate of the second logical channel is connected to a second input of the second element and the third logical channel etc. to the last logical channel, the second input of the second AND element of the first logical channel is connected to the output of the second OR element of the multi-channel operating unit, where the second input of the ninth AND element is connected to the output of the third OR element, the inputs of the eighth AND element are connected to the outputs of the synchronization unit and the sixth OR element, and the output is connected to the first input of the fourth OR element, the output of which is connected to the reset inputs at “0” of the second countable triggers of all logical channels, the inputs of the fifth AND element are connected to a certain com software bus and the corresponding output of the synchronization block, and the output is connected to the second input of the fourth OR element and to the reset inputs at “0” of the first countable triggers of all logical channels, a communication system containing common buses, first and second electronic keys, a logical element, generating signals at its outputs is similar to the first four outputs of the first decoder of a multi-channel operating unit, the logical module LM whose structure and its functioning is determined by logical functions

,

,

where

and

are the inputs of the logical module LM and are connected with the corresponding command buses of the software unit, and C ', C'', C °, C''' are the outputs of the logical module LM and are connected by the output C '''to the first input of the sixth element OR multichannel operating block, as well as with the corresponding inputs of the modules of the shift bits MCP in each logical channel, and the module shift bits MCP1 is in all logical channels except the first and last, and implements the logical functions

,

, where Y'1 and Y'2 are the outputs of the MCP1 module and are connected with the third and fourth inputs of the first OR element of the given and subsequent logical channels, the variables b ', b'',C', C '', t1 are the input signals for MCP1 , and b ', b''come from the outputs of the first countable triggers of this and subsequent logical channels. C 'and C''come from the outputs of the logical module LM, t1 comes from the output of the OR-NOT element of the multi-channel operating unit, the module MCP2 in the first logical channel implements the logical functions

,

and

where Y1, Y2 and Y3 serve as outputs of the MCP2 module and are connected with the third and fourth inputs of the first OR element of the first logical channel and with the fourth input of the first OR element of the second logical channel, and b1, b2, С ', С'', С °, t1 are the inputs of the MCP2 module and are connected to the outputs of the first counting triggers of the first and second logical channels, with the three outputs of the LM logical module and with the output of the OR-NOT element of the multichannel operating unit, the MCP3 module calculates the logical functions U1 '''= bn · C''· t1 where the signal U1 '''comes from the output of the MCP3 module to the third the course of the first OR element of the last logical channel, signals bn, С '', t1, are fed to the inputs of the MCP3 module, respectively, from the output of the first counting trigger of the last logical channel, from the output of the logical module LM and from the output of the OR-NOT element of the multi-channel operating unit, where the control the input of the electronic switch is connected to the output of the seventh OR element, the three inputs of which are connected to two corresponding outputs of the first decoder and to a specific output of the decoder of the program selection block, the second input of the sixth element OR connected to the command bus of the software unit, the output of the ninth element AND is connected to the first inputs of the fourth elements And in each logical channel, the second inputs of the fourth elements And of each logical channel together with the information outputs of the electronic switch of the multi-channel operating unit are connected to the common buses of the communication system, and the outputs of the fourth elements And in each logical channel they are connected to the first inputs of EXCLUSIVE OR elements, common buses are also connected to the outputs of the first and second electronic keys of the systems s of communication and to the corresponding inputs of the RAM block and the output block, the inputs of the first and second electronic keys are associated with specific outputs of the input block and the RAM block, the control inputs of the first and second electronic keys, the RAM block and the output block are connected to the corresponding outputs of the logic element a communication system, the three inputs of which are combined with the corresponding three inputs of the first decoder of the multi-channel operating unit and with three outputs of the program unit, in the switch in the computational unit, the inputs of the AND element are connected to the fifth output of the decoder and the direct output of the memory cell, and the output is connected to the third inputs of the fourth elements AND of all logical channels and the third input of the first element AND of the RAM block, as well as to the third input of the AND element of the output unit, the sixth element AND is connected by inputs to the sixth output of the decoder and the direct output of the memory cell, and by the output to the first input of the element And the pulse counter of the program unit, the second input of the last element AND indicated by is connected to the corresponding output of the synchronization block, and the output is connected to the control input of the electronic key of the pulse counter of the program block, the first counting trigger in each logical channel has the same circuit and contains a memory cell, the first and second elements OR, the first and second elements AND, and the outputs of the first and second AND elements are connected to the inputs of the first OR element, the output of which is connected to the information input of the memory cell, the inverse output of the latter is connected to the first input of the second AND element, the second input of which is connected with the output of the second OR element, the inputs of the latter are connected to the input of the OR element of the multichannel operating unit and with the corresponding command bus of the program unit, the inputs of the first AND element of the first counting trigger are connected to a specific command bus of the program unit and to the output of the third OR element of the multichannel operational unit, direct outputs of the memory cell in all counting triggers are their outputs and are associated with specific inputs of the modules of the shift modules MCP1, MCP2 and MCP3 in the corresponding logical channels lah, the control input of the memory cell of the first counting trigger is its counting input and is connected to the output of the third AND element in each logical channel, and the reset input at “0” of the indicated memory cell simultaneously serves as the reset input at “0” of the first counting trigger and is connected in all logical channels to the output of the fifth element AND multichannel operating unit, the element EXCLUSIVE OR and the eighth element OR, which is connected to the second and third outputs of the second and third inputs by the first and second inputs of the encoder, and the output is connected to the first input of the sixth AND element, the inputs of the EXCLUSIVE OR element are connected to a specific command bus and to the first T1 bus from among the common buses of the communication system, and the output is connected to the second input of the fifth OR element, n are the same circuit fragments F1 ... Фn according to the number of logical channels, each circuit fragment is associated with a corresponding logical channel and contains two logical elements OR and an exclusive OR, with the first, second and third inputs of an OR element connected to the output of the first OR element of a multi-channel op radio unit, with the second input of the second AND element of the corresponding logical channel and with the corresponding output of the decoder of the switching and computing unit, and the output is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the output of the first counting trigger of the corresponding logical channel, and the outputs of the EXCLUSIVE OR elements are the outputs of the corresponding circuit fragments and are connected to the information inputs of the electronic switch and the controlled element of the multi-channel operating block, the second control input of the controlled element is associated with a specific output of the program block, the program selection block is introduced consisting of the first, second and third electronic keys, a multi-bit pulse counter, read-only memory ROM, the first and second AND elements, the decoder, the OR element, and the first the electronic key is connected by information inputs to the common buses T1 ... Tn of the communication system, and by its outputs with the installation inputs of a multi-bit pulse counter, the outputs of which are connected to the corresponding inputs of the read-only memory ROM, its outputs associated with the information inputs of the second and third electronic keys, the outputs of which are connected respectively to the command and address buses of the software unit, the inputs of the first element And are connected to the first output of the decoder and to a specific output of the synchronization unit, and the output is connected with the control input of the first electronic key, the inputs of the second AND element are connected to the output of the OR element and to a specific output of the synchronization unit, and the output is connected n with the counting input of a multi-bit pulse counter, the inputs of the OR element are connected to the second and third outputs of the decoder, which are connected to the control inputs of the second and third electronic keys, respectively, the three inputs of the decoder are connected to two specific command buses of the program unit and with the direct output of the memory cell switching -computing unit.

The device consists of the input block shown in Fig. 1, one group of inputs of which is connected to discrete sensors and sources of binary code (not shown in the diagram) X1 ... X _R , and the second group of inputs is connected to address buses C'12 ... C'j, associated with the switching and computing unit 2 connected to the RAM unit 3, the output unit 4, the program unit 5, the synchronization unit 6, the multi-channel operation unit 7 containing n logical channels, the first and second decoders 8 and 9, the last connected to the first input first elem nta And 10, connected by the second input to the output of the third element OR 11, the second element And 12, connected by the first input with a specific output of the synchronization unit, the second element OR 13, connected by the input to the third element And 14, the first element OR 15, the output of which is connected with the inputs of all logical channels, the managed element 16, the managed memory cell 17, the sixth element And 18, the seventh element And 19, the fourth element And 20, the fifth element And 21, the fourth element OR 22, the eighth and ninth element And 72, And 73, the sixth and the seventh element OR 74, OR 75, elemen t OR NOT 76, electronic switch 77, element and first element EXCLUSIVE OR 79 and 103, eighth element OR 101, controlled trigger 102, fifth element OR 107, first element NOT 112 and the communication system shown in FIG. 10 having common buses 80, a logical element (decoder) 81, connected by four outputs e1, e2, e3 and e4 with control inputs of the first 82 and second 83 electronic keys, as well as with two corresponding inputs of the RAM block and the output block, program selection block 86, logical module LM and discrete module DM.

The operation of the device is carried out to the clocks generated in the synchronization block 6, each clock cycle is divided into four quarters for fixing transients in the triggers in the third and fourth quarters of the clock cycle with q1 = 1 and q2 = 1.

In block 7, the outputs of the decoders 8 and 9 are designated, respectively, e1 ... e7 and D1 ... D3. The values of the signals (variables) e1, e2, e3, and e4 in the decoders 8 and 81 are the same.

The communication system serves to organize the exchange of information between blocks 1, 3, 4 and 7. When the e1 signal is activated, key 82 passes the value of the code Q1 ... Qn from the outputs of input block 1 to the inputs of logical channels in block 7 via shared buses 80 in the form of information bottom T1 ... Tn + 1. If the output e2 is activated, the key 83 passes the P1 ... Pn code from the outputs of block 3 in the form of T1 ... Tn to the inputs of the elements And 23 of all logical channels on shared buses 80. When activating e3 or e4, in block 7 the output О of the OR element 75 is activated and the switch 77 passes the code value B1 ... Bn from the outputs of the logical channels, through circuit fragments F1 ... Фn to the common buses 80 in the form of information data T1 ... Tn to the input of the rows of cells memory, respectively, in block 3, or in block 4.

,

,

,

,

,

,

,

, С1…С11 обозначены командные шины (сигналы) на выходах программного блока 5, связанные с соответствующими входами блоков 2, 7, 86, модулями ЛМ и ДМ управляемого элемента 16 и управляющие их работой.Across

,

,

,

,

,

,

,

, C1 ... C11 marked command buses (signals) at the outputs of the program unit 5, associated with the corresponding inputs of the blocks 2, 7, 86, modules LM and DM of the controlled element 16 and controlling their operation.

C'12 ... C'j denotes address buses (commands) that determine the addresses of sources and receivers of information in blocks 1, 3 and 4 and coming from the outputs of program block 5.

X1 ... Xn, ..., Xm ... Xk - multi-bit binary codes (signals), coming for example from the outputs of analog-to-digital converters, where the left bits are the least significant.

Хк + l ... XR - input discrete signals from sensors (buttons, directional switches, etc.).

T1 ... Tn + 1 - information data (signals) at the inputs and outputs of the corresponding electronic keys, switches, units, as well as on the common buses 80 of the communication system (Fig. 10).

Inputs of blocks, logical channels of elements, etc. are indicated by incoming arrows, and outputs are indicated by outgoing arrows.

When closed, all electronic keys and switches have high resistance at the outputs.

Figure 2 shows the structure of the logical channels. Each of the n channels consists of a fourth AND element 23, connected by an output to the first input of an EXCLUSIVE OR 24 element, the output of which is connected to the first input of the first OR element 25, of the first AND element 26, connected by the first input to the second input of the second AND element 27, the output of element 25 connected to the input of the third element And 28, the output of which is connected to the counting input of the first counting trigger 29, the output of which is connected to the counting input of the second counting trigger 30, the output connected to the first input of the second element OR 31, the second input of which it is connected to the output of element And 26 of the module for shifting the bits of the binary code MCP2 for the first channel, the module for shifting the bits of MCP3 for the last channel and the modules for shifting the bits of MCP1 for the remaining channels.

An example of the input unit 1 is presented in Fig. 3 and contains a number of electronic keys 32 to the inputs of which the bits of binary codes X1 ... Xn, ..., Xm ... Xk are received and which alternately, by the corresponding signal of the first decoder 33, pass a certain binary code to the outputs Q1 ... Qn, depending on the values of the address commands C'12 ... С'е, elements And 34, the first inputs of which receive bits of information signals Xk + 1 ... XR, the second inputs of the elements And 34 are connected to the outputs of the second decoder 35 and depending on the values of the address commands to the corresponding address on the buses C'e + 1 ... C'j by activating a specific output of the decoder 35, the corresponding bit of information appears at the output of the OR element 36, i.e. at the output of block 1 for single-bit variables.

An example of a switching and computing unit 2 is shown in FIG. 4, it consists of a decoder 37 connected by inputs to the program unit 5, the first two outputs decoder 37 connected to the inputs of the first and second elements AND 38, AND 39, and the third and fourth outputs connected to the inputs of the two AND elements of the AND-OR element (2-2-2-2-2-AND-4 OR) 40, the output of which is connected to the input of the EXCLUSIVE OR 41 element, the output of the latter is connected to the input of the third element AND 42, connected by the output to the control input of the memory cell (trigger ) 43, the information input of which is connected is connected with the output of the OR element 44, the first input of this element is connected to the output of the fourth AND element 45, and the second input is connected to the output of the fifth And 46 element, the first input of which is connected to the output of the element NOT 47, the AND-NOT element 106 and the sixth AND element 108 with related links.

An example of a random access memory unit 3 is shown in FIG. 5 and contains rows of memory cells 48, one of which contains information code (data) T1 ... Tn from shared buses 80 by command e3 to pulse d2, which are received at the inputs of the first element And 70 from the output of the decoder 81 of the communication system and block 6, the address of the memory cells is formed on the address buses C'12 ... C'e and the outputs of the decoder 49. The binary code is read from the output of one of the rows of memory cells 48 by the electronic key 50 according to the signals from the output of the decoder 49, depending on signal values on address buses x С'12 ... С'е, and on the e2 command, the read code is sent to the shared buses 80 through the key 83 of the communication system, a series of one-bit memory cells 51, where the results of intermediate calculations of Boolean functions are recorded at the output of the memory cell 43 by a command from the output of the And element 38 of block 2 and in accordance with the signals on the address buses C'e + 1 ... C'j and the outputs of the second decoder 52, which also determines the memory cell 51, where the bit of information from the AND 53 and OR 54 elements is read from, write and read at different clock cycles of the device.

An example of the structure of the output unit 4 is presented in Fig.6, it consists of rows of memory cells 55, where the values of the binary codes T1 ... Tn from the common buses 80 are written, which are formed at the outputs of the logical channels through circuit fragments F1 ... Fn and the switch 77 of block 7 by the command from the output of the element And 71, the input of which receives the signals e4 and d2, respectively, from the output of the decoder 81 and from block 6, the addresses of the rows of memory cells are determined by the signals on the address buses C'12 ... C'e coming from the output of the program block 5, and activating the corresponding output first of the decoder 56, from the outputs of the memory cells 55, the binary code can be transmitted, for example, to information systems, digital-to-analog converters, etc., single-bit memory cells 57 are used to record the results of the calculation of Boolean functions received from the output of the memory cell in block 2 by the command from the output of element And 39 of block 2, the address of memory 57 is determined by the signals on the address buses C'e + 1 ... C'j and the activation of the corresponding output of the decoder 58. Variables from the outputs of the memory cells 57 can be fed to electric drives, signaling, etc.

,

,

,

,

,

,

, С1…С11 поступают на входы электронного ключа 111 и далее с выходов ключа 111 поступают на входы соответствующих блоков.An example of a circuit of a program block 5 is shown in FIG. 7, it contains a read-only memory ROM 60, first and second electronic keys 61 and 111, a pulse counter 59 (FIG. 11) having an AND 109 element connected by inputs to an output of an AND element of the block 108 2 and with the output of element And 64 of block 6, an electronic key 85, the control and information inputs of which are connected to the output of element 109 and with common buses 80, transmitting information data T1 ... Tn, and the outputs are connected to the installation inputs of the counting triggers 84, which realize the count of pulses coming to mid the input of the first counting trigger 84 from the output of the first element AND 63 of the synchronization unit 6, and the outputs of the counting triggers are the outputs of the pulse counter 59 and are connected to the outputs of the ROM 60, some of the outputs of which are addressed by the address buses C'12 ... C'j to the inputs of the first electronic key 61, from the outputs of which the signals (binary codes) from the address buses C12 ... Cj are received in all blocks except 2, 6, and 7, and the other part of the outputs of the ROM 60 in the form of command (control) buses С _о ,

,

,

,

,

,

,

, C1 ... C11 go to the inputs of the electronic key 111 and then from the outputs of the key 111 go to the inputs of the corresponding blocks.

The functional relationship between the inputs and outputs of the electronic key 85 is presented below using the variables e and d2:

………

………

и

- выходы электронного ключа 85, d2 - сигнал с выхода элемента 64 блока 6,Where

and

- outputs of the electronic key 85, d2 - signal from the output of element 64 of block 6,

T1 ... Tn - code values on the shared buses 80 of the communication system,

E - the value of the output element And 108 block 2.

является инверсией С, аналогично для других переменных (сигналов).Variable (signal)

is an inversion of C, similarly for other variables (signals).

An example of a synchronization block 6 is shown in Fig. 8, it contains a first counting trigger 62 connected by a direct output to the first element And 63, and an inverse output to the first inputs of the second and third elements And 64, I65, the second input of the last connected to the output of the fourth element And 66, the input of which is connected with the direct output of the second counting trigger 67 and with the output of the inverter 68, the input of the latter, together with the inputs of the trigger 62, element And 63, and element And 64 are connected to the pulse generator 69, the output of element And 65 is connected to the reset input to "0 "Counting trigger 67. Handling unit 6 is illustrated in Figure 9 diagrams.

All triggers and memory cells are triggered by the trailing edge of the pulses arriving at their control, reset and counting inputs. Before starting work, all triggers are reset to "0".

The principle of operation of block 2 is known and consists in the implementation of the Boolean functions AND, OR, NOT at C3 = 0 and the function EXCLUSIVE OR at C3 = 1, sequentially in clock cycles, and also in controlling the corresponding processes in blocks 3, 4, 5, 7, and 86 .

Activation of an output or signal means the appearance of a logical “1”.

и

на управляющих входах управляемого элемента 16 последний реализует логическую функцию ИЛИ, если

и

, то элемент 16 реализует логическую функцию ИСКЛЮЧАЮЩЕЕ ИЛИ, а если

и

, то элемент 16 реализует функцию ИСКЛЮЧАЮЩЕЕ ИЛИ двух последних разрядов двоичного кода на выходах схемных фрагментов Фn-1, Фn.In block 7, with

and

at the control inputs of the controlled element 16, the latter implements a logical function OR, if

and

, then element 16 implements the logical function EXCLUSIVE OR, and if

and

, then element 16 implements the function EXCLUSIVE OR of the last two bits of the binary code at the outputs of the circuit fragments Фn-1, Фn.

The operation of the device consists in calculating the logical functions in block 2 with the simultaneous implementation of operations on multi-bit binary codes in block 7, and if necessary, the device ensures the joint operation of blocks 2 and 7, for example, in the case of studying set and received (accepted) binary codes and making decisions on the results of a logical analysis of the results. The device operates on the clocks generated in block 6.

.We explain the operation of the device with a few examples. Assume that

.

и

.Compare two binary numbers A1 and A2 and suppose that A1 = A2 and both are expressed in binary code 11001011. Suppose that the number A1 is in block 1 in the form X1 ... Xn and n = 8, and the number A2 is stored in the block of random access memory 3 in the values P1 ... Pn and n = 8, i.e. block 7 has eight logical channels. The equality of numbers is determined by the method of algebraic addition of numbers A1 and -A2, presented in the additional code, we assume that

and

.

At the first clock cycle, the values X1 ... X8, with the corresponding values C'12 ... C'e and e1 = 1, will come from block 1 through key 82 to the common buses 80 of the communication system and then to the inputs of the fourth elements And 23 of all logical channels of block 7, where by the commands C9 ... C11, the output e1 of the decoder 8 and the number A1 are activated for a single output of the element AND 73 through the elements EXCLUSIVE OR 24, OR 25, AND 28 and d1 = 1 are recorded in counting triggers 29.

At the second clock, with the corresponding signals C'12 ... С'е and е2 = 1 in block 3, the corresponding output of the decoder 49 is activated and from the output of the key 50 the number A2 through the key 83 and the common bus 80 of the communication system will go to the inputs of the elements 23 of all logical channels and with D1 = 1, according to the signal from the outputs of the elements AND 10, OR 15 and EXCLUSIVE OR, the inversion of the number A2 will go to the counting inputs of the counting triggers 29 of all logical channels and for d1 = 1, the EXCLUSIVE OR bitwise function is implemented for the numbers A1 and A2, while on outputs of counting triggers 29 of all logical channels vayutsya unit values.

On the third step, the output D1 of the decoder 9 of block 7 is activated and, with C _o = 1, the logic “1” from the output of the AND 14 element through the OR 13, AND 27 elements of the first channel will go to the corresponding inputs of the OR 25, AND 26 elements and the logical “1” with the output of the AND 26 element through the OR element 31 of the first channel will appear at the input of the And 27 element of the second logical channel, and then through the And 27, I26 and OR 31 elements of the subsequent channels, the indicated logical “1” is formed at the outputs of the OR elements 31 of all logical channels and with a pulse d1 = 1 all counting triggers 29 will switch to state zero "that is, the result of the difference of two equal numbers appeared, and all the triggers 30 to the “1” state and information was recorded from the output of the OR element 31 of the last logical channel to the memory cell 17 by the signal from the output of the And element 20 of block 7.

логический «0» с выходов схемных фрагментов Ф1…Фn, через элемент ИЛИ 16, при соответствующих сигналах С9…С11 по команде е6 с выхода первого дешифратора 8 блока 7 поступает через элемент 40 на вход элемента 41 блока 2, где инвертируется при С1=1, и в третьей четверти такта при C2=1, d1=1 и С3=0 единичное значение сигнала с выхода элемента ИЛИ 44 запишется в ячейку памяти 43 по команде с выхода элемента И 42.At the same third measure with

logical "0" from the outputs of the circuit fragments F1 ... Фn, through the OR element 16, with the corresponding signals C9 ... C11, by the command e6 from the output of the first decoder 8 of block 7, it passes through element 40 to the input of element 41 of block 2, where it is inverted with C1 = 1 , and in the third quarter of the clock cycle with C2 = 1, d1 = 1 and C3 = 0, a single signal value from the output of the OR element 44 is written to the memory cell 43 by a command from the output of the And 42 element.

On the fourth clock, the logical “1” from the output of the memory cell 43 for certain commands C4 ... C6 and activation of the corresponding output of the decoder 37 of block 2 and the output of the element And 39 with a pulse d2 = l coming from the output of the element And 64 of the block 6, is written to a certain value C'e + 1 ... C'j memory cell 57 of the output unit 4 as information that A1 = A2.

Consider the second example, when A1 <A2 and A1 = 11001011, and A2 is 10011011.

At the first clock, by analogy with the first example, the number A1 is recorded in the counting flip-flops 29 in bits into each logical channel of block 7.

At the second step with e2 = 1, similarly to the first example, only with D1 = 1, the inversion of the number A2 goes to the inputs of the elements And 28 and in the third quarter of the beat (d1 = 1) the unit value of the digits of the number A2 changes the state of the counted triggers 29 to the opposite and to the output of triggers 29 shows a result equal to A1 + Ā2 (10101111), while in the second logical channel, trigger 29 changed its state twice in two cycles, which led to a change in the state of the second counting trigger 30 from zero to one and the fact of transfer from the second was fixed discharge into the third and whether from the second logical channel to the third, which occurs in similar situations in all logical channels of block 7.

On the third clock cycle, according to signals D1 and Co, the logical “1” through the elements AND 14, OR 13, AND 27 of the first channel enters the second and first inputs of the elements OR 25, AND 26 of the first logical channel and from the output of element 26 through the element OR 31, the logical unit to the input of the AND element 27 of the second channel and further to the inputs of the OR elements 25, AND 26, and from the output of the OR element 31, the logical “1” as a result of the transfer was received at the input of the And 27 element of the third logical channel and further to the inputs of the OR elements 25, AND 28 , AND 26, from the output of the last element, logical "1" through the element OR 31 arrives at the input of the And 27 element of the fourth channel and then at the inputs of the And 26, OR 25, And 28 elements, then the transfer does not pass, because at the outputs of triggers 29 and 30, logical zeros. Thus, the AND 26 and OR 31 elements provide end-to-end transfer from one logical channel (discharge) to another logical channel (discharge) from top to bottom, when there is transfer, then when d1 = l, the states of triggers 29 in the first four channels and at the outputs change of the triggers 29 of all logical channels, the result of the algebraic sum A1 + (- A2) is set in the additional code 01011111, at the same time, the signal from the output of the And 20 element will record information (0) from the output of the trigger 30 through the OR element 31 of the last channel in the memory unit 17 and 7, while the zero value at the output of the OR element 31 shows that A1 <A2 and the result of the algebraic sum in the additional code is obtained. At the second cycle, in block 2 with C1 = 1, C2 = 1 and C3 ... C6 equal to "0", through the elements AND 46 and OR 44, the logical "1" enters the information input of the memory cell 43, which at the zero output of the AND element -OR 40 is recorded in cell 43 by the signal at the output of the EXCLUSIVE OR element 41 through the AND element 42 to the control input of the memory cell 43 with d = 1.

с выхода второго элемента ИЛИ 31 последнего логического канала поступает на выход элемента И-ИЛИ 40 блока 2, и при С1=1 на выходе элемента И 41 имеется логический «0», что оставляет на выходе ячейки памяти 43 логическую «1».In the third cycle, according to the signal e7 = 1 from the output of the decoder 8 of block 7, the value

from the output of the second element OR 31 of the last logical channel, it goes to the output of the AND-OR element 40 of block 2, and with C1 = 1, the output of element AND 41 has a logical “0”, which leaves logical “1” at the output of memory cell 43.

и е6=1 значение L1=1 с выхода элемента ИЛИ 16 блока 7 поступит через элемент И-ИЛИ 40 на вход элемента И 41, и при С 1=1 на выходе последнего образуется логический «0» и единичное значение на выходе ячейки 43 не изменится и полученный результат вычисления логической функции

·L1, подтверждающий, что А1<А2.At the fourth measure with

and e6 = 1, the value L1 = 1 from the output of the OR element 16 of block 7 will go through the AND-OR 40 element to the input of the And 41 element, and with C 1 = 1 the logical “0” is formed at the output of the latter and the unit value at the output of the cell 43 is not the resulting result of computing a logical function will also change

· L1, confirming that A1 <A2.

On the fifth step, the result obtained above from the output of the memory cell 43 of block 2 with the corresponding command from the output of the decoder 37 and d2 = 1 in the second quarter of the clock, in accordance with the command at the output of the And 39 element, is written to the output block 4 in one of the memory cells at the corresponding address C'e + 1 ... C'j.

Further, it would be necessary to calculate the logical function L1 · L2 in the block 2 described above, and if A1> A2, then the function L1 · L2 was equal to logical “1”.

Let us return to the third step when the result of the algebraic sum of two numbers A1 and -A2 was obtained in the additional code, and we continue to solve the problem of determining the result of calculating the algebraic sum A1 + (- A2).

At the third clock cycle with Co = 1, the transfer process will end, which is formed at the outputs of triggers 30 and elements and 26, while through the elements I 27, OR 25, and 28 of the logical channels, according to the pulse dl, the transfer values will go to the counting inputs of the triggers 29, and to their outputs will result in the addition of numbers A1 and A2. If the absolute value of the number A1 is greater than the number A2 i.e. | A1 |> | A2 |, then on the fourth step, add one to the value A1 + A2 and get the desired result A1 + (- A2), and if | A1 | <| A2 | it is necessary to invert the result of addition A1 + A2 and then we will obtain the desired result of addition A1 + (- A2).

In order to implement the above algorithm, the eighth element OR 101 and corresponding communications are introduced into the multi-channel operation unit 7. The inputs of the element OR 101 are connected to the outputs D2 and D3 of the decoder 9, and the output is connected to a specific input of the element And 18, the other input of which is connected to the direct output of the managed memory cell 17, and the output of the element And 18 is connected to the first input of the first element EXCLUSIVE OR 103, the output K2 of which is connected to the input of the second element OR 13, and the output K1 of the element And 19 is connected to one of the inputs of the first element OR 15.

The proposed scheme works as follows. If | A1 |> | A2 |, then on the third clock cycle, in the memory cell 17 of block 7 with Co = 1 and pulse d1 = 1, the signal from the output of element And 20 will record a single transfer from the highest order, i.e. from the output of trigger 30 through the OR element 31 of the last logical channel and on the same clock cycle, all triggers 30 will be reset in the fourth quarter of the clock cycle with q2 = l.

On the fourth step with D2 = 1, Co = 1 and K2 = 1, the unit transfer through the elements OR 13, AND 27, OR 25, AND 28 is recorded in the number A1 + A2 and at the outputs of the triggers 29 the value of the desired sum A1 + (- A2) is formed .

If | A1 | <| A2 | or | A1 | = | A2 |, then on the third step, “0” will be written to memory cell 17 and the triggers 30 of all logical channels will be reset to “0”, and on the fourth step when D2 = 1, K1 = 1 and K2 = 0 by the signal from the output of the OR element 15 will invert the number A1 + A2 and the outputs of the triggers 29 will display the result of the algebraic sum A1 + (- A2).

Thus, in the proposed version of the algorithm and the proposed change in the scheme, the algebraic addition of two numbers A1 + (- A2) required four clock cycles instead of six, as in the prototype, which significantly increases the speed of the device by reducing the number of clock cycles by one and a half times for this operation.

Further, in the prototype, the result obtained could be written to RAM block 3 or to output block 4 at the next fifth clock cycle. The proposed algorithm and the corresponding scheme allow this to be done on the same fourth measure, reducing the total number of measures for the implementation of algebraic addition and recording the result in blocks 3 or 4.

For this, “n” identical circuit fragments F1 ... Фn are entered into block 7 according to the number of logical channels, each of which (Fig. 13) contains two elements OR 99 and EXCLUSIVE OR 100, in each circuit fragment the three inputs of OR 99 are associated with the output of the OR element 15 of block 7, with the second input of the And element 27 of the corresponding logical channel and with the seventh output e'7 of the decoder 37 of the block 2, the output of the OR element 99 is connected to the first input of the EXCLUSIVE OR 100 element, the second input of which is connected to the output of the trigger 29 of the corresponding logical ka ala, and the output associated with certain data inputs of the electronic switch 77 and the managed element 16, block 7.

We return to the fourth step of calculating the algebraic sum A1 + (- A2). If | A1 |> | A2 |, then with D2 = 1 and K2 = 1 in block 7, from the output of the OR 13 element, the logical “1” will go to the input of the And 27 element of the first logical channel and through the transfer through the And 26 and OR 31 elements it will go to the inputs of certain logical channels and at the inputs and outputs of the OR elements 99 of the corresponding circuit fragments, and taking into account the signals at the outputs of the triggers 29 at the outputs of the EXCLUSIVE OR 100 elements of all circuit fragments F1 ... FP, the desired value of the sum A1 + (- A2) will appear, which can be written, for example, in the block of RAM 3 on the same clock signal e3 = 1 output from the first decoder 8 block 7. When | A1 | <| A2 | and D2 = 1, K1 = 1 at the output of the OR element 15 of block 7, a logical “1” will appear, which will go to the inputs of the elements OR 99 and then to the inputs of the elements EXCLUSIVE OR 100 of all circuit fragments, while the output of the last elements will display the result of the sum A1 + (-A2), which through switch 77 with e3 = 1 can be written into the main memory 3. The introduction of circuit fragments has increased the speed of the device and due to the fact that when e'7 = 1, using circuit fragments F1 ... Фn, it is possible for one tact to invert the code stored on the outputs of the triggers 29 and at e3 = 1 for write this inversion, for example, into RAM block 3, which obviously follows from an analysis of the operation of circuit fragments.

The controlled trigger 102 of block 7, connected to the control input with the output of the And element 12 and the information input with the direct output of the memory cell 17, and the output with the bus Tn + 1, determines the sign of the difference of two numbers and allows you to save this sign for any number of clock cycles of the device, when the state of the memory cell 17 may change. The inputs of the element And 12 are associated with a specific output of the decoder 8 of the block 7 and with the output of the element 66 of the synchronization block 6.

The discharge shift module MCP1 for each logical channel in block 7, except for the first and last, has two outputs U'1 and U'2 and five inputs t1, C ', C' ', b', b '', its operation is determined by Boolean features:

Where the first output Y'1 is connected to the third input of the first OR element 25 of this logical channel, the second output Y'2 is connected to the fourth input of the OR element 25 of the subsequent channel, input b 'is connected to the output of the counting trigger 29 of this logical channel, input b ”is connected with the output of the first counting trigger 29 of the subsequent logical channel, the inputs C 'and C ”are connected to the corresponding outputs of the logical module LM, t1 is connected to the output of the OR-NOT 76 element.

The shift module MCP2 of the first logical channel has three outputs U1, U2, U3 and six inputs b1, b2, t1, C ', C' ', C °, and its operation is determined by Boolean functions:

,

,

,

, а

и

являются входными сигналами логического модуля ЛМ и поступают на его входы с выходов программного блока 5.Where the first output U1 is connected to the fourth input of the OR element 25 of the first logical channel, the second output U2 is connected to the third input of the OR element 25 of the same channel, the third output is connected to the fourth input of the OR element 25 of the second logical channel, input b1 is connected to the output of the first counting trigger 29 of the first logical channel, input b2 is connected to the output of the counting trigger 29 of the second logical channel, inputs C ', C "are connected to the corresponding outputs of the logical module LM, input t1 is connected to the output of the OR-NOT 76 element and input C ° is connected to the corresponding the current output of the LM logic module, in which the outputs

,

,

,

, but

and

are the input signals of the logical module LM and enter its inputs from the outputs of the program unit 5.

The shift module MCP3 of the last logical channel has one output U1 '' 'and three inputs b n, С' ', t1 and operates in accordance with the Boolean function:

Where the output Y1 '' 'is connected to the third input of the OR element 25 of the last logical channel, the input bn is connected to the output of the trigger 29 of the last logical channel, the input C' 'is connected to the corresponding output of the logical module LM, the input t1 is connected to the output of the OR-NOT 76 element block 7.

The shift of the code bits down from the first to the last logical channel is carried out by the command C '= 1, with C' '= 0, t1 = 1, C ° = 0. In this case, for the MCP2 module, if b1 = 1 and there is a logical “0” at the output of the trigger 29 of the second logical channel, then in accordance with functions (3) and (5), the logical unit will be established at the output of U1 and it will also appear at the output of the element OR 25, will go to the input of AND 28 and with d1 = 1, trigger 29 of the first channel will change its state to zero. At the same time, when the signals at the inputs d1, d2 are inequalized, the output U3 is activated and the logical “1” goes to the input of the And 28 element and, at the end of the d1 pulse, the output of the trigger 29 of the second channel will take the opposite value, i.e. the value that was at the output of trigger 29 of the first logical channel. At the same time, in the MCP1 modules, in accordance with function (2), when the signals at the outputs of the triggers 29 of this and subsequent logical channels are not equal, the output U'2 is activated in all MCP1 modules and the logical “1” through the corresponding OR 25 elements will go to the inputs of the And 28 corresponding logical channels, and at the output of the trigger 29 of each subsequent channel, the output value of the trigger 29 of this logical channel will appear, i.e. there will be a shift down the bits of the code previously recorded in triggers 29.

A shift of the code digits up occurs when the command C '' = 1 is present, when C '= 0, C ° = 0, t1 = 1. Then, in accordance with functions (1) ... (6), the outputs U2 in the MCP2 module, U'1 in the MCP1 module and the output U1 '' 'in the MCP3 module can be activated, while the output U2 is activated if the input signals b1, b2 at the inputs MCP2 modules are not equal, and in this case, through the OR element 25, the logical 1 will go to the input of the And 28 element of the first logical channel and the trigger 29 of the first channel will take the value of the trigger 29 of the second logical channel. At the same time, for any MCP1 module, if the signals b ', b' 'are not equal, the output U1' is activated and the logical “1” through the OR 25 element will go to the input of the And element 28 of this channel, where the corresponding MCP1 module is located, and the output of the trigger of this logical channel will be set trigger output value 29 of the subsequent logical channel. At the same time, with bn = 1, the output U1 ″ of the MCP3 module is activated and the logical “1” appears at the output of the And 28 element and the trigger 29 of the last logical channel goes into the “0” state. Thus, there will be a shift from bottom to top of the bits of the code recorded in the triggers 29.

The presence of the LM logical module in the device made it possible to organize a cyclic shift of binary codes down with the transfer of the highest order to the lowest order at C ° = 1, which directly follows from the analysis of formula (3), which determines the value of U1 in the MCP2 module.

A single value of the direct output of the memory cell 17 in block 7 means that there is a transfer, for example, after arithmetic addition of n bits of two binary numbers, the transfer value to the next n + 1 bit is activated when D3 = 1 at the output of the decoder 9 of block 7 and will go through the OR element 13 not input element And 27 of the first logical channel of block 7.

The program selection block 86 is shown in FIG. 12 and consists of a first electronic key 87 connected by information inputs to common data buses 80 T1 ... Tn, by its outputs to the installation inputs of a multi-bit pulse counter 88, the outputs of which are connected to the corresponding inputs of the ROM 89 associated with its outputs with the information inputs of the second 90 and third 91 electronic keys, the outputs of these keys are connected respectively to the command and address buses of the program unit, the first and second elements And 92 and And 93, with its output, the first element And 92 is connected to the control input of the key 87, and its inputs with the output of the fourth element And the synchronization unit 6 and with the first 61 output of the decoder 94, the output of the element And 93 is connected to the counting input of the counter 88 , the first input of the second AND element 93 is connected to the output of the OR element 95, connected to the inputs of the second b2 and third b3 outputs of the decoder 94, the second input of the And 93 element is connected to the output of the And element 63 of block 6, the control inputs of the keys 90 and 91 are connected to the outputs of B2 and b3 of the decoder 94, whose inputs are unified command with two tires S'o, S''o, and to direct the output of block 43 of memory cell 2, the output 61 of the decoder 94 is also connected to the third input 75 of the OR block 7. The outputs of decoder 94 are activated only when α = 0.

Suppose that in one of the program fragments it is necessary to select odd numbers from the set of numbers represented in binary code and stored, for example, in input block 1 and place them in the memory cells of block 3 at predetermined arbitrary addresses. The binary codes of these addresses are recorded in ROM 89, and the code of the first address is stored in the block of RAM 3. The memory cell 43 of block 2 is set to zero.

запишется по сигналу с выхода элемента И 73 блока 7 в триггеры 29 логических каналов, и на следующем такте при С1=1 логический «0» сохранится в ячейке памяти 43, и на следующем такте при соответствующих командах б1=1, α=0, е2=1 значение кода первого адреса по шинам T1…Tn из блока 3 запишется через ключ 87 в счетчик 88. На следующем такте при б3=1, α=0 адрес ячейки памяти, куда следует записать нечетное число, появится на выходе ключа 91, т.е. на адресных шинах, а ключ 61 блока 5 закроется и произойдет запись нечетного числа с выходов триггеров 29 через схемные фрагменты и общие шины 80 в блок 3 при е3=1. Одновременно под действием сигнала б3 и счетного импульса с выхода блока 6 в двоичный код счетчика 88 прибавится единица и активируется на выходе ПЗУ 89 новый адрес для записи второго нечетного числа.At the first clock cycle, the first number from the input block 1 is read, for example, it is odd and, when C1 = 0, an odd number, when C1 = 0,

is recorded by the signal from the output of the And element 73 of block 7 to the triggers 29 of the logical channels, and at the next clock with C1 = 1 the logical “0” will be stored in the memory cell 43, and at the next clock with the corresponding commands б1 = 1, α = 0, е2 = 1, the code value of the first address on the T1 ... Tn buses from block 3 is written via key 87 to counter 88. At the next step, with b3 = 1, α = 0, the address of the memory cell where the odd number should be written will appear at the output of the key 91, t .e. on the address buses, and the key 61 of block 5 closes and an odd number is recorded from the outputs of the triggers 29 through circuit fragments and shared buses 80 to block 3 with e3 = 1. At the same time, under the action of signal b3 and a counting pulse, the unit will be added to the binary code of counter 88 and the unit will be activated at the output of ROM 89; a new address for recording the second odd number will be activated.

If the second number turns out to be even, then with C1 = 0 and T1 = 0 this number will not be written to triggers 29 of the logical channels, and if C1 = 1, logical “1” will be written to cell 43 of block 2 and the above process will not be repeated.

In contrast to the prototype, where odd or other numbers can be written only to addresses that went sequentially with a difference of one, in the proposed device, due to the introduction of ROM89, it became possible to record these numbers by addresses in any order, which extends the functionality of the device. To determine even numbers, an EXCLUSIVE OR 79 element is introduced in block 7, the inputs of which are connected to the first T1 bus and the C1 command bus, and the output is connected to the input of the OR 107 element, which reduced the number of clock cycles when determining an even number and writing it to logical channels at C1 = 1.

Electronic keys 61 and 111 in block 5 are turned on if the corresponding signals are b3 = 0 and b2 = 0, otherwise they are turned off (closed).

In contrast to the analogue, access to one or another part of the ROM 89 memory may depend on the calculation result, which appears in the form of T1 ... Tn on the shared buses 80, which determines the part of the memory in the ROM that should be addressed depending on the calculation results.

The AND-NOT element 106 in block 2, which has its inputs connected to the corresponding outputs of the decoder, and the memory cell 43, and the output to the specific inputs of the elements AND 23, 70, AND 71 in blocks 7, 3, 4, allows you to feed or block writing binary code to these blocks depending on the values of the output signal at the output of the memory cell 43.

The connection between the common buses 80, transmitting information signals T1 ... Tn with the installation inputs of the counting flip-flops 84 through the electronic key 85 of block 5, allows implementing the program of operation of the device depending on the results of the analysis in block 2 of the received data at the output of the logical channels of block 7, because . the control signal of the operation of the key 85 comes from the output of the element And 108, which is connected by its inputs with the outputs of the memory cell 43 and the decoder in block 2. Moreover, the proposed structure simplifies the general circuit of the device, for example, the absence of connections between the key 85 and address buses compared to the prototype maintaining functionality.

,

, Я', t1, q1, поступающие соответственно с двух входов логического модуля ЛМ, выходов элементов ИЛИ 11, ИЛИ-НЕ 76, И 21 блока 7, выходными сигналами триггеров 29 являются b1…bn для всех логических каналов, поступающие через схемные фрагменты Ф1…Фn на информационные входы выключателя 77 и управляемого элемента 16 блока 7 и на соответствующие входы модулей сдвига разрядов МСР1, МСР2, МСР3. При значении сигналов

или t1=1,

или Я'=0 первый счетный триггер 29 работает в режиме счетного триггера и его функционирование описано на предыдущих страницах.Presented in figure 2 in the first logical channel, the scheme of the first counting triggers 29 is the same for all logical channels and consists of a memory cell 29-1, the first and second elements OR 29-2 and 29-5, the first and second elements And 29-3 and 29-4 with corresponding links. The outputs of the elements AND 29-3, AND 29-4 are connected to the inputs of the element OR 29-2, the output of which is connected to the information input of the memory cell 29-1, the inverse of the latter is connected to the first input of the element And 29-4, the second input of which connected to the output of the element OR 29-5. The input signals of the counting trigger 29 are

,

, I ', t1, q1, respectively, coming from the two inputs of the logic module LM, the outputs of the elements OR 11, OR NOT 76, AND 21 of block 7, the output signals of the triggers 29 are b1 ... bn for all logical channels coming through the circuit fragments F1 ... Фn to the information inputs of the switch 77 and the controlled element 16 of block 7 and to the corresponding inputs of the modules of the shift bits MCP1, MCP2, MCP3. With the meaning of the signals

or t1 = 1,

or I '= 0, the first counting trigger 29 operates in the counting trigger mode and its operation is described on the previous pages.

и t1=0, триггер 29 работает как управляемый триггер, куда информация поступает с выхода элементов ИЛИ 29-3, И 29-2 и хранится в ячейке памяти 29-1 при поступлении импульса с выхода элемента И 28 в каждом логическом канале. При Я'=1,

и Д=1 в ячейку памяти 29-1 через элементы И 10, ИЛИ 15, ИЛИ 25 в ячейку памяти 29-1 по импульсу с выхода элемента И 28 запишется логическая «1» с выхода элемента ИЛИ 29-2 и на следующих тактах при Я'=1,

, Д1=1,

и d'=1 произойдет поразрядно вычисление булевой функции И от двоичных кодов последовательно по тактам, поступающим на входы элементов И 23 всех логических каналов. При этом количество последовательно поступающих двоичных кодов не ограничено.If

and t1 = 0, trigger 29 works as a controlled trigger, where the information comes from the output of the OR 29-3, AND 29-2 elements and is stored in the memory cell 29-1 when a pulse arrives from the output of the AND 28 element in each logical channel. When I '= 1,

and D = 1 in the memory cell 29-1 through the elements AND 10, OR 15, OR 25 in the memory cell 29-1 on the pulse from the output of the AND element 28, the logical "1" is written from the output of the OR element 29-2 and at the following clock cycles I '= 1,

, D1 = 1,

and d '= 1, the Boolean function AND is bitwise computed from the binary codes sequentially according to the clocks supplied to the inputs of the AND elements 23 of all logical channels. Moreover, the number of consecutively arriving binary codes is not limited.

, Д1=1, то по импульсу dl=l, поступающему с выхода элемента И 66 блока 6, в ячейку памяти 29-1 запишется логический «0» и на последующих тактах при Я'=1,

, Д1=0 и d=1 произойдет поразрядное вычисление логической функции ИЛИ от двоичных кодов последовательно по тактам, поступающим на входы элементов И 23 всех логических каналов.If I '= 1,

, Д1 = 1, then according to the pulse dl = l, coming from the output of the And element 66 of block 6, the logical “0” is written into the memory cell 29-1 and at subsequent ticks when I '= 1,

, D1 = 0 and d = 1, the bitwise calculation of the logical function OR from the binary codes occurs sequentially according to the clocks received at the inputs of the AND elements 23 of all logical channels.

.The introduced discrete DM module (Fig. 14) contains the first and second elements AND 110 and 113, the element NOT 114, the inputs of the first element OR 104 connected to the outputs of the first counting flip-flops 29 of the penultimate and last channels, the output of the second element OR 105 connected to the information input managed memory cell 17 of the multi-channel operating unit 7. The DM module allows you to store the values of the sign bits of two binary codes stored in the counting triggers 29 of the penultimate and last logical channels of the multi-channel operational unit and 7, wherein the first exclusive OR element 103 inverts the signal at the output of the AND element 18 on command

.

The technical and economic effect of using the device compared to the prototype is to increase logical speed by reducing the number of clock cycles during arithmetic operations and recording the results of operations in the RAM block, in expanding the functionality by changing the order of the program taking into account the results of the calculations and the possibility of arbitrary selection of memory cell addresses for recording binary codes selected according to one or another semantic attribute, as well as simplification of device while maintaining its functionality, for example, by reducing communication lines in the program unit.

Information sources

1. RF patent for the invention No. 2273042, bull. No 9 on 03/27/08

2. RF patent for the invention No. 2319192, bull. No 7 on 03/10/08

Claims (1)

A device for constructing programmable digital microprocessor systems, containing an input unit that receives signals from sensors and generates a specific code at its output, an output unit for recording the values of codes coming from all logical channels to memory cells and transferring them through digital-to-analog converters to electronic devices and electric drive mechanisms, program unit, RAM unit, synchronization unit and switching and computing unit, consisting of AND-OR elements, EXCLUSIVE element SOFT OR, five AND elements, memory cells, OR and NOT elements, while the first inputs of two AND AND OR elements are connected respectively to the third and fourth outputs of the decoder, and the second inputs are connected to the output of the input block connected by the first and second groups of inputs with by the group of information outputs of the control object and with the group of address outputs of the program block, as well as to the output of the RAM block, the output of the AND-OR element is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to a specific output of the of the program unit, the output of the EXCLUSIVE OR element is connected to the first input of the third AND element, connected by the second input to the corresponding output of the synchronization unit, and the output - to the control input of the memory cell, the information input of which is connected to the output of the OR element, the second input of the last connected to the output of the fifth element And, the second input of which is connected to a certain bus of the program unit, the first input of the fifth AND element is connected to the output of the NOT element, and the input of the latter is connected to the second input of the fourth AND element and, accordingly, with the program bus, the first input of the fourth AND element is connected to the inverse output of the memory cell, and its output is connected to the first input of the OR element, the direct output of the memory cell is connected to the information inputs of the output block and the RAM block, the first inputs of the first and second elements AND are connected to the first and second outputs of the decoder, their second inputs are combined and connected to the corresponding outputs of the synchronization block, and the outputs are connected to the corresponding inputs of the output block and the RAM block for information recording control, multi-channel operation unit containing a controlled element, nine AND elements, seven OR elements, a first and second decoders, a controlled memory cell, a controlled trigger, an electronic switch, OR-NOT, NOT elements, an EXCLUSIVE OR element and “n” in parallel working logical channels that have the same structure and each of which contains an EXCLUSIVE OR element, four AND elements, two OR elements, two countable triggers, and each logical channel has a multi-channel operational block, the output of the EXCLUSIVE OR logic element is connected to the first input of the first OR element, the second input of which is connected to the output of the second AND element, connected by the second input to the first input of the first AND element, and the output of the first OR element is connected to the first input of the third AND element, the output of the last with the counting input of the first counting trigger, the output of which is connected to the second input of the first AND element and to the counting input of the second counting trigger, the output of the latter is connected to the first input of the second OR element, the second input to which is connected to the output of the first AND element, while in the multi-channel operating unit the output of the first OR element is connected to the second inputs of the EXCLUSIVE OR logical channels, the first and second inputs of the first OR element are connected respectively to the outputs of the first and seventh AND elements, and two inputs of the first element And connected to one of the outputs of the second decoder and the output of the third OR element, the inputs of which are connected to two corresponding outputs of the first decoder, the first and second inputs of the second element AND are connected with one of the outputs of the synchronization unit and with a specific output of the first decoder, and the output is connected to the control input of the controlled trigger, the first input of the second OR element is connected to the output of the first EXCLUSIVE OR element, and the second input is connected to the output of the third AND element, the inputs of which are connected to the corresponding output of the second decoder and the output of the first element NOT, whose input is connected to the output of the third element OR, the first input of the seventh element And is connected to the corresponding output of the second decoder, and in the second inputs of the sixth and seventh AND elements are connected respectively with direct and inverse outputs of the controlled memory cell, the information input of which is connected to the output of the second OR element of the discrete DM module, and the control input of the controlled memory cell is connected with the output of the fourth AND element, the first input of which is connected together with the first inputs of the second elements AND of all logical channels to the corresponding command bus of the program unit, the second input of the fourth element And together with the second inputs of the third elements AND of all the logs channels are connected to a specific output of the synchronization unit, in the multi-channel operation unit, the information input of the controlled trigger is connected to the direct output of the controlled memory cell, the inverse output of the controlled trigger is connected via one of the common buses of the communication system to the output unit, the control input of the controlled element is connected to a specific command bus program block and with the first input of the fifth element OR, the output of the last connected to the first input of the ninth element AND, in the switching and computing The first inputs of the third and fourth AND elements, the AND-OR element are connected to the corresponding two outputs of the first decoder, and the second inputs are connected to the output of the managed element of the multichannel operational block and the output of the second OR element of the last logical channel, the inputs of the first and second decoders of the multichannel operational block connected to the corresponding command buses of the software unit, the output of the second element OR of the first logical channel is connected to the second input of the second element AND the second logic one channel, the output of the second OR gate of the second logical channel is connected to a second input of the second element and the third logical channel etc. to the last logical channel, the second input of the second AND element of the first logical channel is connected to the output of the second OR element of the multi-channel operating unit, where the second input of the ninth AND element is connected to the output of the third OR element, the inputs of the eighth AND element are connected to the outputs of the synchronization unit and the sixth OR element, and the output is connected to the first input of the fourth OR element, the output of which is connected to the reset inputs at “0” of the second countable triggers of all logical channels, the inputs of the fifth AND element are connected to a certain com software bus and the corresponding output of the synchronization block, and the output is connected to the second input of the fourth OR element and to the reset inputs at “0” of the first countable triggers of all logical channels, a communication system containing common buses, first and second electronic keys, a logical element, generating signals at its outputs, similarly to the first four outputs of the first decoder of a multi-channel operating unit, the logical module LM, the structure of which and its functioning is determined by logical functions

Where

and

are the inputs of the logical module LM and are connected with the corresponding command buses of the software unit, and C ', C'', C °, C''' are the outputs of the logical module LM and are connected by the output C '''to the first input of the sixth element OR of a multi-channel operating unit , other outputs - with the corresponding inputs of the modules of the shift bits MCP in each logical channel, moreover, the module shift bits MCP1 is located in all logical channels, except the first and last, and implements the logical functions

where Y'1 and Y'2 are the outputs of the MCP1 module and are connected with the third and fourth inputs of the first OR element of the given and subsequent logical channels, the variables b ', b'',C', C '', t1 are the input signals for MCP1, moreover, b ', b''come from the outputs of the first counting triggers of this and subsequent logical channels, C' and C '' come from the outputs of the logical module LM, t1 comes from the output of the OR-NOT element of the multichannel operation block, the MCP2 module in the first logical channel implements logical functions

and

where Y1, Y2 and Y3 serve as outputs of the MCP2 module and are connected with the third and fourth inputs of the first OR element of the first logical channel and with the fourth input of the first OR element of the second logical channel, and b1, b2, С ', С'', С °, t1 are the inputs of the MCP2 module and are connected to the outputs of the first counting triggers of the first and second logical channels, with the three outputs of the LM logical module and with the output of the OR-NOT element of the multi-channel operating unit, the MCP3 module calculates the logical function Y1 ^''' = bn · C ^'' · t1, where the signal U1 ^'''is supplied with the output module MSR3 tert th input of the first OR gate of the last logical channel signals bn, C ^'', t1 fed to MSR3 module inputs respectively output from the first counting trigger last logical channel, output from the logic module LM and the output of OR-NO multichannel operation unit, wherein the control the input of the electronic switch is connected to the output of the seventh OR element, the three inputs of which are connected to two corresponding outputs of the first decoder and to a specific output of the decoder of the program selection block, the second input of the sixth element OR connected to the command bus of the software unit, the output of the ninth element AND is connected to the first inputs of the fourth elements AND in each logical channel, the second inputs of the fourth elements AND of each logical channel together with the information outputs of the electronic switch of the multi-channel operating unit are connected to the common buses of the communication system, and the outputs fourth AND elements in each logical channel are connected to the first inputs of EXCLUSIVE OR elements, common buses are also connected to the outputs of the first and second electronic keys communication systems and to the corresponding inputs of the RAM block and the output block, the inputs of the first and second electronic keys are connected to certain outputs of the input block and the RAM block, the control inputs of the first and second electronic keys, the RAM block and the output block are connected to the corresponding outputs of the logic element a communication system, the three inputs of which are combined with the corresponding three inputs of the first decoder of the multichannel operational unit and with three outputs of the program unit, in which the switching and computing unit, the inputs of the AND element are NOT connected to the fifth output of the decoder and the direct output of the memory cell, and the output is connected to the third inputs of the fourth elements AND of all logical channels and to the third input of the first element AND of the RAM block, as well as to the third input of the AND element output unit, the sixth element AND is connected by inputs to the sixth output of the decoder and the direct output of the memory cell, and by the output to the first input of the element And the pulse counter of the program unit, the second input of the last element AND is connected with the corresponding output of the synchronization block, and the output is connected to the control input of the electronic key of the pulse counter of the program block, the first counting trigger in each logical channel has the same circuit and contains a memory cell, the first and second elements OR, the first and second elements AND, and the outputs of the first and the second AND elements are connected to the inputs of the first OR element, the output of which is connected to the information input of the memory cell, the inverse output of the latter is connected to the first input of the second AND element, the second input of which is connected inen with the output of the second OR element, the inputs of the latter are connected to the input of the OR element of the multichannel operating unit and with the corresponding command bus of the program unit, the inputs of the first element AND of the first counting trigger are connected to a specific command bus of the program unit and to the output of the third element OR of the multichannel operational unit , the direct output of the memory cell in all counting triggers are their outputs and are associated with specific inputs of the modules of the shift modules MCP1, MCP2 and MCP3 in the corresponding logical to In analogs, the control input of the memory cell of the first counting trigger is its counting input and is connected to the output of the third AND element in each logical channel, and the reset input at “0” of the indicated memory cell simultaneously serves as the reset input at “0” of the first counting trigger and is connected in all logical channels to the output of the fifth AND element of the multichannel operational unit, characterized in that an EXCLUSIVE OR element and an eighth OR element, which is connected to the second and third inputs by the first and second inputs, are inserted into the multichannel operational unit the outputs of the second decoder, and the output is connected to the first input of the sixth AND element, the inputs of the EXCLUSIVE OR element are connected to a specific command bus and to the first T1 bus from among the common buses of the communication system, and the output is connected to the second input of the fifth OR element, “n” are the same circuit fragments F1 ... Фn according to the number of logical channels, each circuit fragment is connected to the corresponding logical channel and contains two logical elements OR and an exclusive OR, with the first, second and third inputs of the OR element connected to the output of the first IL element And a multi-channel operating unit, with the second input of the second AND element of the corresponding logical channel and with the corresponding output of the decoder of the switching and computing unit, and the output is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the output of the first counting trigger of the corresponding logical channel, and the outputs of the elements EXCLUSIVE OR are outputs of the corresponding circuit fragments and are connected to the information inputs of the electronic switch and the controlled multi-channel element of the first operating unit, where the first and second inputs of the first EXCLUSIVE OR element are connected respectively to the output of the sixth AND element and to the output of the program unit, and the second control input of the managed element is connected to the output of the program unit and to the input of the discrete DM module, the program selection unit is introduced consisting of the first, second and third electronic keys, a multi-bit pulse counter, read-only memory ROM, the first and second AND elements, a decoder, an OR element, the first the second electronic key is connected by information inputs to the common buses T1 ... Tn of the communication system, and by its outputs with the installation inputs of a multi-bit pulse counter, the outputs of which are connected to the corresponding inputs of the read-only memory ROM, their outputs connected to the information inputs of the second and third electronic keys, the outputs of which connected respectively to the command and address buses of the program unit, the inputs of the first AND element are connected to the first output of the decoder and to a specific output of the unit synchronization, and the output is connected to the control input of the first electronic key, the inputs of the second AND element are connected to the output of the OR element and to a specific output of the synchronization unit, and the output is connected to the counting input of a multi-bit pulse counter, the inputs of the OR element are connected to the second and third outputs of the decoder, which are connected to the control inputs of the second and third electronic keys, respectively, the three inputs of the decoder are connected to two specific command buses of the program unit and to the direct output of the cell the name of the switching and computing unit, a discrete DM module in which two inputs of the first OR element are connected to the outputs of the first counting triggers of the penultimate and last logical channels, and the output is connected to the first input of the second AND element, the second input of which is connected to the output of the program unit, and the output connected to the first input of the second OR element, the second input of the last connected to the output of the first AND element connected by two inputs to the output of the second OR element of the last logical channel and to the output of the element NOT the input with the second input of the second element I.

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