SU1293727A1 - Polyfunctional calculating device - Google Patents

Abstract

The invention relates to the field of computer technology. Ci can be used to perform multiplication, division, square root and sorting of large arrays of multi-digit numbers. The purpose of the invention is to expand the functionality of the device by performing a sorting operation and improving the processing performance of large data arrays. The conveyor-matrix device contains a matrix of N rows and N columns, two additional columns of N cells and N control cells, triggers, N maximum number selection circuits, N read signal generation circuits, and the OR element, where N is the operand width. Each cell of the matrix and an additional column contains two three 3 hera, logical elements and an adder, and the control cell contains logical elements AND, OR. The selection circuit of maximally about a number contains the OR element sequentially connected, the EXCLUSIVE OR element and the trigger, and the read signal generation circuit includes, in addition to these elements, a trigger, two WL elements, AND element, the device efficiency increases with increasing digit size and volume of the processed information. 2 z.p, f-crystals, 8 ill., 2 tab. with S (L

Description

The invention relates to computing and can be used to perform multiplication operations, dividing, extracting a square root and sorting large arrays of multi-digit numbers.

The purpose of the invention is to expand the functionality of the device by performing a sorting operation and improving the processing performance of large data arrays.

FIG. 1 shows a functional diagram of the device; figure 2 - functional diagram of the cell matrix; ya fi1. 3 is an additional cell diagram; in fig. 4 is a control cell diagram; in fig. 5 - block diagram of the selection of the maximum number; in fig. 6 is a circuit for generating a readout signal; in fig. 7 is a block diagram diagram; in fig. 8 - sorting algorithm.

The device contains matrix 1 cells, additional cells 2, control cells 3, maximum number selection block 4, read signal generation blocks 5, element OR 6, triggers 7 forming first and second oblique matrices 7.1 and 7.2 triggers and oblique angle matrix 7.3 trigger pairs , the first input bus 8 of the operand, the second input bus 9 of the operand, the output bus 10 of the remainder, the output bus 11 of the sort, the first t2 and the second 13 output buses of the result and the output bus 14 of the readout signal of the device, as well as the synchronization unit 15, the third input operand bus 16, control bus 17, an input 18 multiplication value 1.

live tire

bus

19 values О, input bus 20 of the operation code and input bus 21 for general reset of the device.

Cell 1 is formed by triggers 22 and 23, elements AND 24-26, element. OR

Code О ,,, О Multiplicable Multiplier

Constant So

Dividend

Same Same Divider

27, the element EX or 28 and the adder 29.

Additional cell 2 consists of triggers 30 and 31, element I 32,

EXCLUSIVE OR 33 and adder 34.

Control cell 3 is made on AND 35-39 elements and OR 40-43 elements

Block 4 selection of the maximum number consists of a trigger 44, the element OR 45 and the element EXCLUSIVE OR 46.

Block 5 of forming the readout signal contains triggers 47 and 48, elements IL 49-51, element AND 52 and element EXCLUSIVE OR 53.

The synchronization unit 15 is formed by a clock pulse generator 54, And 55 and 56 elements, a decoder 57, a decoder 58 zero and a binary counter 59.

In tab. Figure 1 shows the state of the control signals, depending on the operation being performed, in Table. 2 - the status of information inputs and outputs of the device depending on the operation being performed. IT a b l and c a 1

Multiplication 40 C Co + A B Division

Extract

45

table 2

Product Major Junior Bit Definition

Also

Private

Balance Opervtsi

Inputs

8j 9 I 16

Podkoren Code 0,., 0 expression

Code number

The multiplication and Co + AK operations are performed in the same way, however, when multiplying, inputs 8 ... 0 are applied to the inputs, and in the second operation, the codes are constant. When multiplying, on the second information input of the cell 3 and on the third control inputs of the 17 cells 2, a single signal is set, and on the second and sixth outputs of the control cell - zero. This allows you to configure for logical repetition the elements EXCLUSIVE OR 28 cells 1, the element EXCLUSIVE OR 33 and the element AND 32 cells 2 of the first row. The second information input of cell 2 and input 8 of the device serves a zero code,

In the first cycle, the first N-paired multiplier bottom goes through bus 9 to the triggers of 22 cells 1 of the first row. The Nth bit of the nepBoi o multiplicand enters via bus 16 into cell 3 and through the element OR 41 to the first output and first control input of the first cell 1 of the first row. The N-ro value of the multiplier is set at the first inputs of the And 25 elements of all cells 1, the second inputs of which receive bits of the multiplicand from the trigger 22. The remaining multipliers of the input 16 are written into triggers 7 of the first column of the first skew matrix 7.1 Triggers. Partial amount is generated on third outputs.

cells 1.

In the second cycle, the partial amount from the third outputs of cells 1 of the first row is rewritten to triggers 23 on the second information inputs of cells 1 of the second row and to trigger 31 on the second information input to cell 2 of the highest bit. The first multiplicand is rewritten from the flip-flops of 22 cells 1 of the first row into the same triggers of the second row on the third information inputs (high order through cell 3). (N-1) -th multiplier factor from trigger 7 of the first column of the first oblique matrix

12937274

Continued table.2 Outputs

12 I 13

10 I II

Root

Also

Code number

0

c 5

five

0 5

0

1.1 enters through the cell 3 of the second line on the elements And 25 cells 1 of the second line. The remaining bits of the multiplier are overwritten into triggers 7 of the second column of the first oblique matrix 7.1. In this cycle, in the second row, a partial sum of the product of the first multiplier by V (N-1) -th multiplier of the multiplier is formed, which is added to the partial sum of the first multiplier of the Nth bit multiplier. At the same time, in the first row, the value of the highest bit of the product in cell 2 is formed: the transfer signal from the second output of cell 2 of the second row is fed to the first control input of cell 2 of the first row and through elements 32 and 33 to the input of adder 34.

In the third cycle, at the second input of the cell 3 of the third row, there may be a zero or a single signal depending on the transfer signal at the second output of the cell 2 of the second row. However, changing this signal does not affect the output signals of cell 3. In this cycle, the contents of the second cell trigger lines are rewritten to the third cell cell triggers, (N-2) bit of the first multiplier is rewritten from trigger 7 of the second column of the first oblique matrix 7 , 1 in cell 3 and fed to the inputs of cells 1 of the third row, the value of the highest bit of the product from the third output of cell 2 of the first row is written to the second trigger 7 of the first pair of the second column of the second row of the third oblique matrix The second row enters the second pair of operands, the remaining bits of the first multiplier are rewritten into the triggers 7 of the third column of the first oblique matrix 7.1. In this tact, in the first row receive a partial amount ripo izvesheni second multiplicand on the N-th bit of the second multiplier, which

enters the third input of cell 3 and cell 1 of the first row. At the same time, in the third line, a partial sum of the product of the first multiplied by (K-2) -th bit of the first multiplier is added, which is added to the result obtained earlier. In the second line get the second digit of the highest bit of the product.

After 2p + 1 clock cycles, the result of the product of the first pair of numbers is obtained at the outputs 13 (most significant bits) and at the outputs 10 (least significant bits) of the device. The result of the product of the following pairs of numbers is obtained every 3 cycles. The highest bit in the + A-B operation is formed at the first output 12 of the device.

Division operations,

In cells 3 at the inputs of the second and division control, single signals are installed, and at the third, the control inputs of cells 2, the left signals (Table 1). This allows setting elements 25 of cells 1 for logical repetition to break the chain of propagation of transfers between cells 2 and use cells 2 as cells 1.

In the first cycle, the second information input of cell 2, the second information inputs of cells 1 and the installation input of triggers 7 of the second oblique matrix 7.2 and 2N divisible digits are supplied, which are recorded in the corresponding triggers 31 of cell 2, triggers 23 of cell 1 and the corresponding triggers 7 of the second oblique matrix 7.2. Bus 9 receives N splitter digits, which write 22 cells of the first row into triggers. Using cell 2 as cell 1 allows you to shift the dividend by one bit to the left relative to the divisor. The division operation is performed according to the algorithm without restoring the remainder. The subtraction of the next remainder of the divider corresponds to the summation of the additional divider code.

The first digit of the first quotient (formed at the second output of cell 2 of the first row, the unit (zero) signal of which indicates a positive (negative) current balance. The first remainder is

the dividend is formed on the third outputs of the cells 1 of the first row.

In the second cycle, a single (zero) signal may be received from the second output of cell 2 of the first row, second, fifth, and sixth, single (zero) signals will be output to the second input of the second cell, and therefore in adders 29

cells 1 of the second row can be subtracted (summed) from the current balance code. The first digit of the quotient from the second output of cell 2 of the first row is written into the first trigger 7 of the first pair of the first column of the third oblique matrix 7.3. The first divider from the trigger 22 cells 1 of the first row on the fourth output is copied into similar triggers of the cells of the second row of the third information inputs (in the first cell 1 through the cell 3 of the second line) “The first remainder of dividing the first pair of numbers from the third outputs of cells 1 of the first line is written into the triggers 31 cells 2, the triggers 23 cells 1, the remaining bits of the dividend with the trigger 7 ervoy second oblique lines of the matrix in 7.2 rewrite 7 triggers the second row of the same matrix and the flip-flop 23 N-1 th cell of the second row. In cells 1 and cell 2 of the second line, the second digit of the first quotient and the second remainder of dividing the first pair of numbers is formed. At the same time, a second pair of operands enters the first line of buses 8 and 9 and the first digit of the second quotient and the first remainder of dividing the second pair of numbers are formed in the cells of the first row,

The result of the quotient of the first pair of operands is obtained in n clocks at the outputs 12, and the remainder at the outputs 10. The result of the calculations of the subsequent pairs of numbers is obtained at these outputs after every clock cycle.

Elements And 25 cells 1 are set to logical repetition. At the device input 17, a zero signal is set, in connection with which cells 2 participate in the computational process as cells 1.

In the first cycle, the second information input to the cell 2 of the highest bit gives a zero signal.

and bus 8 - (2N-1) -digit code of the root mantissa, which is recorded in the trigger 31 of cell 2, the trigger of 23 cells 1 and the trigger 7 of the first row of the second oblique matrix 7.2. In the triggers of 22 cells 1 of the first row, a zero code is written. The computational process involves only cell 2 and two cells 1 of the most significant bits of the first row of the matrix, in which the code of the operating system, С, is written. This dsod is summed with code 111, which is set on the outputs of elements 28 and 33 of these cells. As a result, the first digit of the root, which is formed at the third outputs of the respective cells 1, is determined.

In the second cycle, the first digit Z of the second output of cell 2 of the first row is written to the first trigger 7 of the first pair of the third column of the oblique matrix 7.3,. and from the third outputs of the corresponding cells 1 of the matrix and the triggers 7 of the first row of the second oblique matrix 7.2, the digits of the first radix are rewritten into the triggers of the cells of the second row. Cell 2 and the first three cells 1 of the second row take part in the computational process. The remaining cells 1 with a single signal from the second output of cell 3 are set to repeat. original information. To the shifted remainder, the following two digits of the root expression are added to the right. The code thus generated is summed with another code, also formed from two parts. The first part is equal to the bit size EXCLUSIVE OR digits Z1 with the code OZ1 and is formed in the cells 2 and 1 of the second line of the device. The second part is equal to code 11 and is formed in the second and third cells 1 of the same line. As a result, the second digit of the root, which is formed at the second output of the cell 2 of the second row, and the second remainder at the third outputs of the cells 1, is determined. At the same time, the second radix is fed to the first row. Subsequently, the extraction of the root is carried out according to the algorithm without restoring the residue. In the i-M cycle, to the next one, shifted by 1 bit to the left, the next two are added to the remainder on the right.

figures of the radixed C, C ,; and a code is obtained which is added to the code Zj @ (OZ .. .Zj). 11. The action Zj © О is performed on the elements EXCLUSIVE OR 33 cells 2, and the action Zj ® (OZ, ... Zi) - on the elements 28 cells 1. At the same time, the i-e radicata enters the first line of the device,

In the N-M cycle, the penultimate remainder is combined with the last digit and summed up with the code Z ,,., @ (OZ ... Z.). 1, a to the first line comes the N-e radix.

The result of the extraction of the root is formed in the N-M clock at the outputs 12 (the result of the extraction of the roots) and the outputs 10 (the remainder). The result of extracting the next radicand is obtained after one cycle.

Sorting operation

Before starting work from the computer, the synchronization unit receives a general reset signal through the input bus 20 of the device. At the output of the decoder 58, a signal appears that resets all the triggers of the device. The clock pulses of the generator 54 pass through the element 56 to the C inputs and the P bhod of all the device triggers (the zero signal at the output of the decoder 58 does not interfere with their passage). At the same time, the clock pulses of the generator 54 through the element 55 and 55 (when sorting at the second input of the element 55 are a single signal) arrive at the counter 59. When the counter counts N cycles, a single signal appears at the output of the decoder 58, which closes the element 56 and stops further receipt of clock pulses in the device. In the (N + 1) -M cycle, a single signal appears at the sort control output.

At the second input of the cell 3 of the first line, a single signal is set. At the fourth inputs of the cells of all 3 lines, single signals are installed from the first outputs of blocks 5 (from the inverse outputs of the flushed triggers 48). Since the control input of block 5 of the last row is connected to the zero bus, and the triggers are reset, the zero signal on the third outputs is fed to the control input of all blocks 5, and on the second outputs - on

Wrong control inputs of all cells 1, do not release readings of the contents of the flip-flops 22 through the element 26 to the eighth outputs of cells 1 and the device output 11.

Sorting is done through boron sampling, in this case, the maximum number, separating it from the rest of the numbers, and further selecting the largest number from the remaining n; in relation to the selected maximum number. This algorithm, whose scheme is shown in FIG. 8, is

is associated in an associative way.

In the first measure. The N-bit code of the first sorted number is fed through bus 9 and is written to the triggers of 22 cells 1 of the first row.

In the second cycle, the contents of the .22 flip-flops from the fourth outputs of cells 1 of the first row are recorded at the corresponding third inputs into the same-named triggers of the same cells of the second row, and the triggers of the first row record the code of the second sortable number.

After N ticks, codes of N sorted numbers will be recorded in all lines of the device.

Simultaneously sorted numbers are passed through blocks 4 to form the maximum number from the given n numbers. In schemes 4, the states of the same-named bits of the sorted numbers are analyzed. If the i-th bit of all codes contains all zeros, then a single signal is set in it, and if at least one unit, a zero signal is set. Before starting, the triggers of 44 blocks 4 are reset and O are set at one of the inputs of the OR 45 elements. The second inputs of these elements 45 receive the codes of the sorted numbers. The triggers 44 are set to single states, to the second input of which a single signal arrives. The state of these triggers does not change in the future. The generated code of the maximum number for p clocks at the outputs of blocks 4 is fed to the corresponding inputs of the elements OR 27 of all cells 1.

In (n + 1) th cycle, a single signal is received at the input of the sorting control of cells 3 of all lines, which passes through AND 38 to the third control output of cells 1 and allows viewing of the recorded array

: 0

five

0

five

In the vertical direction, viewing is conducted from the bottom up, i.e. from the Nth row to the first, In the horizontal directional-1, from left to right, the elements OR 27 and the elements AND 24 cells 1 form a chain of sequential viewing of the contents of the triggers of these 22 cells. The purpose of viewing is not interrupted if there are 1 in the corresponding cells on the third information inputs or if all the bits of the same name contain all O. The presence of a single signal on the information input of circuit 5 indicates that the i-th row contains the maximum number. This single signal enters the trigger 47 of block 5 and through the element 52 at the second output, permitting the reading of the maximum number from the triggers of 22 cells 1 through the element 26 at the corresponding eighth outputs of this line.

A single signal at the third output of block 5, where the maximum number is found, is fed to the control input of block 5 located above the line. It prohibits reading from this string S if 1 is also set at the information input. Therefore, first the maximum number is read from the low i-th line, and then from (1-1) th, (1-2) -th, etc., if there are several maximum numbers in this array.

A single signal from trigger code 47 enters through the element. OR 6 to output 14 and controls the reading of the maximum number. In the case of the presence of several maximum numbers, a single signal at output 14 is present until the last maximum number is read. A zero signal at output 14 allows the following numbers to be viewed.

If in the trigger 47 i-th line is written 1 (1 at the second output,

0 and on the fourth control inputs of the cells 1) then from this line the maximum number is output to the output 11 of the device through the AND 26 element along the eighth outputs of the cells 1

5 lines. Simultaneously from the trigger 47, a single signal is sent to the element OR 50 and through the element 53 EXCLUSIVE OR is recorded at the S input to the trigger 48. At the first output

five

0

 one

A zero signal appears, which, arriving at the quarter input of cell 3 of this line, establishes 4dc | About on the fourth output of cell 3 and excludes this line from further viewing. Then O from the fourth output of cell 3 passes the entire line, enters the information input of the block 5 of this line and through the OR element 49 via the R input is written to the trigger 47. The generated O on the third output allows reading the maximum word from the lines above, and O at the fourth exit, it indicates the end of the shift from the given line.

The next viewing of the sorted numbers begins after reading 20 of all the maximum numbers in the given array and the appearance of the zero signal at the output 14 of the element OR 6.

Claims (3)

Claims 25 55 one . A multifunctional computing device containing a matrix of cells, a column of N control cells and a column of N additional cells (N is the operand width), the first control and the first information inputs of the nth cell of the pth row of the matrix (, 2 ,. ..., N-1;, 2 ,, .., N) are connected respectively to the first and second outputs of the (n + 1) -th cell of the pth row of the matrix, the first control and the first information inputs of the pth cell N-ro columns of the matrix are connected respectively to the first and second outputs of the p-th control cell of the column. Second output of the p-th cells of the first column of the matrix are connected to the first information input of the pth additional cell of the column, the second information input of the cell is ta-th (t  2,3N) row and n-th column matrix connected to the third output of the cell (ta-1) -th row (n + 1) -th column of the matrix, the second information input of the p-th cell of the first row of the matrix is the p-th bit of the first input bus operand device, the third output n cell of the first column of the matrix is connected to the second information input (p + O of the additional cell of the column, the third output of the cell of the Nth row 5 о372712 is the p-th bit of the output tire of the remainder of the device, the third ir-information input of the z-th (, 2, ..., t-2) cells of the t-th row of the matrix is connected to the fourth output of the z-th cell (t-1 ) -th line, the third information input of the –th cell of the th line (m, ..., N) is connected to the fourth output of the –th cell (P1-1) of the –th line, the third information input thirty 20 25 ,  (t-1) -th cell of the m-th row of the matrix is connected to the third output of the m-th control cell of the column, the fourth output of the n-th cell of the n-th row of the matrix is connected to the first input (n + 1) -th control the cell of the column, the third information input of the pth cell of the first row of the matrix is the pm bit of the second input bus of the device operand, the second control input of the t cell of the pth row of the matrix is connected to the right output (t-1) - cells of the same row of the matrix, the second control input of the first cell of the pth row is connected to the fourth output of the pth control cell of a hundred The third control input of the pth cell of the pth row of the matrix is connected to the fifth output of the pth control cell of the column, the third control input of the first cell of the bth row of the matrix is connected to the first output of the mth additional cell of the column, the third control input of the i-th cell of the matrix row (, ..., N; i 2, ..., j-1) is connected to the sixth output of the (1-1) -th cell of the same row of the matrix, the third control input The j-th cell (-2) -th row of the matrix is connected to the second output (-2) -th control cell of the column, the third control input of the t-th cell (L-2) -th row of the matrix (, ..., N) subkey n to the fifth output (s-1) th cell in the same row of the matrix, a second data input of the first additional column of cells is the 2N-M per discharge howling input operand bus device, wherein the cell matrix comprises an adder element. .: the mentor is EXCLUSIVE or and the AND element, with the first input of the EXCLUSIVE element or the cell being the second 55 control input and the fifth output of the matrix cell, the second input of the element EXCLUSIVE OR the cell is connected. to the output of the element And the matrix cell, the output of the element is EXCLUSIVE OR whose35 40 45 50 The matrix is connected to the first information input of the matrix cell adder, the output of the cell totalizer is the third output of the matrix cell, the transfer output of the matrix cell adder is the second output of the matrix cell, the transfer input of the matrix cell adder , the first input of the cell element AND the matrix cell is the first control input of the matrix cell and the first output of the matrix cell, the second input of the (n + 1) -and control cell column and the first control input of the nth additional the column cells are connected to the second output (n + 1) of the additional cell of the column, the first control input of the Nth additional cell of the column is connected to the bus value of the logical zero of the device, the sixth output of the pth control cell of the column is connected to the second control input the pth additional cell of the column, the third input of the first control cell of the column is the first bit. the third input bus of the operand of the device, the third control input of all additional cells of the column is the input control bus of the device multiplication, the second input of the first control cell of the column is connected to the bus of the logical unit value of the device, and the control cell contains four elements OR And, the first input of the first element OR of the control cell is the third input of this cell, the second input of the first element OR of the control cell is connected to the first inputs of the first and second element in the AND of the second element OR of the control cell, and is the control input of the control cell division, the first input of the third AND element of the control cell is connected to the third input of the first OR element of the control cell, the first input of the third OR element, the input of the third element OR of the control cell, the second input of the second element OR of the control cell and is the control input for extracting the square root of the control cell, the output of the second element OR of the control cell 0 five  . 5 0 5 0 5 0 5 The fourth input of the control cell AND is connected to the first input; the second input of the fourth control AND element is connected to the second inputs of the first, second and third control AND elements; this is the second input of the control cell, the outputs of the second and third control AND elements the cells are connected respectively to the second the input of the third element OR of the control cell and the first input of the fourth element OR of the control cell, the second input of the fourth element OR of the control cell is the first input of the control cell, the output of the fourth element AND of the control cell is the sixth output of the control cell, the output of the third the OR cell of the control cell is the fifth output of the control cell, the output of the first cell AND of the control cell is the second output of the control cell, the output of the fourth element OR of the control cell is the third output of the control cell, the output of the first element OR of the control cell is the first output of the control cell, characterized in that, in order to extend the functionality by introducing a sorting operation and increasing the performance of the device, it additionally contains N units for selecting the maximum number, N read signal conditioning units, the first oblique trigger matrix consisting of (N-1). rows, n-row of which contains n triggers, oblique matrix of pairs of triggers, consisting of (N-1) rows, n-row of which contains, n pairs of triggers, OR element, second oblique trigger matrix, containing (N-1) columns the pth column of this matrix contains n triggers, the eighth output of the pth cell of the pth column of the matrix is connected to the fourth information input of the (n + 1) th cell of the pth column of the matrix, the pth column of the maximum selection numbers connected to the third information input of the p-th cell of the first row of the matrix, the output p- about the maximum number selecting unit connected to a fourth data input of the p-th cell of the first row 15 matrix, the input of the first trigger of the nth row of the first oblique trigger matrix is the (n + 1) -th digit of the device's third input bus, the output of the nth trigger of the nth row of the first oblique trigger matrix is connected to the third input (n + 1) -th control cell of the column, output of the x-th trigger, where x, (j-1) -th row of the first oblique matrix of the trigger are connected to the input of the (x + 1) -th trigger of the same row of the first oblique matrix of the trigger, inputs first and second triggers of the n-th pair of the n-th row of the oblique matrix of pairs of flip-flops Here, respectively, to the second and third outputs of the nth additional cell of the column, the output of the first trigger of the pth pair (H-1) of the row of the oblique matrix of trigger pairs is the nth digit of the first output bus of the device, the output of the second trigger n -th pair (H-1) -th row of the oblique matrix of trigger pairs is the nth bit of the second output bus of the device result, the second output of the Nth additional cell of the column is NM bit of the first output bus of the device result, the third output N th extra cell column mc N-bit of the second output bus of the device result, the outputs of the first, second triggers of the x-th pair (-2) and rows of the oblique matrix of the pairs of flip-flops are connected to the inputs of the first and second triggers of the x-th pair (-1) of the of the oblique matrix of pairs of triggers, the input of the first trigger of the nth column of the second oblique matrix of triggers is (N + n) -M bit of the first input bus of the device operand, the output of the nth trigger of the nth column of the second oblique matrix of triggers is connected to the second information the entrance of the Nth cell (p + O th page ok matrix, the output of the x-th trigger (jl) -ro column of the second oblique trigger matrix is connected to the input of the (x + 1) -th trigger of the same column of the second oblique trigger matrix, the first output of the pth read signal generator unit is connected to the fourth the input of the p-th control cell of the column, the second output of the p-th block is formed 25 93727 6 neither the read signal is connected to the fourth control inputs of all cells of the pth row of the matrix, the control input of the nth read signal generation unit g is connected to the third output of the (ntl) th readout signal generation unit, the control input of the N-ro formation block the read signal is connected to the bus to the logical zero value of the device; the fourth output of the p-th block to form the read signal is connected to the p-th input of the OR element, the reset input of all the blocks of the formation-. t5, the read signals are connected to the reset output of the synchronization unit, the output of the OR element is the output bus of the read signal of the device, the information input of the pth output signal generation unit is connected to the fifth output of the pth cell of the N-th matrix column, the operation code input of the synchronization unit is the input bus of the operation code of the device, the general reset input of the synchronization unit is the input bus of the general reset of the device, the clock output of the synchronization unit is connected to the synchronous inputs of all triggers the output, the reset output of the synchronization block is connected to the reset inputs of all the device triggers a, the output of the sorting block synchronization sub-35 keys to the control inputs of the sort of all control cells of the column, the output of the division control of the synchronization block is connected to the inputs of the division control of all control cells the cells of the column, the output control of the square-root extraction of the synchronization unit is connected to the inputs of the control of the extraction of the square root of all control spaces of the 5th column, the seventh output of the d-th (d 1,,. . The NN) matrix cell is the dM bit of the device sorting output bus, each matrix cell additionally contains two triggers, an OR element and two AND elements, the second information input of the matrix cell adder is connected to the output of the first matrix cell trigger , the installation input of the first 5 trigger of the matrix cell is the second information input of the matrix cell, the installation input of the second trigger of the cell is three 1712 the second information input of the cell, the output of the second trigger of the matrix cell is connected to the second input of the first cell element of the matrix cell, the first input of the cell IL element and the first input of the second cell element, and the second input of the second matrix cell element is the fourth control input of the matrix cell, the output of the second element And the matrix cell is the seventh output of the matrix cell, the second input of the JiM element of the matrix cell is the fourth information input and the eighth output The matrix cells, the output of the element OR the matrix cells are connected to the first input of the third element and the matrix cell, the second input of the third element and the matrix cell is the third control input of the matrix cell, the output of the third element and the matrix cell is the sixth output f of the matrix cell, an additional cell matrix contains two triggers, the AND element, the EXCLUSIVE OR element and the adder, with the output of the first trigger of the additional cell connected to the first input of the element AND the additional cell, the second input of the element And complement The cell is the first control input of the additional cell, the output of the element AND the additional cell is connected to the first input of the element EXCLUSIVE OR the additional cell, the second input of the element EXCLUSIVE OR the additional cell is the second control input and the first output of the additional cell, the output of the second the trigger of the additional cell is connected to the first information input of the adder whose additional The key element of the EXCLUSIVE OR element of the additional cell is connected to the second information input of the additional cell adder, the transfer input of the additional cell adder is the first information input of the additional cell ID, the second output output of the additional cell adder, the output of the additional cell totalizer is the third output of the additional cell, the installation input the second trigger additional whose second input of the element OR is connected five five 0 five 0 50 The ki is the second information input of the additional cell, the installation input of the first additional cell trigger is the third control input of the additional cell, the control cell further comprises a fifth AND element, and the first input of the fifth And control cell element is the fourth input of the control the cell, the second input of the fifth element AND the control cell is the control input of the sorting of the control cell, the output of the fifth element AND of the control cell is the fourth output of the control cell cells, the synchronization unit contains a clock pulse generator, two elements AND, a binary counter, a decoder and a zero decoder, the output of the clock generator is connected to the first input of the first and direct input of the second element AND of the synchronization unit, the first output of the decoder is connected to the second input of the first element And the synchronization unit, the second and third outputs of the decoder are respectively the control outputs for dividing and extracting the square root of the synchronization unit, the information input of the digitizer The input of the operation code, the synchronization block, the binary counter count input is connected to the output of the first element AND the synchronization block, the binary counter reset input is the general reset input of the low-resolution block bit outputs of the binary counter are connected to the bit inputs of the zero decoder, the zero decoder output is connected to the inverse input of the second element And the synchronization unit, and is the reset output of the synchronization unit,. the output of the second element And the synchronization unit is the clock output of the synchronization unit, the overflow output of the binary counter is the output of the sorting control of the synchronization unit 2, The device according to claim 1; Each block of maximum number selection contains a trigger, an OR element, and an EXCLUSIVE OR element, with the first input of the OR element being the input of the maximum number selection block. nineteen to the forward output of the trigger, the output of the element OR is connected to the first input of the element EXCLUSIVE OR, the second input of the element EXCLUSIVE OR is connected to the bus of the logical zero value of the device, the output of the element EXCLUSIVE OR is connected to the setup input of the trigger, the inverse trigger output is the output of the chord's chord output, is the output of the chord's chord output to the installation input of the trigger, the inverse output of the trigger is the chord output of the chord . 3. The device according to claim 1, about tl and - chip}, with the fact that each block of the formation of the readout signal contains two triggers, three elements is the fourth output of the read signal forcing unit, the second input of the second element OR is connected to the forward output of the second trigger, the output of the second element OR is connected to the first input of the EXCLUSIVE OR element, the second input of the IC KEY or the element of the 10 device an EXCLUSIVE OR element is connected to the input of the asynchronous setup of the second trigger; the input of the asynchronous reset of the second trigger is combined with the second input of the first elefarit two trigger, three elements - OR AND element and EXCLUSIVE 5 element element OR, inverse second code SHSCH, JJlCMcn. „„ „„ „„ „-Ottsyutg-about PRPPKTM VIKHOPOM OR, the inverse input of the first element OR is combined with the input of the asynchronous installation of the first trigger and is the information input of the read signal generation unit, the direct input of the first element OR is the reset input of the read signal generation unit, the output of the first element OR is connected to the asynchronous reset input of the first trigger, the output of the first trigger is connected to the first inputs of the second OR element and the AND and B20 elements 25 the trigger is the first output of the block of the formation of the scheduling signal, the signal of the AND element is connected to the first input of the third IL element and is the second output of the read signal forming block, the second inputs of the AND element and the third OR are interconnected and control the input of the linking signal shaping unit, the output of the third element OR, is with the third output of the block of the formation of the readout signal. 93727 The fourth output of the second element OR is connected to the forward output of the second trigger, the output of the second element OR is connected to the first input of the EXCLUSIVE OR element, the second input of the EXCLUSIVE OR element is connected to the bus of the unit unit value, 10 output of the element EXCLUSIVE OR is connected to the input of the asynchronous installation of the second trigger, the input of the asynchronous reset of the second trigger is combined with the second input of the first elec - - 5 cops OR, inverse code of the second ment or inverse second code „„ „„ „„ „- from the PRPPKTM OCCUPATION the trigger is the first output of the block of the formation of the signal of the interlacing, the signal of the element AND is connected to the first input of the third element OR and is the second output of the block of the formation of the signal of the reading, the second inputs of the element AND and the third element OR are interconnected and control the input of the counting signal generation unit, the output of the third element OR is the third output of the reading signal generation unit. 9 oz oE  eight, FIG. 2 3 LM FIG. L3fj Fig. § FIG. 6 FIG. 7 Recordable for arrays 3 MQKCUMOflbHOW selection array words  the end Editor L. Pchelinska Order 387/53 Compiled by S. Silaev Tehred And, Popovich Proofreader T. Kopb Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Fie.8