RU2761135C1 - Counter with saving the number of units - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention relates to the field of computer technology and automation. The counter with the preservation of the number of units contains external inputs of the device D3, D2, D1, D0, external control inputs Y1, Y0, external outputs of the device Q3, Q2, Q1, Q0, external transfer output CR, synchronous D-triggers with work permit input CE 1₃, 1₂, 1₁, 1₀, multiplexers 2₃, 2₂, 2₁, 2₀, logic element OR-NOT 3, a two-bit binary counter 4, as well as an external input of work permits 5 and an external synchronization input 6.

EFFECT: ensuring that a given number of units can be stored in sets of consecutive counter states.

1 cl, 2 dwg, 2 tbl

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer technology and automation, is intended to generate multi-output code combinations and can be used in cryptography problems and minimization problems using a linear programming apparatus.

PRIOR ART

A counter with a variable counting module is known (Computer circuitry. Collection of tasks: textbook. - M .: NRNU MEPhI, 2012. - 240 p., Fig. 72, p. 79-81), containing a counter, a comparison circuit and an OR element, moreover, the outputs of the counter are connected to the first group of inputs of the comparison circuit, the second group of inputs of which is connected to the external inputs of the setting of the counting module, and the output of the comparison circuit is connected to the first input of the OR element, the second input of which is connected to the external input of the initial setting, and the output of the OR element is connected to input of synchronous setting of the counter to zero state. This counter allows you to quickly change (program) the conversion module.

The disadvantage of this device is the formation of sequential binary sets that do not preserve the number of single bits.

A known counter of a group structure with a variable module (RU No. 2617329 C1, IPC H03K 23/40, G06F 17/00, declared 03.21.2016, published 04.24.2017, bull. No. 12) containing a group of N counters 1 ₁ , 1 ₂ , ..., 1 _n , the first group of N comparison circuits 2 ₁ , 2 ₂ , ..., 2 _n , a group of N-1 adders 3 ₁ , 3 ₂ , ..., 3 _n-1 , the second group of N comparison circuits 4 ₁ , 4 ₂ , ..., 4 _n , the first group of N elements OR 5 ₁ , 5 ₂ , ..., 5 _n , the second group of N elements OR 6 ₁ , 6 ₂ , ..., 6 _n , decoder 7, multiplexer 8, group of N external inputs for setting the counting modules 9 ₁ , 9 ₂ , ..., 9 _n , external inputs for setting the total counting module 10, external inputs for setting the number of counters 11, external synchronization input 12, external reset input 13, external operation enable input 14, group of N external outputs 15 ₁ , 15 ₂ , ..., 15 _n , external transfer output of the counter 16. The counter operation algorithm is based on setting the lower counter groups to zero when the total module value in the current group is reached MA.

The disadvantage of this device is the formation of sequential binary sets that do not preserve the number of single bits.

A known generator of m-bit binary sequences with a non-decreasing number of ones (described in the Device for solving combinatorial problems SU No. 1672466 Α1, IPC G06F 15/20, declared 05/31/1989, published 08/23/1991, Bull. No. 31 and in the Device for calculating combinatorial functions RU No. 2006934 C1, IPC G06F 15/20, declared 07/01/1991, published 01/30/1994), containing a group of m boot triggers with direct and inverse outputs and initial setting in the initial state, a triangular matrix (of m columns and m rows ) bit triggers with an initial setting to zero, a group of AND elements and OR elements, which also form triangular matrices, and a group of OR output elements, combining the direct outputs of the triggers in the bit columns of the triangular matrix.

The disadvantages of this device are large hardware costs and low performance, which is associated with the sequential formation of the next state of the sequence.

The closest device of the same purpose to the claimed invention in terms of a set of features is adopted as a prototype, a counter of the group structure with the preservation of the number of units in groups (RU # 2736704 C1, IPC H03K 23/40, G06F 17/00, declared 03/17/2020, published on November 19, 2020, bull. No. 32) containing an external input N-bit data bus DI, an external output N-bit bus QO, a group of G group counters 1 ₁ , 1 ₂ , ..., 1 _g , the first group of G elements AND 2 ₁ , 2 ₂ , ..., 2 _g , a group of G elements OR 3 ₁ , 3 ₂ , ..., 3 _g , block of intergroup transfers 4, external synchronization input CLK, external input G bit buses permitting loading into EL groups, parallel counting of EP groups and sequential counting of EU groups, external CO transfer output. Each of the group counters 1i (where i = 1, ..., G) consists of (Ki) bits (where N = K1 + K2 + ... + KG) and contains (Ki) D-flip-flops 5 ₁ , 5 ₂ , 5 _(Ki) , a transfer generator 6, a group of (Ki) code generators with the preservation of the number of units 7 ₁ , 7 ₂ , ..., 7 _(Ki) , a group of (Ki) multiplexers MX 8 ₁ , 8 ₂ , ..., 8 _(Ki) , an element OR 9 and internal (Ki) bit line QT of the trigger outputs.

The disadvantage of this device is the execution of transitions for each input set of units Ki only one transition graph and large hardware costs for the formation of the next state code.

OBJECT OF THE INVENTION

An object of the invention is to provide hardware that stores the number of ones in successive counter states.

In the problems of cryptography in the formation of block ciphers, the device is designed to implement scattering and mixing operations in sets of round functions with simultaneous parallel processing of several groups of data on different transition graphs.

In combinatorial and integer linear programming problems, the device is designed to generate permutations without repetitions.

The technical result of the invention is to expand the arsenal of tools for the same purpose, in terms of the ability to save a given number of units in sets of sequential counter states, to control the selection of the transition graph for counter states and to reduce hardware costs.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved in that the counter, while maintaining the number of units, contains external inputs of the device D3, D2, D1, D0, external control inputs Y1, Y0, external outputs of the device Q3, Q2, Q1, Q0, external transfer output CR, synchronous D-flip-flops with CE input enable operation 1 ₃ , 1 ₂ , 1 ₁ , 1 ₀ , multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ , NOR gate 3, two-digit binary counter 4, and also contains an external operation enable input 5 and external synchronization input 6,

moreover, the external inputs of the device D3, D2, D1, D0 are connected to the zero inputs of the corresponding multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ ,

external input of work enable 5 and external input of synchronization 6 are connected to the corresponding inputs of the same name for the enable of work and inputs C of synchronization of D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ 1 ₀ and binary counter 4,

external control inputs Y1, Y0 are connected to the corresponding address inputs S1, S0 of multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ and connected to the first and second inputs of the OR-NOT logic element 3, the output of which is connected to the input R of the synchronous setting of the counter 4 to the zero state, the output of which is the external carry output CR,

in addition, the output of the D-flip-flop 1 _{3 is} connected to the first and second information inputs of the multiplexer 2 ₂ and the third information input of the multiplexer 2 ₁ ,

the output of the D-flip-flop 1 _{2 is} connected to the first information input of the multiplexer 2 ₁ , and is also connected to the second and third information inputs of the multiplexer 2 ₀ ,

the output of the D-flip-flop 1 _{1 is} connected to the second information input of the multiplexer 2 ₃ , to the third information input of the multiplexer 2 ₂ , and to the first information input of the multiplexer 2 ₀ ,

the output of the D-flip-flop 1 _{0 is} connected to the first and third information inputs of the multiplexer 2 ₃ and to the second information input of the multiplexer 2 ₁ ,

moreover, the outputs of the multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 _{0 are} connected to the inputs D of the corresponding D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ 1 ₀ , the outputs of which are the corresponding external outputs of the device Q3, Q2, Q1, Q0.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a functional diagram of the proposed counter while maintaining the number of units. FIG. 2 shows a conventional graphic designation of the proposed meter. Table 1 shows the counter micro-operations performed. Table 2 shows the specified transition graphs of the counter.

FIG. 1-2, in tables 1-2 and in the text the following designations are accepted:

D3, D2, D1, D0 - external inputs of the device,

Y1, Y0 - external control inputs,

Q3, Q2, Q1, Q0 - external outputs of the device,

CR - external carry output,

G - transition graphs,

V1, V2, V3 - options for switching inter-bit transfer circuits,

С - sync inputs of the CT counter and T triggers,

CE - work permit inputs,

CR - external carry output,

CT - two-digit binary counter,

D - information input of the trigger,

K - number of units,

MX - multiplexer,

N = 4 - number of digits,

R - synchronous input of setting the trigger to zero state, S1, S0 - address inputs of multiplexers, Τ - trigger.

1 ₃ , 1 ₂ , 1 ₁ 1 ₀ - synchronous D-flip-flops with CE input of work enable,

2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ - multiplexers,

3 - logical element OR-NOT,

4 - two-digit binary counter,

5 - external input for permission to work CE,

6 - external synchronization input C.

The counter keeping the number of units contains external device inputs D3, D2, D1, D0, external control inputs Y1, Y0, external device outputs Q3, Q2, Q1, Q0, external transfer output CR, synchronous D-flip-flops with CE input of enable 1 ₃ , 1 ₂ , 1 ₁ 1 ₀ , multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ , OR-NOT logic gate 3, two-bit binary counter 4, and also contains an external enable input 5 and an external synchronization input 6.

The external inputs of the device D3, D2, D1, D0 are connected to the zero inputs of the corresponding multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ .

External input of work enable 5 and external input of synchronization 6 are connected to the corresponding inputs of the same name of the enable of work and inputs C of synchronization of D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ 1 ₀ and binary counter 4.

External control inputs Y1, Y0 are connected to the corresponding address inputs S1, S0 of multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ and connected to the first and second inputs of the OR-NOT logic element 3. The output of the OR-NOT logic element 3 is connected to the input R synchronously setting the counter 4 to zero, the output of which is the external transfer output CR.

The output of the D-flip-flop 1 _{3 is} connected to the first and second information inputs of the multiplexer 2 ₂ and the third information input of the multiplexer 2 ₁ .

The output of the D-flip-flop 1 _{2 is} connected to the first information input of the multiplexer 2 ₁ , and is also connected to the second and third information inputs of the multiplexer 2 ₀ .

The output of the D-flip-flop 1 _{1 is} connected to the second information input of the multiplexer 2 ₃ , to the third information input of the multiplexer 2 ₁ , and to the first information input of the multiplexer 2 ₀ .

The output of the D-flip-flop 1 _{0 is} connected to the first and third information inputs of the multiplexer 2 ₃ and to the second information input of the multiplexer 2 ₁ .

The outputs of the multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 _{0 are} connected to the D inputs of the corresponding D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ 1 ₀ .

Outputs of D-flip-flops _{1 3} , 1 ₂ , 1 ₁ 1 ₀ are the corresponding external outputs of the device Q3, Q2, Q1, Q0.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows. The proposed counter allows generating N bit code combinations (N = 4) at the external outputs Q of the counter, in which a given number of K units are stored. In this case, the device can be set (programmed) single values at the corresponding external data inputs D3, D2, D1, D0 (K≤N).

The proposed counter is implemented on four synchronous D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ 1 ₀ . On the external control inputs Y1, Y0, the option number (V1, V2 or V3) of inter-bit transfer circuits switching or the boot mode is set. Table 1 shows the micro-operations performed (load or shift) and inter-bit transfer chains. For example, variant V1 and 0-3-2-1-0 correspond to the following interdigit shifts: from the 0th digit to the 3rd digit, from the 3rd digit to the 2nd digit, from the 2nd digit to the 1st discharge and from 1st digit to 0th digit. All inter-bit shifts are carried out simultaneously on the 0/1 edge of C sync signals at external input 6.

The counter makes transitions in accordance with the graphs of states at a single value of the enable signal CE at the external input 5 in accordance with the graphs of states G. The functioning of the counter is shown in Table 2 in the form of graphs of transitions G, a sequence of states. The vertices of the graph indicate the values of the decimal status codes of the outputs Q (Q3 is the most significant bit, Q0 is the least significant one). In the number of column G, the first digit indicates the number of units in states, and the second indicates the ordinal number. For example, column G25 - the status code bits Q3,…, Q0 contain two units, and digit 5 is the ordinal number of the column. The counter is set to the initial state (the first left vertex of the graph) in the loading mode (Y1 = 0, Υ0 = 0). Columns G of the same name in Table 2 indicate the same sequence of transitions between states.

With one unit (K = 1 out of 4) and three units (K = 3 out of 4), the transition graphs, respectively, G11, G12, G13 and G31, G32, G33 are determined only by the option number (V1, V2 or V3) of switching inter-bit transfer circuits for all matching seed values. With two units (K = 2 out of 4), transitions are possible along six columns G21, ..., G26, depending on the option number (V1, V2 or V3) of switching inter-bit transfer circuits and on the initial data at the inputs D3, D2, D1, D0 or the state set at the outputs when changing the switching option (V1, V2 or V3). Columns G23, G24 and G26 (with K = 2) of the corresponding options (V1, V2 or V3) of switching inter-bit transfer circuits contain only two vertices for stable states of the counter.

In addition, the device counts clock cycles with a two-bit binary counter 4. In this case, a single value of the carry signal CR = 1 is formed at every fourth clock cycle. Synchronous setting at input R to the initial zero state of counter 4 is carried out in the download mode (Y1 = 0, Υ0 = 0).

The proposed counter works as follows. The counter operation algorithm is as follows.

Before starting work, in the parallel loading mode (Υ1 = 0, Υ0 = 0), the initial code value containing K units is set at the external inputs D3, D2, D1, D0. Writing to D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ 1 _{0 is} carried out according to the sync signal C at external input 6 with a single value of the CE enable signal at external input 5. At the same time, a single value is formed at the output of the OR-NOT logic element 3, which is transmitted to the input R of counter 4, through which counter 4 is synchronously set to zero.

Further, on the control inputs Y1 and Y0, a code is set in accordance with Table 1, corresponding to the number of the option (V1, V2 or V3) of switching inter-bit transfer circuits. Transitions to the following states in accordance with the graphs G are carried out on the following clock signals C at external input 6. The values from the outputs of the synchronous D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ 1 ₀ are transmitted to the external outputs of the device Q3, Q2, Q1, Q0. At the same time, in the two-bit binary counter 4, the clock signals C are counted, and at every fourth clock cycle, a unit value is formed at the output of the counter 4, which is transmitted to the external transfer output CR = 1.

Further, in the process of operation, before the next clock signal C, you can change the code value at the control inputs Y1 and Y0 in accordance with Table 1, corresponding to the new option number (V1, V2 or V3) of switching inter-bit transfer circuits. In this case, the device will continue transitions in accordance with the specified graph G, starting from the state set at the previous time, and the binary counter 4 will also continue counting from the current value.

In addition, during operation, before the next clock signal C, you can set a new required code value at the external inputs D3, D2, D1, D0 containing K units and set the parallel loading mode (Y1 = 0, Υ0 = 0), in which the code value will be loaded into D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ 1 ₀ by sync signal C at external input 6 and at the same time counter 4 is synchronously set to zero.

In comparison with the prototype in the proposed device, hardware costs are reduced, because there are no formers of the next state, and the values of the code of the next state are carried out by specifying the switching option of inter-bit transfer circuits between the counter bits.

The above information allows us to conclude that the proposed counter corresponds to the claimed technical result - it implements the generation of code combinations at the outputs while maintaining the number of units in sets of sequential counter states, has the ability to set the initial state of the counter and set the switching option of inter-bit transfer circuits between the counter bits for the corresponding transition graphs and also reduced hardware costs.

Claims (9)

The counter with saving the number of units contains external device inputs D3, D2, D1, D0, external control inputs Y1, Y0, external device outputs Q3, 02, Q1, Q0, external transfer output CR, synchronous D-flip-flops with CE input of enable 1 ₃ , 1 ₂ , 1 ₁ , 1 ₀ , multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ , OR-NOT logic gate 3, two-bit binary counter 4, and also contains an external input for enable 5 and an external input for synchronization 6, moreover, the external inputs of the device D3, D2, D1, D0 are connected to the zero inputs of the corresponding multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ , external input of work enable 5 and external input of synchronization 6 are connected to the corresponding inputs of the same name of the enable of work and inputs C of synchronization of D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ , 1 ₀ and binary counter 4, external control inputs Y1, Y0 are connected to the corresponding address inputs S1, S0 of multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 ₀ and connected to the first and second inputs of the OR-NOT logic element 3, the output of which is connected to the input R of the synchronous setting of the counter 4 to the zero state, the output of which is the external carry output CR, in addition, the output of the D-flip-flop 1 _{3 is} connected to the first and second information inputs of the multiplexer 2 ₂ and the third information input of the multiplexer 2 ₁ , the output of the D-flip-flop 1 _{2 is} connected to the first information input of the multiplexer 2 ₁ , and is also connected to the second and third information inputs of the multiplexer 2 ₀ , the output of the D-flip-flop 1 _{1 is} connected to the second information input of the multiplexer 2 ₃ , to the third information input of the multiplexer 2 ₂ , and to the first information input of the multiplexer 2 ₀ , the output of the D-flip-flop 1 _{0 is} connected to the first and third information inputs of the multiplexer 2 ₃ and to the second information input of the multiplexer 2 ₁ , moreover, the outputs of the multiplexers 2 ₃ , 2 ₂ , 2 ₁ , 2 _{0 are} connected to the inputs D of the corresponding D-flip-flops 1 ₃ , 1 ₂ , 1 ₁ , 1 ₀ , the outputs of which are the corresponding external outputs of the device Q3, Q2, Q1, Q0.

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