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KR970072187A - Method for forming gate oxide film of semiconductor device - Google Patents

Method for forming gate oxide film of semiconductor device Download PDF

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Publication number
KR970072187A
KR970072187A KR1019960011717A KR19960011717A KR970072187A KR 970072187 A KR970072187 A KR 970072187A KR 1019960011717 A KR1019960011717 A KR 1019960011717A KR 19960011717 A KR19960011717 A KR 19960011717A KR 970072187 A KR970072187 A KR 970072187A
Authority
KR
South Korea
Prior art keywords
ramp
temperature
reactor
oxide film
gate oxide
Prior art date
Application number
KR1019960011717A
Other languages
Korean (ko)
Other versions
KR100187662B1 (en
Inventor
권오정
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019960011717A priority Critical patent/KR100187662B1/en
Publication of KR970072187A publication Critical patent/KR970072187A/en
Application granted granted Critical
Publication of KR100187662B1 publication Critical patent/KR100187662B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 어닐링 공정시 온도가 높아짐에 따라 수반되는 수평 저하를 고려하여 870℃ 이하에서 진행하여 게이트 산화막의 구조 변화에 의한 수명 저하를 막아 게이트 산화막의 신뢰성을 향상시킬 수 있는 반도체 소자의 게이트 산화막 형성 방법이 개시된다.The present invention relates to a method for forming a gate oxide film of a semiconductor device which can improve the reliability of a gate oxide film by preventing a decrease in lifetime due to a change in structure of a gate oxide film at a temperature lower than 870 캜, A method is disclosed.

Description

반도체 소자의 게이트의 산화막 형성 방법Method for forming oxide film of gate of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도 본 발명에 따른 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device according to the present invention.

Claims (8)

반도체 소자의 게이트 산화막 형성 방법에 있어서, 웨이퍼를 질소 분위기하의 반응로 내부로 로딩하는 단계와, 상기 로딩 단계로부터 공정가스 분위기하에서 상기 반응로 내부의 온도를 상승시키는 제1램프-업(Lamp-Up)시키는 단계와, 상기 웨이퍼를 공정가스 분위기하에서 산화시키는 단계와, 상기 산화 단계로부터 질소 분위기 하에서 상기 반응로 내부의 온도를 상승시키는 제2램프-업(Lamp-Up)시키는 단계와, 상기 웨이퍼를 질소 분위기에서 어닐링하는 단계와, 상기 어닐링 단계로부터 질소 분위기에서 반응로 내부의 온도를 낮추는 램프-다운(Lamp-Down)시키는 단계와, 상기 반응로에서 웨이퍼를 언로딩하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.A method for forming a gate oxide film of a semiconductor device, comprising: loading a wafer into a reaction furnace under a nitrogen atmosphere; and performing a first ramp-up A step of oxidizing the wafer under a process gas atmosphere, and a second ramp-up step of raising the temperature inside the reaction furnace in a nitrogen atmosphere from the oxidation step, The method comprising: annealing the substrate in a nitrogen atmosphere; ramping down a temperature inside the reactor in a nitrogen atmosphere from the annealing step; and unloading the wafer in the reactor A method of forming a gate oxide film of a semiconductor device. 제1항에 있어서, 상기 웨이퍼의 로딩시 상기 반응로내의 온도는 600℃인 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.The method according to claim 1, wherein the temperature in the reactor is 600 ° C when the wafer is loaded. 제1항에 있어서, 상기 제1램프-업 단계는 약 5℃/min의 온도상승비율로 반응로내의 온도를 800℃까지 상승시키는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.2. The method of claim 1, wherein the first ramp-up step raises the temperature in the reactor to 800 < 0 > C at a ramp rate of about 5 [deg.] C / min. 제1항에 있어서, 상기 제2램프-업 단계는 반응로 내의 온도를 870℃까지 상승시키는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.2. The method of claim 1, wherein the second ramp-up step raises the temperature in the reactor to 870 < 0 > C. 제1항에 있어서, 상기 어닐링 공정은 870℃ 온도에서 20분간 실시하는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.The method according to claim 1, wherein the annealing is performed at 870 캜 for 20 minutes. 제1항에 있어서, 상기 램프-다운 단계는 약 3℃/min의 온도하강비율로 600℃로 반응로내의 온도를 낮추는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.The method of claim 1, wherein the ramp-down step lowers the temperature in the reactor to 600 占 폚 at a ramp-down rate of about 3 占 폚 / min. 제1항에 있어서, 상기 산화 공정은 800℃온도하에서 산소가스를 이용하여 진행되는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성방법.The method according to claim 1, wherein the oxidation process is performed using oxygen gas at a temperature of 800 ° C. 제1항에 있어서, 상기 산화 공정은 800℃ 온도하에서 산소 및 수소가스를 이용하여 진행되는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.The method according to claim 1, wherein the oxidation process is performed using oxygen and hydrogen gas at a temperature of 800 ° C. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960011717A 1996-04-18 1996-04-18 Method for fabricating gate oxide film of semiconductor device KR100187662B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960011717A KR100187662B1 (en) 1996-04-18 1996-04-18 Method for fabricating gate oxide film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960011717A KR100187662B1 (en) 1996-04-18 1996-04-18 Method for fabricating gate oxide film of semiconductor device

Publications (2)

Publication Number Publication Date
KR970072187A true KR970072187A (en) 1997-11-07
KR100187662B1 KR100187662B1 (en) 1999-06-01

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