KR920004439Y1 - Data converting circuit - Google Patents

Abstract

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Description

Data conversion circuit

1 is an exemplary conversion format of word data to symbol data.

2 is a block diagram of the present invention.

3 is another operation timing diagram of the present invention.

* Explanation of symbols for main parts of the drawings

A: Data word storage section B: Upper data latch section

C: first lower data latch portion D: second lower data latch portion

E: Data symbol output section

The present invention relates to a data conversion circuit in a digital audio tape (DAT) recorder, and more particularly, to a circuit for converting word data into symbol data.

In general, in a DAT system, the analog / digital converted data is generally composed of 16 bits (Bit) and is reconfigured in 8 bit units to be processed.

The 48K mode, the 44K mode, and the 32K mode processed the data in the above-described manner. With the exception of the 32KHz-long play mode, the 12-bit audio data is reconfigured into 8 bits. Although there was no such processing circuit, the 32K-LP mode could not be applied to the DAT system.

Accordingly, an object of the present invention is to provide a data conversion circuit for converting word data in units of 12 bits into symbols in units of 8 bits.

Hereinafter, with reference to the accompanying drawings of the present invention.

FIG. 1 is a word-to-symbol conversion format in 32K-LP mode, and FIG. 2 is a block diagram of the present invention. A and B channels of an audio data word DTWORD are synchronized with the data clock DTCLK in 32KH-LP mode. (Ai, Bi) latches the upper 8 bits of data from the data word storage section A in synchronization with the latch word LCHCLK in a predetermined state and the data word storage section A for serial input of 12 bits each alternately. The upper data latch unit B, the first lower data latch unit C for latching the lower 4 bit data from the data word storage unit A in synchronization with the latch clock LCHCLK, and bus enable. A second lower data latch unit D for relatching the lower 4 bit data stored in the first lower data latch unit C in synchronization with a first pulse of the signal BUSEN, and the base enable signal BUSEN In synchronization with the second pulse of The upper data latch unit generates a second data symbol ABIL having 4 bits and outputting the first lower data latch unit C as the lower 4 bits and is synchronized with a first pulse of the bus enable signal BUSEN. Inputs the upper 8 bit data of channel A from B) to generate the first data symbol Aiu, and synchronizes with the third pulse of the bus enable signal BUSEN from B to B from the upper data latch B. It consists of a data symbol output section (B) for inputting the upper 8-bit data of the channel to generate a third data symbol (Biu).

3 is an operation waveform diagram according to the present invention, where 3a is a data word waveform DTWORD, 3b is a data word write waveform, 3c is a data clock waveform DTCLK, and 3d is A latch clock waveform LCHCLK, 3e is a bus enable waveform BUSEN, and 3f is a data symbol waveform DTSYBOL.

Based on the above-described configuration will be described the present invention in detail.

In the 32K-LF mode, as shown in FIG. 1, the 12-bit data Ai of the A channel and the 12-bit data Bi of the B channel are divided into upper 8 bits and lower 4 bits to separate the first 8 bits. Three data symbols (Aiu, ABil, Biu) are created. Referring to FIG. 2, the data word storage unit A synchronizes the data clock DTCLK with a 12-bit audio data word. DTWORD) serially.

At this time, as shown in FIG. 3, as shown in FIG. 3, the audio data word DTWORD of (3a) is synchronized with the data clock (DTCLK) as shown in (3c) while the high state of (3b) is rolled over the A channel (Ai). The 12 bits of are entered in order.

The 12 bits of which input is completed are inputted in parallel to the upper data latch unit B and the first lower data latch unit C in synchronization with the latch clock LCHCLK of 3d.

In this case, the upper data latch unit B stores the upper 8 bits, and the first lower data latch unit C stores the lower 4 bits.

During the next low state of (3b), 12 bits of the B channel (Bi) portion of the audio data word DTWRD are continuously input, and are input to the upper data latch portion B and the first lower data ratio portion C therebetween. The data is output as an 8-bit first audio data symbol Aiu through the data symbol output section E by the CA pulse of the bus enable signal BUSEN as shown in (3e), and the first lower data. The 4-bit data stored in the latch unit C is stored in the second lower data latch unit D.

Then, after all 12 bits of the B channel Bi of the audio data word DTWORD are input, the upper 8 bits of the 12 bits are assigned to the upper data latch unit B by the latch clock LCHCLK, and the lower 4 bits are the first. Each of the lower data latch units C is stored, and the data word storage unit A receives 12 bits of the A channel Ai of the audio data word DTWORD.

Meanwhile, data of the lower 4 bits of the A channel Ai input to the second lower data latch unit D and the first lower data latch unit C are inputted by the CA pulse of the bus enable signal BUSEN. The lower 4 bits of the input B channel Bi form 8 bits and are input to the data symbol output unit E through the data bus CW3 by CAB pulses to generate the second audio data symbol ABil.

After a predetermined time has elapsed, the upper 8 bits of data of the B channel Bi input to the upper data latch unit B are input to the data symbol output unit E by the CB pulse of the bus enable signal BUSEN. The 8-bit third data symbol Bi is output.

At this time, the 12-bit data of the A channel Ai is continuously stored in the data word storage A, and when all 12 bits are input, the 12-bit data is latched by the latch clock LCHCLK to repeat the above-described process.

Each 12-bit data of the A and B channels (Ai, Bi) inputted in this way is in the order of the first to third data symbols (Aiu, ABil, Biu), each 8 bits as shown in (3f) of FIG. Is output.

As described above, by converting the 12-bit word data into 8-bit data, there is an advantage that the 32K-LP mode can be easily applied to the DAT system.

Claims (1)

In a digital audio tape recorder, a data word storage unit (A) for alternately inputting 12 bits each of the A and B channels of an audio data word (DTWORD) in synchronization with a data clock (DTCLK) in a 32 kHz long play mode. And an upper data latch portion B for latching upper 8-bit data from the data word storage portion A in synchronization with the latch clock LCHCLK in a predetermined state, and the data in synchronization with the latch clock LCHCLK. A first lower data latch unit C for latching lower 4 bit data from the word storage unit A, and the first lower data latch unit C in synchronization with a first pulse of a bus enable signal BUSEN; Outputting the second lower data latch unit D in synchronization with a second lower data latch unit D for relatching the lower 4 bit data stored in the second pulse and the second pulse of the bus enable signal BUSeN. The upper 4 bits and the first lower bit A second data symbol ABil having the output latch C output as the lower 4 bits is generated, and synchronized with the first pulse of the bus enable signal BUSEN, the channel L from the higher data latch unit B is generated. Inputs the upper 8 bits of data to generate a first data symbol (Aiu), and synchronizes the upper 8 bits of data of the B channel from the upper data latch unit (B) in synchronization with the third pulse of the bus enable signal (BUSEN). And a data symbol output section (E) for inputting and generating a third data symbol (Biu).