JPS594920B2 - Control signal transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control signal transmission method in a digital complex system, and more specifically, to a control signal transmission method that can transmit control signals together with timing information from a main circuit block. Ru.

Conventionally, various digital complex systems consisting of a main circuit block that generates timing information and one or more subordinate circuit blocks that operate according to the timing information have been used. In this system, the timing information to be transmitted from the main circuit block to each subordinate circuit block and one or more control signals for controlling the operation of each subordinate circuit block are individually transmitted through dedicated lines. It is composed of

For this reason, the number of wiring between the main circuit block and the dependent circuit block side increases in proportion to the number of dependent circuits, and in a system with a large number of dependent circuit blocks, the wiring becomes complicated and reliability decreases. (The object of the present invention is to transmit data between the main circuit block and the slave circuit block without having to wire a large number of wires between the main circuit block and the slave circuit block.) It is an object of the present invention to provide a control signal transmission system that can transmit a control signal that is transmitted without any trouble especially by providing a dedicated line.

In the present invention, in a control signal transmission method for a digital complex system consisting of a main circuit block and at least one subordinate circuit block controlled by the main circuit block, a control signal is transmitted from the main circuit block to each of the subordinate circuit blocks. The transmitted signal includes an address word signal consisting of a flag bit indicating the start of one word, an address bit into which an address code unique to each of the dependent circuit blocks is inserted, and an address word signal for controlling the operation of each of the dependent circuit blocks. A composite multiplexed signal is obtained by serially multiplexing adjacent address word signals such that adjacent address word signals are separated by a predetermined period and the required control signal is placed within the predetermined period. , transmitting the composite multiplexed signal to all of the slave circuit blocks via a bus line connecting the main circuit block and each of the slave circuit blocks, and receiving the composite multiplex signal in each of the slave circuit blocks. , the decoder circuit provided in each of the dependent circuit blocks detects the beginning of the address word signal from the flag bit of the composite multiplexed signal, and then determines the address code of the composite multiplexed signal and determines the address code to which it belongs. A control signal transmission system is provided which is characterized in that when it is determined that a dependent circuit block is designated, a signal is sent to the accessed circuit to perform the required control.

The system of the present invention will be explained in detail below with reference to the drawings.

FIG. 1 shows an embodiment of a digital complex system using the control signal transmission method of the present invention.

This digital complex system 1 includes a main circuit block 4 including an address signal generation circuit 2 and a control signal generation circuit 3, and a plurality of subordinate circuit blocks 5a that perform predetermined operations according to commands from the main circuit block 4. ,5b,...
... (only two are shown in Figure 1). The address signal generation circuit 2 generates a clock signal S1 of a predetermined period and an address word signal S2 synchronized with this clock signal S1 (see Fig. 2A, b).
), the clock signal S1 is inputted via the bus line 6 to the decoder circuits 7a, 7b, . . . of each dependent circuit block 5a, 5b, . . . 3 is entered. The address word signal S, as shown in FIG. 2b, is composed of 6 bits per word, and the first bit is used as a flag bit and is set to always be "1". There is.

The remaining 5 bits (a to e) are used as address bits, into which a unique address code given to each required dependent circuit block is inserted. Each word constituting the address word signal S2 is output as a serially multiplexed signal at a predetermined time interval t1. On the other hand, the control signal generating circuit 3 is synchronized with the clock signal S1 and generates a signal for the necessary control signal existing in the period between one word and the following other word in the address word signal S2, that is, within the surplus bit t1. It is arranged to generate a control signal S, having bits X, Y. In the illustrated example (see Figure 2c), the control signal bits X and Y are arranged consecutively in each word of the address word signal, and when the bit state becomes [1], these control signal bits It is determined that each dependent circuit block is caused to execute a control of a predetermined content for each bit. Control signal S, is address word signal S
2 into the coupling circuit 3a, and are further serially multiplexed as shown in FIG. It is input as an address/control signal S4. This serially multiplexed address/control signal S
4 is decoded by each decoder circuit 7a, 7b, . from 9a,
Access signals S4a, S4b are applied to corresponding accessed circuits among the accessed circuits indicated by 9b, . . .
, ...... is output.

This access signal, for example S4a shown in FIG.
After 2 elapses, it changes from "O" to "1" for a predetermined time T3,
The accessed circuit 9a is caused to perform a predetermined operation. Although the case where the dependent circuit block 5a is addressed has been described above, the same applies even if other dependent circuit blocks are designated. Decoder circuits 7a, 7b, . . . provided in each dependent circuit block.
. . are for separating and decoding the address/control signal S4 using the clock signal S1, and one of the circuits 1 is shown in detail in FIG.

In Figure 3, 10, 11, 12, 15 to 20, 2
1, 22 and 23 constitute an address detection circuit,
10 is a shift register, 11 is a 4-bit binary counter, and 12 is a 4-bit binary counter.The contents of the 4-bit output from the 11 are decoded and outputs are sent to the terminal corresponding to the contents among the terminals 1 to 16. 13 is an R-S flip-flop, 14
are D-type flip-flops, 15 to 19 are AND gates, 20 is an OR gate, and 21 is an exclusive OR gate; 15 to 20 constitute a comparison circuit;
24 are gates. The decoder circuit 7a is the terminal 25
The address/control signal S4 from the bus line 8 is input to the terminal 26, and the clock signal S1 from the bus line 6 is input to the terminal 26.
is input, and this clock signal S1 is input to shift register 1.
0 as a shift pulse. Therefore, the address word signal S2 inputted from the terminal 25 is written into the shift register 10 sequentially at each rising edge of the clock signal S1. On the other hand, terminals 27 to 31 are each applied with a self-address signal of a logic level corresponding to a 5-bit address code attached in advance to the dependent circuit block 5a to which this decoder circuit 7a belongs. Therefore, for convenience of explanation, it is assumed that the self-address signal pre-assigned to this block 5a is (00101), and that the contents of a to e shown in FIG. 2b designate the block 5a, that is, ( 00101). Now, assuming that the period T5 is longer than the time length T4 of the word, "1" of the flag bit F in the word is at bit position 10 of the shift register 10.
a, the contents of the shift register 10 are such that only bit position 10a is [1] and the contents of other bit positions are [0].
”, the output of the gate 22 changes from “0” to “1”, and therefore, the reset terminal R of the binary counter 11 and the set terminal S of the R-S flip block 13 become “1”.
Then, the binary counter 11 is reset and at the same time R-
S flip-flop 13 is set and its Q output becomes [1]. That is, the shift register 10 is programmed for a predetermined period of time.
By inputting "O" and then inputting flag bit "D", a predetermined set/reset operation is performed. At this time, the output of the 4-bit binary counter 11 is (
0000), and only one terminal of the decoder 12 becomes "1". Therefore, in this case, the terminals 27 to 31 have (0, O,
1, 0, 1) are applied, the outputs of the AND gates 15 to 19 are all "0", and the output of the OR gate 20 is also "0". At this time, since the signal "O" corresponding to address bit a is applied to the terminal 25, the output of the gate 21 also becomes "0", and therefore the R-S flip-flop is not reset. Next, when the next clock signal is input, since terminal 16 of the decoder 12 is at "O", the gate 23 is in the open state, so this clock signal is input to the clock terminal C of the 4-bit binary counter 11. As a result, only two terminals of the decoder 12 become "1", and a signal with the same logic state as the signal applied to the terminal 28, that is, "O" in this example, becomes OR.
Appears at the output of gate 20. At this time, the address bit b (one "O") is applied to the terminal 25, so the R-S flip-flop 13 is not reset in this case as well.As can be seen from the above explanation, the clock signal S1
Each time a signal is inputted manually, the signal applied to terminals 27 to 31 is taken out from the OR gate 20 and sequentially compared bit by bit with address bits a to e, and when the bits are equal, the R-S flip-flop 13 is output. It is designed so that there is no need to reset it. After the match or mismatch between the specified address bit (00101) and the unique address bit (00101) applied to the terminals 27 to 31 is detected in this way, the clock signal S1 is further inputted. The contents of control bits X and Y are stored in bit positions 10b and 10a of shift register 10, respectively. After that, when the clock signal S1 is input, the decoder 12
8 terminals become "1" and "O" is applied to one input terminal of the NOR gate 34 via the inverter 33, so the logic with the clock signal S1 applied to the other input terminal of the NOR gate 34 is A clock signal Sla is applied to each clock terminal C of the D-type flip-flops 35, 36 whose D terminals are connected to bit positions 10b, 10a of the shift register 10, respectively. The contents of control bits X and Y stored in 10a are latched into each flip-flop 35 and 36. Therefore, the contents of X and Y are output from the Q terminals of flip-flops 35 and 36, respectively, and are used for control. It can be taken out as S3 & 1, S3a2 from the signal output terminals 37, 38. Furthermore, when the clock signal S1 is input and the 9 terminal of the decoder 12 becomes "1", the state of the Q output of the R-S flip-flop 13 changes. ``1'' is latched in the D-type flip-flop 14, and therefore the value ``1'' of its Q output is passed to the output terminal 32 through the gate 24, which is kept open by the signal from the 16 terminal of the decoder 12. The access signal S is output to the accessed circuit 9a in FIG.
4a.

When the clock signal S1 continues to be input, the 16 terminal of the decoder 12 becomes "1", the gate 24 is closed and the transmission of the access signal S4a is stopped, and the gate 2
3 is also closed to prohibit the clock signal S1 from being supplied to the clock terminal C of the binary counter 11. In the above,
The case where the contents of the address bits are the same as the code given to the terminals 27 to 31 has been explained, but if they are not the same, the output of the gate 21 becomes "1" during the comparison operation of these bits, and the R-S flip - Since the flop 13 is reset, the access signal S4a is not output from the terminal 32.

Further, as can be seen from the above explanation, the time point at which the access signal S4a is generated and the length of the period are different from each other in the D-type flip-flop.
The signal to be supplied to the clock terminal C of the flop 14 and the inhibit terminals of the gates 23 and 24 can be arbitrarily selected depending on which terminal of the decoder 12 is supplied.

According to the present invention, address word signals are serially multiplexed to form timing information, and control signals are further serially multiplexed to this multiplexed timing information and transmitted from the main circuit block to each slave circuit block. The number of wiring lines between the main circuit block and each subordinate circuit block can be significantly reduced, making it possible to reduce the size of the system and to increase the reliability of the system.

Furthermore, when adding a slave circuit block, according to the method of the present invention, it is only necessary to extend the bus line, so the addition can be done extremely easily.Furthermore, the main circuit block and the slave circuit block can be integrated into an integrated circuit. It has excellent effects such as being able to significantly reduce the number of connection pins.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2a to 2e are waveform diagrams of various parts in FIG. 1, and FIG.
FIG. 3 is a circuit diagram of the decoder circuit shown in the figure. 1...Digital complex system, 2...
・Address signal generation circuit, 3... Control signal generation circuit, 4... Main circuit block, 5a, 5b...
...Subordinate circuit block, 6, 8...Bus line, 7a, 7b...Decoder circuit, S1...
...Clock signal, S2...Address word signal, S3...Control signal, S4...
Address/control signals.

Claims (1)

[Scope of Claims] 1. A control signal transmission method for a digital complex system consisting of a main circuit block and at least one dependent circuit block controlled by the main circuit block, in which each of the dependent circuit blocks is transmitted from the main circuit block to each of the dependent circuit blocks. The transmission signal sent to is an address word signal consisting of a flag bit indicating the beginning of one word, an address bit into which an address code unique to each of the dependent circuit blocks is inserted, and a signal indicating the operation of each of the dependent circuit blocks. Composite multiplexing consists of control signals for performing control, and is serially multiplexed so that adjacent address word signals are placed apart by a predetermined period and the required control signal is placed within the predetermined period. The composite multiplexed signal is transmitted to all of the dependent circuit blocks via a bus line connecting the main circuit block and each of the dependent circuit blocks, and in each of the dependent circuit blocks, an address is sent to the decoder circuit. A detection circuit is provided, and the address detection circuit includes a counter that counts clock signals, a decoder that decodes the output of the counter, and a comparison circuit that compares the output of the decoder with a set self-address signal. ,
When the flag bit in the composite multiplexed signal is input, the counter is reset, and the output of the counter is subsequently decoded and compared by the decoder, and when it matches the set self address, the control bit is extracted. A control signal transmission method characterized in that a signal is sent to an accessed circuit to perform necessary control. 15