SU1443159A1 - Multichannel switching device - Google Patents

Abstract

The invention relates to electronic switching technology and can be used in automatic data collection systems. The purpose of the invention is to increase the reliability of information. The multi-channel switch contains information source 9 in each channel, key elements 10 and 11, synchronous D-flip-flop 12. In addition, the device includes a divider 2 frequencies, control unit 3, key element 4, current source 5, power bus 6-8, common and informational, device 13 of forming address, blocks 14-17 of m elements AND, blocks 20-24 of n elements AND, blocks 18 and 19 of m elements OR, block 25 of analog-to-digital converters, memories 26 and 27, register 28 addresses, triggers 29 and 30 Schmidt, elements And 31 and 32 and the counting trigger 33 with the account th input. The switch alternately connects the information consumer to one of the two storage devices 26 and 27, in which information is updated alternately in the presence of requests for information from the consumer and constantly in the absence of them. 1 il. (L

Description

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The invention relates to electronic switching technology and can be used in automatic data collection systems.

The aim of the invention is to increase the reliability of the read information by implementing in a multichannel switch alternately connecting the information consumer to one of the two RAMs of the multichannel switch, the information in which occurs alternately in the presence of requests and constantly in the absence of them.

The drawing shows a functional scheme of a multi-channel switch

The multi-channel switch contains 1 clock pulse generator, 2 frequency divider, control unit 3, the output of which is connected via key element 4 and current source 5 to power supply bus 6, common bus 7, information bus 8, in each channel information source 9, first and second the key elements 10 and 11 and the synchronous D-flip-flop 12, the device 13 forming the address, the first 14, the second 15, the third 16 and the fourth 17 blocks of m elements AND each, the first 18 and second 19 blocks of m elements OR each, the first 20, second 21, third 22 and fourth 23 blocks of n elements each, block 24, willow n of the OR elements, block 25 of analog-digital conversion (hereinafter referred to as ADC), first 26 and second 27 memories, address register 28, first 29 and second 30 Schmidt triggers, first 31 and second 32 And elements, counting a trigger 33, the clock generator 1 output is connected to the divider 2 frequency input, control unit 3, address generation device 13 and synchronization inputs of D-flip-flop 12 of each channel, second inputs of elements And blocks 14 and 16 are connected to. the corresponding outputs of the device 13 forming the address, the output s of the same elements And blocks 14 and 15 are connected respectively with the first and second inputs of the corresponding elements OR block 18, and the outputs of the same elements And blocks 16 and 17 are connected respectively with the first and second inputs of the corresponding elements OR block 19, the outputs of blocks 18 and 19 are connected to corresponding address inputs of memory devices 26

and 27, respectively, whose informational inputs are connected to the corresponding outputs of elements AND blocks 20 and 21, respectively, and informational outputs of memory devices 26 and 27 are connected to the second inputs of elements And respectively blocks 22 and 23, and the outputs of elements And blocks 22 and 23 are connected with the first and second inputs of the corresponding elements OR block 24, the outputs of which are connected to the information outputs of the data of the multichannel switch, the second inputs of the elements And blocks 20 and 21 are connected to the corresponding output The ADC block 25, whose input is connected to the information bus, is the input of the multichannel switch request connected to the input of the counting trigger 33 and the first inputs of the And 31 and 32 elements, the second inputs of which are connected respectively to the forward and inverse outputs of the trigger 33, and 32 are connected respectively to the inputs of the Schmidt flip-flops 29 and 30. The direct output of the trigger 29 is connected to the first inputs of the elements AND blocks 15 and 22 and the input Read storage device 26, and the inverse output of the trigger 29 is connected to the first inputs of the elements And block 14 and 20 and the input Record storage device 26, Direct output trigger 30 is connected to the first inputs of the elements And blocks 17 and 23 and the input Read storage device 27, and the inverse output of the trigger 30 is connected to the first inputs of elements And blocks 16 and 31 and the input . Record storage device 27. The output of the information source 9 in each channel through the first key element 10 is connected to the information bus 8, the first input of the information source 9 is connected to the common bus 7, and the second input through the second key element 11 is connected to the bus 6 nutrition The information input of the D-flip-flop 12 of the first channel is connected to the output of the splitter 2 frequency and the synchronization input of the device 13 to generate the address, the direct outputs of the D-flip-flops 12, except for the trigger 12 of the last channel, are connected to the information inputs of the D-flip-flops 12 of the subsequent channels and to the inputs key elements 10 and P respectively their channels.

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Multichannel switch works as follows.

After powering on, the multichannel switch is reset to its initial state, in which the D-flip-flops 12 synchronously on the direct outputs have a low voltage level, on the direct outputs of Schmidt triggers 29 and 30 with no signal received. Request from the information consumer and on all outputs Address generation devices 13 are also low voltage levels. In the absence of a signal, the Request, which is a high voltage level at all times necessary to access one of the storage devices 26 and 27, to the first inputs of the elements AND blocks 14 and 20 and the blocks 16 and 21 and the inputs Read storage devices 26 and 27 the inverse outputs of the respective triggers 29 and 30 are supplied with a high voltage level. The generator of 1 clock pulses forms a sequence of clock pulses with a period of T. The clock pulses are fed to the input of divider 2 frequencies, control block 3, inputs synchronize and D-trig- Gere 12, input device 13 forming address.

The frequency divider 2 extracts from the sequence of clock pulses every Nth pulse, which from its output goes to the information input of the D-flip-flop 12 of the first channel and sets a high voltage level at its output that opens the key elements 10 and 11 of this channel. As a result, the source 9 of the first channel information is connected respectively to the power bus 6 and the information bus 8.

Moreover, all the key elements 10 and 11 of the remaining channels are locked, and other sources of information 9 are not polled.

When the next clock pulse arrives at the clock inputs of the D-flip-flops 12, the D-flip-flop 12 of the second channel switches, and the voltage established at its output opens the corresponding key elements 10 and 11 and connects the information source 9 of the second channel to the information bus 8.

After the last channel information source 9 is polled, de59

The frequency clock 2 generates a new trigger pulse for the D-flip-flop 12 of the first channel, and the process repeats. The sequence of clock pulses produced by the generator of 1 clock pulses arrives at the control unit 3, which forms a sequence of pulses of duration t, and a repetition period T, which comes through an additional key element 4 to the current source 5, which turns on the channels only for the time t polled. In the pause (T-t) current source 5 is disconnected from all channels.

The address generation device 13 is a binary pulse counter, where m loggN with outputs for each code bit. The incremental value of the counter code, incremented by one, corresponds to the channel number of the multichannel switch connected to the information bus 8 at a given time. The counter is reset by applying to the synchronization input of the device 13 for generating addresses from the output of the splitter 2 frequency.

Information from sources 9 of information from the information bus 8 is fed to the input of the ADC block 25. The time of the analog-digital conversion unit 25 ADC t; T (T is the period of the following clock pulses). From the output of block 25 ADC information in a parallel n-bit code. Through the elements And blocks 20 and 21 of the n elements And delivers information inputs of the storage devices 26 and 27. The address of the source 9 information from the output of the device 13 forming the address through the blocks 14 and 16 of the m elements And and the blocks 18 and 19 of the m elements of the NL is fed to the address inputs of the storage devices 26 and 27.

Free access of the information consumer to the information source 9 is provided by providing the consumer free access to the information recorded in the storage devices 26 and 27. To obtain the necessary information, the information consumer records the address of the desired channel (the address of the memory cell in the storage devices 26 and 27). in the address register 29, forms a signal Request and delivers it to the input

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counting trigger 33 and the first inputs of the And 31 and 32 elements, And the 31 and 32 elements alternately switch the signal. The request for the inputs of Schmidt triggers 29 and 30, respectively. For example, all odd requests are sent to the input of the Schmidt trigger 29, and the even ones - trigger 30. Let the first request enter the input of trigger 29. Then, on the inverse output of trigger 29 and, respectively, on the first inputs of elements AND blocks 4 and 20, input Record storage device 26 sets a low voltage level, as a result the address of the channel that is not being scanned Audited through blocks 4 and 18 to the address inputs of the storage device 26, the information code from the output of the ADC block 25 does not flow through the block 20 to the information inputs of the storage device 26-, from the direct output of the trigger 29 a high voltage level is applied to the first | the inputs of elements I of block 15, block 22 and to the input of Read memory 26, permitting information from the memory cell of memory 26 to be read at the address received from address register 28 through blocks 15 and 8 to the address inputs of memory 26. Information with memorize The device 26 through the blocks 22 and 24 enters the information outputs of the multichannel switch.

After the removal of the signal, the Request at the input of the trigger 29 is set low, the voltage level is set, and the process of recording the information of the sources 9 information into the storage device 26 is resumed. In the process of reading information from the storage device 26, the update of the information in the storage device 27 is not interrupted. When the next request (in this example, the second one) is received, the trigger 33 changes its state, and a low voltage level is established at the forward output, a high voltage level at the inverse output, the Request signal is received through an open element 32 at the trigger input ra 30. This makes it possible to access information recorded in memory 27,

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Claims (1)

Invention Formula A multichannel switch containing a clock pulse generator, a frequency divider, a control unit whose output is connected via a key element and a current source to the power bus, a common bus, an information bus, an address generation device, the first and second blocks of ha elements And each, the first block of tons of OR elements, analog-to-digital conversion unit, first block of n And elements, first storage device, first Schmidt trigger, address register, in each channel the source of information, first and second key elements A synchronous D-trigger; the source information output on each channel is connected to the information bus through the first key element; Hej, the first information source input is connected to the common bus, and the second input is connected to the power bus through the second key element, the D-trigger information input of the first channel is connected with the output of the frequency divider, the outputs of the D-flip-flops, in addition to the D-flip-flop of the last channel, are connected to the infor- mation HHObbn-iH inputs of the D-flip-flop of subsequent channels and the control inputs of the first and second key elements of their channels, the first inputs of elements AND of the first block of n elements I, of the first block of m elements I and input The recording of the first memory device is connected to the inverse output of the first Schmidt trigger, the direct output of which is connected to the input Reading the first memory device and to the first inputs of the elements And second a block of m elements And, the second inputs of the elements And the second block of m elements And connected to the corresponding outputs of the address register, the inputs of which are connected to the address inputs of the switch, the output of the pulse generator not with the inputs of the frequency divider, control unit, counting input of the address shaping device and the D-flip-flop synchronization inputs of each channel, the R input of the address shaping device is connected to the output of the frequency divider, the second inputs of the AND block of the first block of m elements AND devices - address shaping devices, outputs 714 the elements of the same name And the first and second blocks of m elements And are connected respectively with the first and second inputs of the corresponding ele. OR of a block of m elements OR the outputs of the second connection with the corresponding address inputs of the first storage device, the information inputs of which are connected to the corresponding outputs of the elements AND of the first block of n And elements, the second inputs of And elements of the first block of n And elements are connected to the outputs of the analog block digital conversion, the input of which is connected to the information bus, is the third and fourth blocks of m ale, in order to increase the reliability of the detected information ntov AND each, second third, fourth blocks of n elements AND each, second block of m elements OR, block of n elements OR, first, second elements AND, second storing device, second Schmidt trigger, counting trigger, input Record of the second memory device, the first inputs of the elements And the third block of m elements And the second block of n elements And connected to the inverse output of the second Schmidt trigger, the direct output of which is connected to the input Reading the second memory device, to the first inputs of the elements And the fourth block of n AND gates and the fourth block of n AND gates, the second inputs of AND gates whose outputs are connected to so.otvetstvuyuschimi register address outputs and fourth elements from m elements §loka and connected to respective second inputs of element Q 5 0 5 0 five 0 59 " OR of the second block of m elements OR, the outputs of which are connected to the corresponding address inputs of the second storage device, and the first inputs of the OR elements of the second block of m elements OR are connected to the corresponding outputs of the AND blocks of the third block from the I elements, the second inputs of the AND elements connected to the corresponding outputs of the device forming the address, the first inputs of the elements And the third block of m elements And connected to the direct output of the first Schmidt trigger, the second inputs of the elements And the second block And from the n elements And connected to the corresponding outputs of the analog-digital conversion unit, and the outputs of the elements And the second block of the n elements And connected to the corresponding information inputs of the second storage device, information outputs of the first and second storage devices connected to the second inputs of the corresponding elements And, respectively the third and fourth blocks of n elements And, the outputs of the elements And which are connected respectively with the first and second inputs of the corresponding elements OR block and of the OR elements, the outputs of which are connected to the information outputs of the multichannel switch data, the input request of the multichannel switch is connected to the input of the counting trigger and the first inputs of the first and second elements AND, the second inputs of which are connected respectively to the forward and inverse outputs of the counting trigger, and the outputs the first and second elements And are connected respectively with the inputs of the first and second Schmidt triggers.