KR20000042870A - Forming method of trench of semiconductor device - Google Patents
Forming method of trench of semiconductor device Download PDFInfo
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- KR20000042870A KR20000042870A KR1019980059162A KR19980059162A KR20000042870A KR 20000042870 A KR20000042870 A KR 20000042870A KR 1019980059162 A KR1019980059162 A KR 1019980059162A KR 19980059162 A KR19980059162 A KR 19980059162A KR 20000042870 A KR20000042870 A KR 20000042870A
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- pad
- trench
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 35
- 239000010703 silicon Substances 0.000 claims abstract description 35
- 125000006850 spacer group Chemical group 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract 2
- 150000004767 nitrides Chemical class 0.000 claims description 44
- 230000004888 barrier function Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract 10
- 238000007254 oxidation reaction Methods 0.000 abstract 10
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 트렌치 형성 방법에 관한 것으로서, 보다 구체적으로는 질화막 스페이서를 이용해서 트렌치를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming trenches in semiconductor devices, and more particularly, to a method of forming trenches using nitride film spacers.
반도체 기술의 진보와 더불어 더 나아가서는 반도체 소자의 고속화, 고집적화가 진행되고 있고, 이에 수반해서 패턴에 대한 미세화의 필요성이 점점 높아지고 있으며, 패턴의 칫수도 고정밀화가 요구되고 있다. 이는 반도체 소자에 있어서, 넓은 영역을 차지하는 소자 분리 영역에도 적용된다.In addition to the advances in semiconductor technology, high speed and high integration of semiconductor devices is progressing, and along with this, the necessity of miniaturization of patterns is increasing, and the size of patterns is also required to be highly accurate. This also applies to device isolation regions that occupy a wide area in semiconductor devices.
따라서, 종래에는 토폴로지가 높고, 넓은 면적을 차지하는 로코스(LOCOS) 기술에 의한 필드 산화막 대신 미세한 크기의 트랜치 구조의 소자 분리막이 제안된다.Accordingly, a device isolation film having a trench structure having a fine size is proposed instead of a field oxide film by LOCOS technology having a high topology and occupying a large area.
이러한 미세한 크기를 갖는 트랜치 구조의 소자 분리막으로는, 얕은 깊이를 갖는 트랜치 아이솔레이션(이하, STI:shallow trench isolation) 기술이 있는데, 이 기술은 얕은 깊이로 트랜치를 형성하므로서, 기판 식각시, 기판에 형성되는 스트레스를 줄일 수 있다.A trench isolation device having a shallow depth (hereinafter, referred to as a shallow trench isolation (STI)) technique is a trench isolation device having a shallow depth, which forms a trench at a shallow depth, thereby forming a substrate at the time of etching the substrate. Can reduce stress
기존의 트렌치 형성 방법은 다음과 같다. 실리콘 기판상에 산화막을 형성하고, 산화막상에 질화막을 증착한다. 질화막상에 포토레지스트를 도포하고, 소정의 마스크를 이용한 식각을 실시해서 포토레지스트를 패터닝한다. 패터닝된 포토레지스트를 마스크로 하여 질화막과 산화막 및 실리콘 기판 일부분을 식각하여, 트렌치를 형성한다.The conventional trench formation method is as follows. An oxide film is formed on a silicon substrate, and a nitride film is deposited on the oxide film. A photoresist is applied onto the nitride film, followed by etching using a predetermined mask to pattern the photoresist. Using the patterned photoresist as a mask, a portion of the nitride film, the oxide film and the silicon substrate is etched to form a trench.
그런데, 상기된 기존의 트렌치 형성 방법에서, 트렌치 형성을 위한 식각시, 트렌치의 상단폭보다 하단폭이 넓어져서, 이후에 트렌치에 매립되는 소자 분리막인 산화막에 보이드가 형성될 우려가 있다.However, in the conventional trench forming method described above, when the trench is formed for etching, the lower width is wider than the upper width of the trench, so that voids may be formed in the oxide film, which is an isolation layer embedded in the trench.
이를 방지하기 위해, 종래에는 질화막만을 먼저 식각하여 실리콘 기판을 노출시킨 후, 노출된 질화막의 양측벽에 미리 산화막 스페이서를 형성하여, 산화막 스페이서가 식각 장벽으로 하여 실리콘 기판을 식각하므로써, 트렌치가 상부에서 하부로 가면서 점진적으로 폭이 줄어드는 형상을 갖도록 하였다.In order to prevent this, conventionally, only the nitride film is etched first to expose the silicon substrate, and then oxide spacers are formed on both sidewalls of the exposed nitride film in advance, thereby etching the silicon substrate with the oxide spacer as an etch barrier, so that the trench is The width was gradually reduced to the lower portion.
그런데, 산화막 스페이서를 사용하면 트렌치의 형상을 상기된 형상대로 형성할 수는 있지만, 산화막 스페이서 형성을 위한 산화막 증착 공정에서, 노출된 실리콘 기판 표면이 산화되어, 필요한 액티브 영역 확보가 어려워지는 문제점이 있었다.By the way, when the oxide spacer is used, the trench can be formed in the shape described above. However, in the oxide deposition process for forming the oxide spacer, the exposed silicon substrate surface is oxidized, which makes it difficult to secure necessary active regions. .
따라서, 본 발명은 종래의 트렌치 형성 방법이 안고 있는 문제점을 해소하기 위해 안출된 것으로서, 산화막 스페이서 형성을 위한 산화막 증착시, 실리콘 기판의 액티브 영역이 산화되지 않도록 할 수 있는 반도체 소자의 트렌치 형성 방법을 제공하는데 목적이 있다.Accordingly, the present invention has been made to solve the problems of the conventional trench forming method, and a trench forming method of a semiconductor device capable of preventing the active region of the silicon substrate from being oxidized during the deposition of an oxide film for forming an oxide spacer. The purpose is to provide.
도 1 내지 도 6은 본 발명에 따른 트렌치 형성 방법을 순차적으로 나타낸 도면1 to 6 are views sequentially showing a trench forming method according to the present invention
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
1 ; 실리콘 기판 2 ; 패드 산화막One ; Silicon substrate 2; Pad oxide
3 ; 패드 질화막 4 ; 산화막3; Pad nitride film 4; Oxide film
5 ; 포토레지스트 6 ; 질화막5; Photoresist 6; Nitride film
7 ; 질화막 스페이서 8 ; 산화막 스페이서7; Nitride film spacers 8; Oxide spacer
9 ; 트렌치9; Trench
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 트렌치 형성 방법은 다음과 같다.In order to achieve the above object of the present invention, the trench forming method according to the present invention is as follows.
실리콘 기판상에 패드 산화막과 패드 질화막 및 산화막을 순차적으로 형성한다. 산화막상에 포토레지스트를 도포하고, 포토레지스틀 노광 공정을 통해 패터닝한다. 패터닝된 포토레지스트를 식각 마스크로 산화막과 패드 질화막을 식각하여, 실리콘 기판에 형성될 트렌치 상부에 있는 패드 산화막을 노출시킨 후, 포토레지스트를 제거한다. 전체 구조 상부에 질화막을 균일한 두께로 증착하고 질화막을 식각하면, 패드 질화막의 양측벽에 질화막 스페이서가 형성된다. 양측 질화막 스페이서 사이간 폭이 액티브 영역이 된다. 다시, 전체 구조 상부에 산화막을 균일한 두께로 증착하고, 산화막과 패드 산화막을 식각하면, 질화막 스페이서에 산화막 스페이서가 형성됨과 아울러 트렌치가 형성될 실리콘 기판이 노출된다. 산화막 스페이서를 식각 장벽으로 하여 실리콘 기판 일부를 식각하여 트렌치를 형성한다. 산화막 스페이서와 그 하부의 패드 산화막을 습식 식각하고, 단차진 상태로 노출된 실리콘 기판의 양측 표면을 미소 식각하여 탑 라운딩(top rounding) 형상으로 형성한다.A pad oxide film, a pad nitride film, and an oxide film are sequentially formed on the silicon substrate. A photoresist is applied onto the oxide film and patterned through a photoresist exposure process. The oxide film and the pad nitride film are etched using the patterned photoresist as an etching mask to expose the pad oxide film on the trench to be formed on the silicon substrate, and then the photoresist is removed. When a nitride film is deposited to a uniform thickness over the entire structure and the nitride film is etched, nitride film spacers are formed on both side walls of the pad nitride film. The width between both nitride film spacers becomes an active region. When the oxide film is deposited on the entire structure with a uniform thickness and the oxide film and the pad oxide film are etched, the oxide spacer is formed on the nitride spacer and the silicon substrate on which the trench is to be exposed is exposed. A portion of the silicon substrate is etched using the oxide spacer as an etch barrier to form a trench. The oxide spacer and the pad oxide layer under the wet layer are wet-etched, and both surfaces of the silicon substrate exposed in the stepped state are micro-etched to form a top rounding shape.
상기된 본 발명의 구성에 의하면, 산화막 증착 전의 공정에서, 패드 질화막만을 식각하고 패드 산화막은 식각하지 않으므로써, 액티브 영역의 실리콘 기판이 노출되지 않게 된다. 따라서, 산화막 스페이서 형성을 위한 산화막 증착시, 액티브 영역의 실리콘 기판이 산화되어, 액티브 영역 확보가 어려워지는 것이 방지된다.According to the configuration of the present invention described above, in the step before the oxide film deposition, only the pad nitride film is etched and the pad oxide film is not etched so that the silicon substrate in the active region is not exposed. Therefore, during the deposition of the oxide film for forming the oxide film spacer, the silicon substrate in the active region is oxidized, thereby making it difficult to secure the active region.
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 6은 본 발명에 따른 트렌치 형성 방법을 순차적으로 나타낸 도면이다.1 to 6 are views sequentially showing a trench forming method according to the present invention.
먼저, 도 1에 도시된 바와 같이, 실리콘 기판(1)상에 패드 산화막(2)과 패드 질화막(3)을 순차적으로 증착한다. 이때, 트렌치 형성을 위한 후속 식각 공정에서 질화막(3)도 어느 정도 식각되는 것을 감안하여, 질화막(3)은 1,500 내지 2,500Å 정도의 두께로 두껍한다. 또는, 질화막(3)을 300 내지 1,000Å 정도의 두께로만 형성하고, 질화막(3) 상부에 도 1과 같이 산화막(4)을 증착할 수도 있다. 이어서, 산화막(4)상에 포토레지스트(5)를 도포하고, 노광 공정을 통해 포토레지스트(5)를 패터닝한다.First, as shown in FIG. 1, the pad oxide film 2 and the pad nitride film 3 are sequentially deposited on the silicon substrate 1. At this time, in view of the fact that the nitride film 3 is also etched to some extent in the subsequent etching process for forming the trench, the nitride film 3 is thick with a thickness of about 1,500 to 2,500 kPa. Alternatively, the nitride film 3 may be formed to have a thickness of about 300 to 1,000 GPa, and the oxide film 4 may be deposited on the nitride film 3 as shown in FIG. 1. Next, the photoresist 5 is applied onto the oxide film 4, and the photoresist 5 is patterned through an exposure process.
그런 다음, 패터닝된 포토레지스트(5)를 식각 마스크로 하여, 패드 산화막(2)이 노출되도록 산화막(4)과 패드 질화막(3)을 식각한 후, 포토레지스트(5)를 제거한다. 이어서, 전체 구조 상부에 질화막(6)을 도 2와 같이 균일한 두께로 증착한다.Then, using the patterned photoresist 5 as an etching mask, the oxide film 4 and the pad nitride film 3 are etched to expose the pad oxide film 2, and then the photoresist 5 is removed. Subsequently, a nitride film 6 is deposited on the entire structure with a uniform thickness as shown in FIG. 2.
그리고, 질화막(6)을 습식 식각하여 패드 질화막(3)의 양측벽에만 질화막(6)이 남도록 하므로써, 도 3에 도시된 바와 같이 패드 질화막(3)의 양측벽에 질화막 스페이서(7)를 형성한다. 양측 질화막 스페이서(7) 사이 부분이 트렌치가 형성될 액티브 영역의 폭이 된다. 즉, 질화막(6)을 증착하는 두께에 따라 액티브 영역의 폭이 결정된다.Then, the nitride film 6 is wet-etched so that the nitride film 6 remains only on both side walls of the pad nitride film 3, thereby forming nitride film spacers 7 on both side walls of the pad nitride film 3, as shown in FIG. do. The portion between the two nitride film spacers 7 becomes the width of the active region where the trench is to be formed. That is, the width of the active region is determined by the thickness of depositing the nitride film 6.
이어서, 전체 구조 상부에 산화막을 증착한다. 이때, 종래에는 실리콘 기판(1)이 선행 공정에서 노출되었지만, 본 발명에서는 실리콘 기판(1)은 노출되지 않고 패드 산화막(2)만이 노출된 상태이다. 따라서, 산화막 증착시, 실리콘 기판(1)이 산화되는 것이 방지된다. 증착된 산화막을 질화막과 마찬가지로 습식 식각하여, 도 4에 도시된 바와 같이, 질화막 스페이서(7)의 내측면에 산화막 스페이서(8)가 형성된다. 이때, 노출된 패드 산화막(2)도 같이 식각되어 제거되므로써, 트렌치가 형성될 실리콘 기판(1)의 액티브 영역이 노출된다.Subsequently, an oxide film is deposited on the entire structure. At this time, the silicon substrate 1 is conventionally exposed in the preceding process, but in the present invention, the silicon substrate 1 is not exposed and only the pad oxide film 2 is exposed. Therefore, during the oxide film deposition, the silicon substrate 1 is prevented from being oxidized. The deposited oxide film is wet-etched in the same manner as the nitride film to form an oxide film spacer 8 on the inner surface of the nitride film spacer 7 as shown in FIG. 4. At this time, the exposed pad oxide film 2 is also etched and removed to expose the active region of the silicon substrate 1 on which the trench is to be formed.
그런 다음, 산화막 스페이서(8)를 식각 장벽으로 하여 노출된 실리콘 기판(1)을 식각하면, 도 5와 같이 실리콘 기판(1)에 하부로 갈수록 폭이 줄어드는 형상의 트렌치(9)가 형성된다.Then, when the exposed silicon substrate 1 is etched using the oxide spacer 8 as an etch barrier, a trench 9 having a shape that decreases in width toward the bottom thereof is formed in the silicon substrate 1 as shown in FIG. 5.
마지막으로, 도 6에 도시된 바와 같이, 산화막 스페이서(8)를 습식 식각하여 제거함과 동시에 산화막 스페이서(8) 하부에 있는 패드 산화막(2) 부분도 제거한다. 따라서, 패드 산화막(2) 하부에 있는 실리콘 기판(1) 부분이 노출된다. 그런데, 노출된 실리콘 기판(1) 부분은 트렌치(9)와 직각으로 단차진 형상이므로, 노출된 실리콘 기판(1)의 내측 모서리 부분을 미소 식각하여, 내측으로 완만한 형상을 갖는 탑 라운딩 형상으로 형성한다. 이때의 식각 가스로 SF6, CHF3, 또는 CF4등의 플루오린계의 가스가 사용될 수 있다.Finally, as shown in FIG. 6, the oxide spacer 8 is removed by wet etching, and at the same time, a portion of the pad oxide layer 2 under the oxide spacer 8 is also removed. Thus, the portion of the silicon substrate 1 under the pad oxide film 2 is exposed. However, since the exposed silicon substrate 1 portion has a stepped shape at right angles to the trench 9, the inner edge portion of the exposed silicon substrate 1 is etched into a top rounded shape having a gentle inward shape. Form. At this time, a fluorine-based gas such as SF 6 , CHF 3 , or CF 4 may be used as the etching gas.
이상에서 자세히 설명된 바와 같이 본 발명에 의하면, 패드 질화막만을 식각하고 패드 산화막을 식각하지 않음과 아울러 질화막 스페이서로 미리 액티브 영역을 확보한 상태에서 산화막 스페이서를 형성하게 되므로써, 산화막 스페이서 형성을 위한 산화막 증착시 실리콘 기판의 액티브 영역이 산화되는 것이 방지되고, 액티브 영역의 폭을 확실하게 확보할 수가 있게 된다.As described in detail above, according to the present invention, since the oxide layer spacer is formed by etching only the pad nitride layer, not etching the pad oxide layer, and forming an active region with the nitride spacer in advance, the oxide layer is deposited for forming the oxide spacer. The active area of the silicon substrate is prevented from being oxidized, and the width of the active area can be securely ensured.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100481557B1 (en) * | 2002-09-07 | 2005-04-07 | 동부아남반도체 주식회사 | Method for making narrow sti by using double nitride etch |
| KR100772709B1 (en) * | 2005-12-13 | 2007-11-02 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device with isolation |
| KR100829375B1 (en) * | 2002-12-24 | 2008-05-13 | 동부일렉트로닉스 주식회사 | Formation method of trench in semiconductor device |
| KR100942077B1 (en) * | 2003-05-23 | 2010-02-12 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR100972693B1 (en) * | 2003-06-25 | 2010-07-27 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100402392B1 (en) * | 2001-11-06 | 2003-10-17 | 삼성전자주식회사 | Semiconductor device having trench isolation structure and method of fabricating the same |
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1998
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100481557B1 (en) * | 2002-09-07 | 2005-04-07 | 동부아남반도체 주식회사 | Method for making narrow sti by using double nitride etch |
| KR100829375B1 (en) * | 2002-12-24 | 2008-05-13 | 동부일렉트로닉스 주식회사 | Formation method of trench in semiconductor device |
| KR100942077B1 (en) * | 2003-05-23 | 2010-02-12 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR100972693B1 (en) * | 2003-06-25 | 2010-07-27 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
| KR100772709B1 (en) * | 2005-12-13 | 2007-11-02 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device with isolation |
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