KR19980030446A - Semiconductor substrate and formation method thereof - Google Patents

Abstract

The present invention relates to an SOI substrate and a method of forming the same, wherein the present invention provides a growth barrier layer on a semiconductor substrate, and patterning the growth barrier layer so as to exist only above the cell region where the device is to be formed. After selective epitaxial growth, a step is formed so that the cell region is artificially lower than the peripheral circuit region before the integrated circuit is formed by removing the growth stop layer, and thereafter, after the integrated circuit is formed, between the cell region and the peripheral circuit region It can reduce the surface step.

Description

Semiconductor substrate and formation method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method of forming the same, and more particularly, to a semiconductor substrate and a method of forming the semiconductor substrate capable of reducing a step difference between a cell region and a peripheral region of a device when forming a silicon on insulator (SOI) substrate.

In general, a semiconductor device is composed of a cell region in which a main circuit pattern is formed and a peripheral region in which a peripheral circuit is formed. Accordingly, semiconductor circuits are highly integrated in the cell region, and peripheral circuits are formed in the peripheral region at a wider interval than the cell region.

However, conventionally, integrated circuits are integrated at very high density in the cell region, while circuit patterns are formed at relatively wide intervals in the peripheral region. Thus, when the completed semiconductor device is constructed on the same plane, the cell region is in the peripheral region. Compared with the higher step.

Thus, in order to impart an artificial step to the semiconductor substrate, a thin film oxide film 2, for example, a thermal oxide film is deposited on the semiconductor substrate 1, as shown in FIG. The nitride film 3 is deposited to a predetermined thickness. Then, a resist film is applied over the entire structure, and the resist pattern 4 is formed by exposing and developing the silicon nitride film 3 on the cell region to be exposed. Thereafter, as shown in FIG. 1B, the silicon nitride film 3 and the oxide film 2 are patterned using the resist pattern 4, and the resist pattern 4 is removed by a known method.

Subsequently, as shown in FIG. 1C, the exposed semiconductor substrate 1 is oxidized using the patterned silicon nitride film 3 as a mask to form a field oxide film 5.

Thereafter, as shown in FIG. 1D, the silicon nitride film 3, the oxide film 2 and the field oxide film 5 are removed by wet or dry etching. Then, during the oxidation process for forming the field oxide film, since the silicon substrate is oxidized by a predetermined depth, when the field oxide film is removed, the silicon substrate is recessed by a predetermined depth (indicated by H in the figure), for example, about 0.5 to 2.0 μm. . Therefore, an artificial step is formed in the semiconductor substrate before the device is formed, thereby reducing the step between the cell region C and the peripheral region F in the subsequent device formation process.

However, according to the conventional method as described above, a method of artificially giving a semiconductor step by forming and removing a field oxide film is possible in a general silicon substrate, but it is possible to realize a low voltage, low power, and a simple manufacturing process. A silicon on insulator (SOI) substrate, which is a circuit board, has had many difficulties in forming an artificial step.

Accordingly, the present invention has been made to solve the above-mentioned problems, and provides a semiconductor substrate and a method of forming the same, which minimizes the step difference between the device formed in the cell region of the SOI substrate and the peripheral region, thereby reducing the step level. For the purpose of

1A to 1D are views for explaining a conventional method for forming a semiconductor substrate.

2A to 2D are views for explaining a method for forming a semiconductor substrate of the present invention.

* Explanation of symbols for main parts of the drawings

11 silicon substrate 12 insulating film

13: SOI layer 14: growth stop film

15: resist pattern 16: epitaxial growth layer

100: SOI substrate

In order to achieve the above object of the present invention, the semiconductor substrate of the present invention is a semiconductor substrate having a cell region in which a semiconductor element is formed and a peripheral circuit region, wherein the selective epitaxial growth layer is formed on the peripheral circuit region. , Its surface is formed to be higher than the cell region in which the element is formed.

In addition, the method of forming a semiconductor substrate according to the present invention comprises the steps of: forming a growth stop layer on the semiconductor substrate, patterning the growth stop layer to be present only in the upper cell region where the device is to be formed, and the portion where the growth stop layer is not formed Selective epitaxial growth, and removing the growth barrier.

According to the present invention, by using the selective epitaxial growth method on the SOI substrate, a step is formed so that the cell region is artificially lower than the peripheral circuit region before the integrated circuit is formed, and then after the integrated circuit is formed, the cell region And the surface step between the peripheral circuit area can be reduced.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are diagrams for describing a method of forming a semiconductor substrate of the present invention.

First, an SOI substrate 100 composed of a silicon substrate 11, an insulating film 12, and an SOI layer 13 is provided. An oxide film 14 for protecting the SOI layer 13 is deposited on the SOI substrate 100 in a thickness of 1000 to 2000 kPa by a low pressure chemical vapor deposition (LPCVD) method. Subsequently, in order to minimize the step difference between the peripheral circuit region P and the cell region C, a resist pattern 15 is formed on the oxide layer 14 so that the peripheral circuit region P is exposed.

Thereafter, as shown in Fig. 2B, by using the resist pattern 15, the oxide film 14 is patterned to exist only in the cell region C, and the resist pattern 15 is removed by a known removal method. Then, using the patterned oxide pattern 14 as an epitaxial stop mask, the SOI layer 13 of the exposed peripheral circuit region P is selectively epitaxially grown. Here, the height A of the epitaxially grown layer 16 is approximately 1.5 to 2.0 μm, and the height A is a height in consideration of partial etching during the subsequent process.

On the other hand, in the process of forming the epitaxially grown layer 16, the epitaxially grown layer 16 is penetrated and grown toward the oxide film 14, as indicated by the dotted line in FIG. 2B, so that an artificial step of the SOI substrate 100 is generated. In the process, it has a non-smooth surface.

Thus, in order to form the epitaxially grown layer 16 having a smooth surface, the epitaxially grown layer 16 is blanket etched about 0.3 to 0.5 mu m. Then, as shown in FIG. 2C, the epitaxially grown layer 16 has a smooth curved end surface.

Thereafter, as shown in FIG. 2D, the oxide film 14 is removed by a known removal method, and the SOI substrate 100 having an artificial step of the inclined surface 16A is completed. At this time, the step D becomes about 1.0 to 1.7 μm, and when the element is formed in the cell region C later, it has a height similar to that of the peripheral circuit region P. FIG.

As described in detail above, according to the present invention, by using the selective epitaxial growth method on the SOI substrate, the step is formed so that the cell region is artificially lower than the peripheral circuit region before the integrated circuit is formed, and subsequently integrated. After the circuit is formed, the surface level difference between the cell region and the peripheral circuit region can be reduced.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (10)

A semiconductor substrate having a cell region in which a semiconductor element is formed and a peripheral circuit region, wherein a selective epitaxial growth layer is formed on the peripheral circuit region, and the surface thereof is formed to be higher than the cell region in which the element is formed. Board. The semiconductor substrate of claim 1, wherein the selective epitaxial growth layer has a height of 1.0 to 1.7 μm. The semiconductor substrate of claim 1, wherein both ends of the selective epitaxial growth layer are streamlined. Forming a growth stop layer on the semiconductor substrate, patterning the growth stop layer so as to exist only above the cell region where the device is to be formed, selectively epitaxially growing a portion where the growth stop layer is not formed, and removing the growth stop layer A semiconductor substrate forming method comprising the step of. The method of claim 4, wherein the semiconductor substrate is an SOI substrate comprising a silicon substrate, an insulating film, and an SOI layer. The method of forming a semiconductor substrate according to claim 4 or 5, wherein the growth preventing film is an oxide film. The method of forming a semiconductor substrate according to claim 6, wherein the growth stopper film has a thickness of 1000 to 2000 GPa. The semiconductor according to claim 4 or 5, wherein in the step of selectively epitaxially growing the portion where the growth stop layer is not formed, the portion where the growth stop layer is not formed is grown to about 1.5 to 2.0 mu m in height. Formation method of a substrate. 6. The method of claim 4 or 5, further comprising blanket etching the selective epitaxial layer for a smooth surface between the selective epitaxial growth and forming the growth barrier. A method of forming a semiconductor substrate. The method of claim 9, wherein in the blanket etching step, the selective epitaxial layer is etched by about 0.3 μm to about 0.5 μm.