KR100297098B1 - Method for forming field oxide layer of semiconductor device - Google Patents
Method for forming field oxide layer of semiconductor device Download PDFInfo
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- KR100297098B1 KR100297098B1 KR1019940016105A KR19940016105A KR100297098B1 KR 100297098 B1 KR100297098 B1 KR 100297098B1 KR 1019940016105 A KR1019940016105 A KR 1019940016105A KR 19940016105 A KR19940016105 A KR 19940016105A KR 100297098 B1 KR100297098 B1 KR 100297098B1
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims abstract description 39
- 230000003647 oxidation Effects 0.000 claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 210000003323 beak Anatomy 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
본 발명은 반도체 소자의 필드 산화막(Field oxide) 형성 방법에 관한 것으로, 특히 실리콘 기판의 필드 영역(Field region)에 예비 필드 산화막을 형성시킨후 식각하여 리세스(Recess) 구조를 형성시기고 노출되는 질화막 및 패드 산화막측벽에 캐핑(Capping) 질화막을 형성시킨 후 최종 필드 산화막을 형성시키므로써 필드 산화막 양측에 형성되는 버즈비크(Bird's beak)의 크기를 감소시켜 넓은 활성영역(Active region)을 확보할 수 있도록 한 반도체 소자의 필드 산화막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a field oxide of a semiconductor device. In particular, a preliminary field oxide film is formed in a field region of a silicon substrate and then etched to form a recess structure. By forming a capping nitride film on the nitride and pad oxide side walls, and forming a final field oxide film, the size of the bird's beak formed on both sides of the field oxide film can be reduced to secure a wide active region. A method of forming a field oxide film of a semiconductor device is provided.
일반적으로 반도체 소자의 제조공정에서 소자와 소자사이를 분리시키기 위하여 소자 분리막 즉, 필드 산화막을 형성시키는데, LOCOS(Local oxidation of silicon) 기술에 의해 형성된 필드 산화막의 양측에는 버즈비크가 형성된다. 그러면 종래 반도체 소자의 필드 산화막 형성방법을 제 1a 및 제 1b 도를 통해 설명하면 다음과 같다.In general, a device isolation film, that is, a field oxide film, is formed to separate the device from the device in the manufacturing process of the semiconductor device. Buzzbeek is formed on both sides of the field oxide film formed by LOCOS (Local oxidation of silicon) technology. A method of forming a field oxide film of a conventional semiconductor device will now be described with reference to FIGS. 1A and 1B.
종래 반도체 소자의 필드 산화막 형성 방법은 제 1a 도에 도시된 바와 같이 실리콘 기판(1) 상에 패드 산화막(2) 및 질화막(3)을 순차적으로 형성시킨 후 마스크(Mask)를 사용하여 사진 및 식각공정에 의해 상기 질화막(3)을 패터닝한 상태에서 산화(Oxidation)공정을 실시하여 제 1B 도와 같은 필드 산화막(9)을 형성시키는데, 이 필드산화막(9)의 양측에는 상기 산화 공정시 산화제가 상기 패드 산화막(2)을 따라 측면 확산되어 A 부분과 같은 버즈비크가 형성되며, 이 버즈비크는 활성영역쪽으로 형성되어 활성영역의 크기를 감소시킨다. 더욱이 반도체 소자의 고집적화에 따라 활성 영역사이의 거리가 좁아지기 때문에 실리콘 기판 내부로 성장되는 필드 산화막의 양 측, 체적비(Volume ratio)가 많아야 소자분리 역할을 충실히 할수 있는데, 종래의 LOCOS 방법으로는 상기 체적비를 증가시키는데 한계가 있고, 필드 산화막의 평탄화가 어렵다.In the method of forming a field oxide film of a conventional semiconductor device, as illustrated in FIG. 1A, a pad oxide film 2 and a nitride film 3 are sequentially formed on a silicon substrate 1, and then a photo and etching are performed using a mask. An oxidation process is performed in the state where the nitride film 3 is patterned by the process to form a field oxide film 9 as shown in FIG. 1B. On both sides of the field oxide film 9, an oxidant is formed during the oxidation process. Side-diffusion is performed along the pad oxide film 2 to form a burj beak like the A portion, which is formed toward the active area to reduce the size of the active area. In addition, the distance between the active regions is narrowed due to the high integration of semiconductor devices, so that both sides and volume ratios of the field oxide film grown inside the silicon substrate must be large to faithfully serve as device isolation. There is a limit to increasing the volume ratio, and planarization of the field oxide film is difficult.
따라서, 본 발명은 실리콘 기판의 필드영역(Field region)에 예비 필드 산화막을 형성시킨 후 식각하여 리세스(Recess) 구조를 형성시키고 노출되는 질화막 및 패드 산화막 측벽에 캐핑(Capping) 질화막을 형성시킨 후 최종 필드 산화막을 형성시키므로써 상기한 단점을 해소할 수 있는 반도체 소자의 필드 산화막 형성 방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, after forming a preliminary field oxide layer in a field region of the silicon substrate, the etching is performed to form a recess structure, and a capping nitride layer is formed on the exposed sidewalls of the nitride and pad oxide layers. It is an object of the present invention to provide a method for forming a field oxide film of a semiconductor device which can solve the above-mentioned disadvantages by forming a final field oxide film.
상기한 목적을 달성하기 위한 본 발명은 실리콘 기판(1) 상에 열산화 공정에 의해 패드 산화막(2)을 형성시기고 질화막(10) 및 CVD 산화막(4)을 순차적으로 형성시킨 후, 감광막(8)을 도포하고 패터닝하여 필드영역(B)을 설정하는 단계와, 상기 단계로부터 건식식각방법으로 상기 CVD 산화막(4) 및 질화막(10)의 노출된 부분을 순차적으로 식각하는 단계와, 상기 단계로부터 상기 감광막(8)을 제거시킨 후 산화공정을 진행하여 제 1 필드산화막(5)을 형성시키는 단계와, 상기 단계로부터 습식식각방법으로 상기 제 1 필드센화막(5) 및 CVD 산화막(4)을 제거시긴 후 상기 질화막(10) 및 패드 산화막(2) 측벽에 캐핑 질화막(6)을 형성시키는 단계와, 상기 단계로부터 산화공정에 의해 상기 필드영역에 제 2 필드산화막(7)을 형성시킨 후 습식식각 방법에 의해 상기 질화막(10), 캐핑 질화막(6) 및 패드산화막(2)을 순차적으로 제거시키는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to form a pad oxide film (2) by the thermal oxidation process on the silicon substrate (1) and to form the nitride film 10 and the CVD oxide film (4) sequentially, and then to the photoresist film ( 8) applying and patterning the field region B, sequentially etching the exposed portions of the CVD oxide film 4 and the nitride film 10 by dry etching from the step; Removing the photoresist film 8 from the photoresist film, and then performing an oxidation process to form the first field oxide film 5, and from the step, the first field sensitized film 5 and the CVD oxide film 4 by a wet etching method. After forming the capping nitride film 6 on the sidewalls of the nitride film 10 and the pad oxide film 2, and forming a second field oxide film 7 in the field region by the oxidation process from the step The nitride film 10 by a wet etching method, That comprises a ping nitride film 6 and the pad oxide film (2) in the step of sequentially removing characterized.
제 1a 및 제 1b 도는 종래 반도체 소자의 필드 산화막 형성방볍을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a field oxide film formation method of a conventional semiconductor device.
제 2a 내지 제 2g 도는 본 발명에 따른 반도체 소자의 필드 산화막 형성방법을 설명하기 위한 소자의 단면도.2A to 2G are cross-sectional views of a device for explaining a method of forming a field oxide film of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 패드 산화막1 silicon substrate 2 pad oxide film
3 및 10 : 질화막 4 : CVD 산화막3 and 10: nitride film 4: CVD oxide film
5 : 제 1 필드 산화막 6 : 개핑 질화막5: first field oxide film 6: gapped nitride film
7 : 제 2 필드 산화막 7A : 최종 필드 산화막7: second field oxide film 7A: final field oxide film
8 : 감광막 9 : 필드 산화막8: photosensitive film 9: field oxide film
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 2a 내지 제 2g 도는 본 발명에 따른 반도체 소자의 필드 산화막 형성방법을 설명하기 위한 소자의 단면도로서, 제 2a 도는 실리콘 기판(1) 상에 열산화(Thermal oxidation) 공정에 의해 패드 산화막(2)을 100 내지 300Å 두께로 형성시키고, 질화막(10) 및 CVD 산화막(4)을 순차적으로 형성시킨 후, 감광막(8)을 도포하고 패터닝하여 필드영역(B)을 설정(Define)한 상대의 단면도인데, 상기 질화막(10) 및 CVD 산화막(4)의 두께는 각각 1500 내지 2000Å 및 500 내지 1000Å으로 형성시킨다.2A to 2G are cross-sectional views of a device for describing a method of forming a field oxide film of a semiconductor device according to the present invention. FIG. 2A is a diagram illustrating a pad oxide film 2 on a silicon substrate 1 by a thermal oxidation process. Is formed to a thickness of 100 to 300 Å, the nitride film 10 and the CVD oxide film 4 are sequentially formed, and then the photosensitive film 8 is coated and patterned to define the field region B. The nitride film 10 and the CVD oxide film 4 are formed to have a thickness of 1500 to 2000 mW and 500 to 1000 mW, respectively.
제 2b 도는 건식식각(Dry Etch)방법으로 상기 CVD 산화막(4) 및 질화막(10)을 순차적으로 식각하여 상기 필드영역(B) 양측의 임계치수 바이어스(Critical dimlension bias) D만큼 감소된 영역(C)의 상기 패드 산화막(2)을 노출시킨 상태의 단면도인데, 이때 상기 CVD 산화막(4)은 상기 필드 영역(B)을 임계치수 바이어스 D만큼 감소시기기 위해 사용되며 상기 임계치수 바이어스는 0.05㎛ 이상 발생시킨다.FIG. 2B is a region C which is sequentially etched by the CVD oxide film 4 and the nitride film 10 by a dry etching method, and reduced by a critical di- ension bias D on both sides of the field region B. Is a cross-sectional view of the pad oxide film 2 in the exposed state, wherein the CVD oxide film 4 is used to reduce the field region B by a threshold bias D and the threshold bias is 0.05 µm or more. Generate.
제 2c 도는 상기 감광막(8)을 제거시킨 후 산화공정을 진행하여 제 1 필드산화막(5)을 500 내지 2000Å 두께로 성장시킨 상태의 단면도이다.FIG. 2C is a cross-sectional view of the first field oxide film 5 grown to a thickness of 500 to 2000 GPa by removing the photoresist film 8 and performing an oxidation process.
제 2d 도는 습식식각(Wet etch) 방법으로 상기 제 1 필드 산화막(5)을 완전히 제거시켜 상기 실리콘 기판(1)의 필드영역이 리세스 구조로 형성된 상태의 단면도인데, 이때 상기 CVD 산화막(4)도 제거되며, 상기 습식식각 시 식각제(Etchant)가 HF, NH4F, H2O로 구성된 BOE(Buffered Oxide Etchant)인 경우 제 1 필드 산화막(5)뿐만 아니라 상기 BOE 용액 중에 생성된 NH4OH 성분에 의해 상기 질화막(10) 하부의 실리콘 기판(1)도 D만큼 언더컷트(Undercut)된다. 또한 상기 식각제가 HF인 경우 제 1 필드 산화막(5)만 제거되어 언더컷트가 발생되지 않으므로 언더컷트를 형성시키기 위해서는 상기 제 1 필드 산화막(5)의 두께를 증가시켜 버즈비크를 형성시키고 습식식각해야 한다. 그러므로 상기 제 1 필드 산화막(5)의 두께가 800 내지 1500Å일 경우에는 B0E를 사용하고, 1500 내지 2000Å일 경우에는 HF를 사용한다.FIG. 2D is a cross-sectional view of a field region of the silicon substrate 1 having a recess structure by completely removing the first field oxide film 5 by a wet etch method, wherein the CVD oxide film 4 is formed. Also, when the etchant is a buffered oxide etchant (BOE) composed of HF, NH 4 F, and H 2 O, the NH 4 generated in the BOE solution as well as the first field oxide layer 5 may be removed. The silicon substrate 1 under the nitride film 10 is also undercut by D by the OH component. In addition, when the etchant is HF, only the first field oxide layer 5 is removed and no undercut is generated. Therefore, in order to form an undercut, the thickness of the first field oxide layer 5 must be increased to form a buzz beak and wet etching. do. Therefore, when the thickness of the first field oxide film 5 is 800 to 1500 kPa, B0E is used, and when it is 1500 to 2000 kPa, HF is used.
제 2e도는 소정의 질화막을 70 내지 120Å 두께로 증착한 후 건식식각하여 상기 질화막(10) 및 패드 산화막(2) 측벽에 캐핑 질화막(6)을 형성시킨 상태의 단면도이다. 이때, 캐핑 질화막(6)이 너무 두꺼우면 제 2f 도에 제 2 필드 산화막(7)양쪽 표면에 눌린 자욱이 남는다.FIG. 2E is a cross-sectional view of a predetermined nitride film having a thickness of 70 to 120 Å and dry etching to form a capping nitride film 6 on sidewalls of the nitride film 10 and the pad oxide film 2. At this time, if the capping nitride film 6 is too thick, depressed remains on both surfaces of the second field oxide film 7 in Fig. 2f.
제 2f 도는 산화공정에 의해 제 2 필드 산화막(7)을 2500 내지 3500Å 두께로 형성시킨 상태의 단면도인데, 이때 실리콘 기판(1) 상에 캐핑 질화막(6)은 성장하는 상기 제 2 필드산화막(7)에 의해 상부로 굽혀지며 상기 패드 산화막(2) 측벽은 그대로 캐핑(Capping)된다.FIG. 2F is a cross-sectional view of the second field oxide film 7 being formed to have a thickness of 2500 to 3500 Å by an oxidation process, wherein the capping nitride film 6 is grown on the silicon substrate 1. The upper side of the pad oxide film 2 is bent upwardly by the upper surface of the pad oxide film 2.
제 2g 도는 습식식각 방법에 의해 상기 질화막(10), 캐핑 질화막(6) 및 패드산화막(2)을 순차적으로 제거시켜 최종 필드 산화막(7A)이 형성된 상태의 단면도인데, 상기 제 2d,2e 도에서와 같이 실리콘 기판(1)의 언더컷트로 인하여 상기 실리콘 기판(1)의 필드영역 양측(E 부분)에 상기 캐핑 질화막(6)이 형성되어 상기 제 2 필드 산화막(5) 형성시 상기 필드영역 양측의 실리콘 기판(1)이 산소와 직접 접촉되지 않으므로 버즈비크의 생성이 방지된다.FIG. 2g is a cross-sectional view of the nitride film 10, the capping nitride film 6, and the pad oxide film 2 sequentially removed by a wet etching method to form a final field oxide film 7A. In FIGS. 2d and 2e, FIG. The capping nitride film 6 is formed on both sides (E portions) of the field region of the silicon substrate 1 due to the undercut of the silicon substrate 1, so that both sides of the field region are formed when the second field oxide film 5 is formed. Since the silicon substrate 1 is not in direct contact with oxygen, generation of the burj beak is prevented.
상술한 바와 같이, 본 발명에 의하면 버즈비크를 최소화시기고 체적비를 증가시켜 소자분리 효과를 증가시키며 평탄화를 향상시켜 후속공정을 용이하게 할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, there is an excellent effect of minimizing the buzz bee, increasing the volume ratio, increasing the device isolation effect, and improving the planarization to facilitate the subsequent process.
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