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KR100247642B1 - Method for forming a contact hole in semiconductor device - Google Patents

Method for forming a contact hole in semiconductor device Download PDF

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Publication number
KR100247642B1
KR100247642B1 KR1019970030364A KR19970030364A KR100247642B1 KR 100247642 B1 KR100247642 B1 KR 100247642B1 KR 1019970030364 A KR1019970030364 A KR 1019970030364A KR 19970030364 A KR19970030364 A KR 19970030364A KR 100247642 B1 KR100247642 B1 KR 100247642B1
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film
contact hole
insulating film
insulating
forming
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KR1019970030364A
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Korean (ko)
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KR19990006142A (en
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조경수
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 보다 구체적으로는 입구부의 폭이 접촉부에 비하여 넓은 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole having a wider width than an contact portion.

본 발명은, 도전 영역을 포함하는 반도체 기판 상에 제 1 절연막을 증착하는 단계; 상기 제 1 절연막 상부에, 제 1 절연막보다 식각 속도가 느린 제 2 절연막을 증착하는 단계; 상기 도전 영역 부분이 노출되도록 제 2 및 제 1 절연막의 소정 부분을 식각하여, 접촉부 홀을 형성하는 단계; 상기 접촉부 홀내에 제 2 절연막 보다 식각속도가 느린 막을 매립하는 단계; 상기 반도체 기판 구조물 상에 제 1 절연막과 동일한 식각 속도를 갖는 제 3 절연막을 증착하는 단계; 상기 제 3 절연막을 상기 접촉부 홀에 매립된 막 및 그 양측의 제 2 절연막이 노출되도록 패터닝하여, 입구부홀을 형성하는 단계; 및 상기 접촉부 홀에 매립된막을 제거하여, 콘택홀을 형성하는 단계를 포함한다.The present invention includes the steps of depositing a first insulating film on a semiconductor substrate including a conductive region; Depositing a second insulating layer on the first insulating layer, the second insulating layer having a lower etching speed than the first insulating layer; Etching a predetermined portion of the second and first insulating layers to expose the conductive region portion to form a contact hole; Filling a film having a slower etching speed than a second insulating film in the contact hole; Depositing a third insulating film having the same etching rate as that of the first insulating film on the semiconductor substrate structure; Patterning the third insulating film to expose the film embedded in the contact hole and the second insulating film on both sides thereof to form an inlet hole; And removing the film embedded in the contact hole to form a contact hole.

Description

반도체 소자의 콘택홀 형성방법Contact hole formation method of semiconductor device

본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 보다 구체적으로는 입구부의 폭이 접촉부에 비하여 넓은 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole having a wider width than an contact portion.

반도체 기술의 진보와 더불어 더 나아가서는 반도체 소자의 고속화, 고집적화가 진행되고 있고, 이에 수반해서 패턴에 대한 미세화의 필요성이 점점 높아지고 있으며, 또한 패턴의 칫수도 고정밀화가 요구되고 있다.In addition to the advances in semiconductor technology, the speed and integration of semiconductor devices are increasing, and the necessity of miniaturization of patterns is increasing, and the size of patterns is also required to be highly accurate.

종래에는 콘택되는 부분 즉 접촉부의 폭은 좁고, 입구부의 폭은 넓게 형성되어, 콘택을 용이하게 할 수 있는 T자형 콘택홀이 제안되었다.Conventionally, a contact portion, that is, a contact portion is narrow in width, the width of the inlet portion is formed wide, a T-shaped contact hole that can facilitate the contact has been proposed.

상기 T자형 콘택홀 구조를 첨부 도면 도 1a 및 도 1b를 참조하여 설명한다.The T-shaped contact hole structure will be described with reference to FIGS. 1A and 1B.

도 1a을 참조하여, 도전 영역(도시되지 않음)을 포함하는 반도체 기판(11) 상에 제 1 산화막(12)이 형성된다. 이 제 1 산화막(12) 상부에 제 1 산화막(12)과 식각률이 상이한 절연막 예를들어, 실리콘 질화막(13)이 비교적 얇은 박막으로 형성된 후, 실리콘 질화막(13)은 콘택홀 예정 부분이 노출되도록 패터닝된다. 이어, 결과물 상부에는 제 2 산화막(12)이 형성되고, 제 2 산화막(12) 상부에 콘택용 마스크 패턴(15)이 공지의 포토리소그라피 방식에 의하여 형성된다.Referring to FIG. 1A, a first oxide film 12 is formed on a semiconductor substrate 11 including a conductive region (not shown). An insulating film having an etch rate different from that of the first oxide film 12 on the first oxide film 12, for example, after the silicon nitride film 13 is formed of a relatively thin thin film, the silicon nitride film 13 is exposed so that the contact hole planned portion is exposed. Is patterned. Subsequently, a second oxide film 12 is formed on the resultant, and a contact mask pattern 15 is formed on the second oxide film 12 by a known photolithography method.

그리고나서, 도 1b에 도시된 바와 같이, 콘택 마스크 패턴(15)의 형태로 제 2 산화막(14)이 식각되어, 입구부 홀이 형성된다. 이어서, 노출된 실리콘 질화막(13)을 마스크로 하여, 하부의 제 1 산화막(12)을 식각하여 접촉부 홀을 형성하므로서, 입구부에 비하여 접촉부 홀이 좁은 콘택홀(H)이 형성된다. 그후, 마스크 패턴(15)은 공지의 방식으로 제거된다.Then, as shown in FIG. 1B, the second oxide film 14 is etched in the form of the contact mask pattern 15 to form an inlet hole. Subsequently, using the exposed silicon nitride film 13 as a mask, the lower first oxide film 12 is etched to form a contact hole, thereby forming a contact hole H having a narrower contact hole than the inlet part. Thereafter, the mask pattern 15 is removed in a known manner.

그러나, 상술한 바와 같이, 입구부의 홀을 형성한다음, 산화막들 사이에 형성된 질화막을 마스크로 하여 접촉부의 홀을 형성하게 되면, 실리콘 질화막(13)과 제 1 산화막(12)의 식각 속도차에 의하여, 콘택홀(H) 측벽이 일부 식각된다. 이를 레터럴(lateral) 식각이라 한다.However, as described above, when the hole of the inlet is formed and then the hole of the contact is formed using the nitride film formed between the oxide films as a mask, the etching rate difference between the silicon nitride film 13 and the first oxide film 12 is different. As a result, the sidewalls of the contact holes H are partially etched. This is called lateral etching.

이로 인하여, 콘택 영역의 디파인(define)이 어렵게 되는 문제점이 발생된다.As a result, a problem arises in that it is difficult to define the contact region.

따라서, 본 발명은 콘택홀 형성시, 측벽의 레터럴 식각을 방지하여, 콘택홀 디파인을 용이하게 할 수 있는 반도체 소자의 콘택홀 형성방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of facilitating contact hole definition by preventing lateral etching of sidewalls when forming a contact hole.

제1a도 및 제1b도는 종래의 반도체 소자의 콘택홀 형성방법을 설명하기 위한 도면.1A and 1B are views for explaining a method for forming a contact hole in a conventional semiconductor device.

제2a도 내지 제2h도는 본 발명에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 각 공정별 단면도.2A to 2H are cross-sectional views of respective processes for explaining a method for forming a contact hole in a semiconductor device according to the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 반도체 기판 2 : 제 1 산화막1: semiconductor substrate 2: first oxide film

3 : 실리콘 질화막 4, 7 : 마스크 패턴3: silicon nitride film 4, 7: mask pattern

5 : 포토레지스트막 6 : 제 2 산화막5: photoresist film 6: second oxide film

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 도전 영역을 포함하는 반도체 기판 상에 제 1 절연막을 증착하는 단계; 상기 제 1 절연막 상부에, 제 1 절연막보다 식각 속도가 느린 제2 절연막을 증착하는 단계; 상기 도전 영역 부분이 노출되도록 제 2 및 제 1 절연막의 소정 부분을 식각하여, 접촉부 홀을 형성하는 단계; 상기 접촉부 홀내에 제 2 절연막 보다 식각속도가 느린 막을 매립하는 단계; 상기 반도체 기판 구조물 상에 제 1 절연막과 동일한 식각 속도를 갖는 제 3 절연막을 증착하는 단계; 상기 제 3 절연막을 상기 접촉부 홀에 매립된 막 및 그 양측의 제 2 절연막이 노출되도록 패터닝하여, 입구부 홀을 형성하는 단계; 및 상기 접촉부 홀에 매립된막을 제거하여, 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention comprises the steps of: depositing a first insulating film on a semiconductor substrate including a conductive region; Depositing a second insulating film on the first insulating film, the second insulating film having a lower etching speed than the first insulating film; Etching a predetermined portion of the second and first insulating layers to expose the conductive region portion to form a contact hole; Filling a film having a slower etching speed than a second insulating film in the contact hole; Depositing a third insulating film having the same etching rate as that of the first insulating film on the semiconductor substrate structure; Patterning the third insulating film to expose the film embedded in the contact hole and the second insulating film on both sides thereof to form an inlet hole; And forming a contact hole by removing the film embedded in the contact hole.

본 발명에 의하면, 입구부가 접촉부 보다 넓은 콘택홀을 형성하는 공정에서, 접촉부의 콘택홀을 먼저 형성하고, 이부분을 포토레지스트막으로 매립한다음, 입구부의 홀을 형성하고, 레지스트 막을 제거하므로서, 콘택홀의 측벽이 레터럴 식각되는 현상이 방지된다.According to the present invention, in the step of forming a contact hole in which the inlet part is wider than the contact part, the contact hole of the contact part is formed first, and this part is filled with a photoresist film, and then the hole of the inlet part is formed and the resist film is removed, The sidewalls of the contact holes are laterally etched.

[실시예]EXAMPLE

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도면 도 2a 내지 도 2h는 본 발명에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 각 공정별 단면도이다.2A through 2H are cross-sectional views of respective processes for describing a method of forming a contact hole in a semiconductor device according to the present invention.

먼저, 도 2a를 참조하여, 반도체 기판(1)상에 제 1 산화막(2)과, 실리콘 질화막(3)이 순차적으로 형성된다. 이때, 반도체 기판(1)은 도전 영역을 포함하는 실리콘 기판일 수 있다. 또한, 실리콘 질화막(3) 대신에 산화막(2)보다 식각 속도가 매우 느린 금속 산화막 또는 실리콘 질산화막등이 이용될 수 있다. 이어, 실리콘 질화막(3) 상부에는 콘택 영역을 한정하기 위한 즉, 도전 영역이 노출될 수 있는 제 1 마스크 패턴(4)이 형성된다.First, referring to FIG. 2A, a first oxide film 2 and a silicon nitride film 3 are sequentially formed on the semiconductor substrate 1. In this case, the semiconductor substrate 1 may be a silicon substrate including a conductive region. Instead of the silicon nitride film 3, a metal oxide film, a silicon nitride oxide film, or the like, which has a much lower etching speed than the oxide film 2, may be used. Subsequently, a first mask pattern 4 is formed on the silicon nitride film 3 to define the contact region, that is, to expose the conductive region.

그후, 도 2b에 도시된 바와 같이, 이 제 1 마스크 패턴(4)의 형태로 실리콘 질화막(3)이 식각된다.Thereafter, as shown in FIG. 2B, the silicon nitride film 3 is etched in the form of the first mask pattern 4.

이어서, 도 2c에서와 같이, 소정 부분 식각이 이루어진 실리콘 질화막(3)을 마스크로 하여, 제 1 산화막(2)을 식각한후, 상기 제 1 마스크 패턴(4)을 제거하여, 접촉부의 홀(100)이 형성된다.Subsequently, as shown in FIG. 2C, the first oxide film 2 is etched using the silicon nitride film 3 having a predetermined partial etching as a mask, and then the first mask pattern 4 is removed to form a hole in the contact portion ( 100) is formed.

그런다음, 도 2d에 도시된 바와 같이, 반도체 기판(1) 상부에는 결과물이 충분히 매립되도록 실리콘 질화막보다 식각 속도가 현저히 느린막 예를들어, 포토레지스트막(5)이 도포된다.Then, as shown in FIG. 2D, a film, for example, a photoresist film 5 is applied to the upper portion of the semiconductor substrate 1 with a significantly slower etching rate than the silicon nitride film so that the resultant material is sufficiently embedded.

그후, 도 2e를 참조하여, 포토레지스트막(5)은 실리콘 질화막(3) 표면이 노출되도록 화학적 기계적 연마되어, 접촉부 홀내에 매립된다.Then, referring to FIG. 2E, the photoresist film 5 is chemically mechanically polished to expose the surface of the silicon nitride film 3 and embedded in the contact hole.

도 2f에 도시된 바와 같이, 구조물 상부에는 제 2 산화막(6)이 소정 두께로 증착된후, 제 2 산화막(6) 상부에 접촉부홀 부분이 포함되도록 제 2 마스크 패턴(7)이 형성된다.As shown in FIG. 2F, after the second oxide film 6 is deposited to a predetermined thickness on the structure, the second mask pattern 7 is formed to include the contact hole portion on the second oxide film 6.

그리고 나서, 도 2g에 도시된 바와 같이, 제 2 마스크 패턴(7)의 형태로 제 2 산화막(6)이 식각되어, 입구부 홀이 형성된다.Then, as shown in FIG. 2G, the second oxide film 6 is etched in the form of the second mask pattern 7 to form an inlet hole.

이어, 도 2h에 도시된 바와 같이, 제 2 마스크 패턴(7) 및 접촉부 홀내에에 매립된 포토레지스트막(5)은 공지의 플라즈마 에슁 방식에 의하여 제거되어, 레터럴식각이 발생되지 않는 콘택홀(H)이 형성된다.Then, as shown in FIG. 2H, the second mask pattern 7 and the photoresist film 5 embedded in the contact hole are removed by a known plasma etching method, so that no lateral etching occurs. (H) is formed.

이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 입구부가 접촉부 보다 넓은 콘택홀을 형성하는 공정에서, 접촉부의 콘택홀을 먼저 형성하고, 이부분을 포토레지스트막으로 매립한다음, 입구부의 홀을 형성하고, 레지스트 막을 제거하므로서, 콘택홀의 측벽이 레터럴 식각되는 현상이 방지된다.As described in detail above, according to the present invention, in the process of forming the contact hole with the inlet part wider than the contact part, the contact hole of the contact part is formed first, and this part is filled with a photoresist film, and then the hole of the inlet part is formed. By forming and removing the resist film, the phenomenon that the sidewalls of the contact holes are laterally etched is prevented.

따라서, 반도체 소자의 콘택홀 디파인이 용이하여 진다.Therefore, the contact hole fine of the semiconductor element becomes easy.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

도전 영역을 포함하는 반도체 기판 상에 제 1 절연막을 증착하는 단계; 상기 제 1 절연막 상부에, 제 1 절연막보다 식각 속도가 느린 제2 절연막을 증착하는 단계; 상기 도전 영역 부분이 노출되도록 제 2 및 제 1 절연막의 소정 부분을 식각하여, 접촉부 홀을 형성하는 단계; 상기 접촉부 홀내에 제 2 절연막 보다 식각속도가 느린 막을 매립하는 단계; 상기 반도체 기판 구조물 상에 제 1 절연막과 동일한 식각 속도를 갖는 제 3 절연막을 증착하는 단계; 상기 제 3 절연막을 상기 접촉부 홀에 매립된 막 및 그 양측의 제 2 절연막이 노출되도록 패터닝하여, 입구부 홀을 형성하는 단계; 및 상기 접촉부 홀에 매립된막을 제거하여, 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.Depositing a first insulating film on a semiconductor substrate including a conductive region; Depositing a second insulating film on the first insulating film, the second insulating film having a lower etching speed than the first insulating film; Etching a predetermined portion of the second and first insulating layers to expose the conductive region portion to form a contact hole; Filling a film having a slower etching speed than a second insulating film in the contact hole; Depositing a third insulating film having the same etching rate as that of the first insulating film on the semiconductor substrate structure; Patterning the third insulating film to expose the film embedded in the contact hole and the second insulating film on both sides thereof to form an inlet hole; And forming a contact hole by removing the film embedded in the contact hole. 제1항에 있어서, 상기 제 1 절연막과 제 3 절연막은 실리콘 산화막인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein the first insulating film and the third insulating film are silicon oxide films. 제1항 또는 제2항에 있어서, 상기 제 2 절연막은 실리콘 질화막, 실리콘 질산화막, 금속산화막 중 선택되는 하나의 막인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method according to claim 1 or 2, wherein the second insulating film is one of a silicon nitride film, a silicon nitride oxide film and a metal oxide film. 제1항에 있어서, 상기 접촉부 홀을 형성하는 단계, 상기 제 2 절연막 상부에 도전영역을 포함하는 부분이 노출되도록 마스크 패턴을 형성하는 단계; 상기 마스크 패턴의 형태로 제 2 절연막을 식각하는 단계; 상기 마스크 패턴 및 제 2 절연막을 마스크로 하여 제 1 절연막을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, further comprising: forming a contact hole, forming a mask pattern to expose a portion including a conductive region over the second insulating layer; Etching the second insulating film in the form of the mask pattern; And etching the first insulating film using the mask pattern and the second insulating film as a mask. 제1항에 있어서, 상기 접촉부 홀내에 매립되는 막은 포토레지스트막인 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein the film embedded in the contact hole is a photoresist film. 제5항에 있어서, 상기 접촉부 홀내에 제 2 절연막 보다 식각속도가 느린막을 매립하는 단계는, 반도체 기판 상에 상기 접촉부 홀이 충분히 매립되도록 포토레지스트막을 도포하는 단계; 상기 포토레지스트막을 상기 제 2 절연막 표면이 노출되도록 화학적 기계적 연마하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 5, wherein the embedding of the film having a slower etch rate than the second insulating layer in the contact hole comprises: applying a photoresist film to sufficiently fill the contact hole on a semiconductor substrate; And chemically polishing the photoresist film to expose the surface of the second insulating film.
KR1019970030364A 1997-06-30 1997-06-30 Method for forming a contact hole in semiconductor device KR100247642B1 (en)

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