KR102398505B1 - Display Device - Google Patents

Abstract

In the display device of the present invention, the timing controller controls pixel data of an input image having k (k is a natural number) bits, main data having j (j is a natural number less than k) bits, and sub data having (k-j) bits. , and a first EPI signal including main data and a second EPI signal including sub data are transmitted through a pair of data lines. The source drive IC receives the first and second EPI signals from the data line pair, restores main data and sub data from the first and second EPI signals, respectively, and returns pixel data including the restored main data and sub data. It is converted to data voltage and output. The first EPI signal is transmitted in the active period of the data enable signal, and the second EPI signal is transmitted in the horizontal blank period between adjacent active periods.

Description

Display Device

The present invention relates to a display device.

An active matrix driving type liquid crystal display uses a thin film transistor (hereinafter referred to as "TFT") as a switching element to display a moving picture. Since this liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), it is applied to displays in portable information devices, office devices, computers, etc., as well as being applied to televisions and is rapidly replacing cathode ray tubes.

A liquid crystal display device includes a plurality of source drive integrated circuits (hereinafter, referred to as “ICs”) for supplying data voltages to data lines of a liquid crystal display panel, and gate pulses (or scan pulses) to gate lines of the liquid crystal display panel. ) a plurality of gate drive ICs for sequentially supplying, and a timing controller for controlling the drive ICs.

The timing controller supplies digital video data, a clock for sampling digital video data, and a control signal for controlling the operation of the source drive ICs to the source drive ICs through an interface such as mini LVDS (Low Voltage Differential Signaling). . The source drive ICs convert digital video data input from the timing controller into analog data voltages and supply them to data lines.

In another method, the applicant of the present application connects the timing controller and the source drive ICs in a point-to-point manner to minimize the number of wirings between the timing controller and the source drive ICs and a new signal transmission protocol for stabilizing signal transmission. (hereinafter referred to as "EPI interface protocol") in Korean Patent Application 10-2008-0127458 (2008-12-15), US Application 12/543,996 (2009-08-19), Korean Patent Application 10-2008-0127456 (2008) -12-15), US Application 12/461,652 (2009-08-19), Korean Patent Application 10-2008-0132466 (2008-12-23), US Application 12/537,341 (2009-08-07), etc. there is.

The timing controller and the source drive IC transmit data through a pair of signal wiring pairs, but there is a limit to the speed of data transmission to each source drive IC.

An object of the present invention is to provide a display device capable of increasing data transmission speed.

The display device of the present invention includes a display panel, a timing controller, and a source drive IC. The display panel includes data lines, gate lines crossing the data lines, and pixels arranged in a matrix form. The timing controller divides the pixel data of the input image having k (k is a natural number) bits into main data having j (j is a natural number less than k) bits and sub data having (k-j) bits, the main data A first EPI signal including , and a second EPI signal including sub data are transmitted through the data line pair. The source drive IC receives the first and second EPI signals from the data line pair, restores main data and sub data from the first and second EPI signals, respectively, and returns pixel data including the restored main data and sub data. It is converted to data voltage and output. The first EPI signal is transmitted in the active period of the data enable signal, and the second EPI signal is transmitted in the horizontal blank period between adjacent active periods.

The display device of the present invention can efficiently transmit higher-bit image data by dividing and transmitting the bits of the image data by the timing controller. Accordingly, even if the grayscale value of the image data includes a grayscale value of “255' or higher, data transmission can be facilitated.

1 is a view showing a touch sensor embedded display device according to the present invention.
2 is a view showing a transmitter of a timing controller and a receiver of a source drive IC;
Fig. 3 is a diagram showing an example in which a timing controller divides data;
4 to 6 are diagrams showing examples of data packets;
7 is a waveform diagram showing the EPI protocol.
8 is a diagram illustrating output timing of EPI signals;
9 is a block diagram showing an internal circuit configuration of source drive ICs;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

The display device of the present invention includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode display (OLED). , OLED) and the like can be implemented as flat panel display devices. In the following embodiments, the liquid crystal display will be mainly described, but it should be noted that the display device of the present invention is not limited to the liquid crystal display.

1 is a view showing a display device according to the present invention.

1 , a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel (PNL), a timing controller (TCON), one or more source drive ICs (SIC#1 to SIC#4), and a gate drive IC (GIC) is provided.

A liquid crystal layer is formed between the substrates of the liquid crystal display panel PNL. The liquid crystal display panel PNL includes liquid crystal cells arranged in a matrix form by an intersecting structure of data lines DL and gate lines GL.

A pixel array including data lines DL, gate lines GL, TFTs, and storage capacitors is formed on the TFT array substrate of the liquid crystal display panel PNL. The liquid crystal cells are driven by an electric field between a pixel electrode to which a data voltage is supplied and a common electrode to which a common voltage is supplied through the TFT. The gate electrode of the TFT is connected to the gate line GL, and the drain electrode thereof is connected to the data line DL. The source electrode of the TFT is connected to the pixel electrode of the liquid crystal cell. The TFT is turned on according to a gate pulse supplied through the gate line GL to supply the data voltage from the data line DL to the pixel electrode of the liquid crystal cell. A black matrix, a color filter, and a common electrode are formed on the color filter substrate of the liquid crystal display panel PNL. A polarizing plate is attached to each of the TFT array substrate and the color filter array substrate of the liquid crystal display panel (PNL), and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed. A spacer for maintaining a cell gap of the liquid crystal cell Clc may be formed between the TFT array substrate of the liquid crystal display panel PNL and the color filter array substrate.

Liquid crystal display panel (PNL) is a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, or horizontal electric field driving method such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. can be implemented. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display device and a transflective liquid crystal display device. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

1 , a solid line is a pair of data lines through which signals such as a clock training pattern signal, control data, and video data of an input image are transmitted. In FIG. 1, a dotted line is a lock feedback signal wiring connected between the last source drive IC (SIC#4) and the timing controller (TCON).

The timing controller (TCON) enables vertical/horizontal synchronization signals (Vsync, Hsync) and external data from an external host system (not shown) through interfaces such as LVDS (Low Voltage Differential Signaling) interface and TMDS (Transition Minimized Differential Signaling) interface. An external timing signal such as a signal (Data Enable, DE) and a main clock (CLK) is received. The timing controller TCON is serially connected to each of the source drive ICs SIC#1 to SIC#4 through a data line pair. The timing controller (TCON) operates to satisfy the above-described EPI interface protocol to transmit digital video data of the input image to the source drive ICs (SIC#1 to SIC#4) and to the source drive ICs (SIC#1 to SIC#). 4) and the operation timing of the gate drive IC (GIC) are controlled. The timing controller (TCON) transmits the clock training pattern signal, control data, digital video data of the input image, etc. to the source drive ICs (SIC#1~SIC#4) according to the signal transmission standard determined by the EPI interface protocol. converted to , and serially transmitted to the source drive ICs (SIC#1~SIC#4) through the data wire pair. Signals transmitted from the timing controller TCON to the source drive ICs SIC#1 to SIC#4 include the EPI clock CLK.

The timing controller TCON transmits the clock training pattern signal to the source drive ICs SIC#1 to SIC#4 when the lock signal LOCK input through the lock feedback signal line is at a low logic level, and transmits the lock signal LOCK ) is inverted to a high logic level, the control data and digital video data transmission of the input image are resumed. The lock signal fed back to the timing controller TCON is inverted to a low logic level only when the recovery circuit outputs of all the source drive ICs SIC#1 to SIC#4 are unlocked.

The source drive ICs (SIC#1 to SIC#4) generate the output of the clock recovery circuit through clock training when a high logic level lock signal (LOCK) and a clock training pattern signal are input from the source drive IC of the previous stage. When the phase and frequency of the output are locked and the CDR function is stabilized, a high logic level lock signal is transmitted to the next stage source drive IC. When the CDR functions of all source drive ICs (SIC#1 to SIC#4) are stable, the last source drive IC (SIC#6) sends a high logic level lock signal (LOCK) to the timing controller (TCON) through the lock feedback signal wiring. ) is sent to The lock signal output terminal of the previous stage source drive IC is not connected to the lock signal input terminal of the first source drive IC (SIC#1). For this reason, the high logic level DC power voltage VCC is input to the lock signal input terminals of the first source drive ICs SIC#1. After the timing controller (TCON) receives the high logic level lock signal (LOCK) from the last source drive IC (SIC#4), the EPI clock (or EPI clock) embedded control data and video data are transmitted to the source drive ICs. Transmit serially to each (SIC#1~SIC#4). The control data includes source control data for controlling the output timing of the data voltage output from the source drive ICs SIC#1 to SIC#4, the polarity of the data voltage, and the like. The control data may include gate control data for controlling the operation timing of the gate drive IC (GIC).

Each of the source drive ICs SIC#1 to SIC#4 may be connected to the data lines of the liquid crystal display panel PNL by a chip on glass (COG) process or a tape automated bonding (TAB) process. The source drive ICs SIC#1 to SIC#4 receive a clock training pattern signal, control data, video data, etc. each having an EPI clock embedded therein through a pair of data lines. The CDR circuits of the source drive ICs (SIC#1 to SIC#4) input the EPI clock to the clock recovery circuit to generate the number of RGB bits of video data x 2 internal clocks. The clock recovery circuit outputs internal clocks and a mask signal using a phase locked loop (hereinafter referred to as “PLL”) or a delay locked loop (hereinafter referred to as “DLL”) and outputs a lock signal ( LOCK) occurs. The source drive ICs SIC#1 to SIC#4 sample the video data bits of the input image according to the internal clock timing and then convert the sampled RGB bits into parallel data.

The source drive ICs SIC#1 to SIC#4 restore the source control data and the gate control data by decoding the control data input through the data line pair using a code mapping method. The source drive ICs (SIC#1 to SIC#4) convert the video data of the input image into positive/negative analog video data voltages in response to the restored source control data to generate data lines of the liquid crystal display panel (PNL). (DL) is supplied. The source drive ICs SIC#1 to SIC#4 may transmit gate control data to one or more of the gate drive ICs GIC.

The gate drive IC (GIC) may be connected to the gate lines of the TFT array substrate of the liquid crystal display panel through a TAP process or may be directly formed on the TFT array substrate of the liquid crystal display panel (PNL) through a GIP (Gate In Panel) process. . The gate drive IC (GIC) is directly received from the timing controller (TCON) or in response to gate control data received through the source drive ICs (SIC#1 to SIC#4) to positive/negative analog video data voltage. Synchronized gate pulses are sequentially supplied to the gate lines GL.

2 is a diagram illustrating a transmitter Tx of the timing controller TCON and a receiver Rx of the source drive IC SIC. The source drive IC (SIC) shown in FIG. 2 refers to any one of the source drive ICs SIC#1 to SIC#4.

Referring to FIG. 2 , the timing controller TCON receives digital video data RGB of an input image from a host system through an LVDS interface or a TMDS interface. The timing controller TCON generates control data including source control data and gate control data based on an external timing signal input from a host system using an internal timing control signal generating circuit. The timing controller (TCON) rearranges the timing of the clock and data (RGB) input from the host system through the LVDS interface or the TMDS interface, and converts the clock into a difference signal pair between the data signals for EPI transmission do.

To this end, the transmission unit Tx includes a data alignment unit 21 , a clock generation unit 22 , a data packet generation unit 23 , and a transmission buffer 24 .

The data alignment unit 21 aligns and outputs digital video data RGB input from the host system according to the resolution of the liquid crystal display panel PNL.

The clock generator 22 generates a delimiter, which is a clock component, by frequency-dividing the synchronization signal SYNC input from the outside, for example, a dot clock. In addition, the clock generator 22 generates control data including source control data and gate control data based on the synchronization signal SYNC.

The data packet generation unit 23 generates data packets by inserting a delimiter, which is a clock component, between the data aligned by the data alignment unit 20 . A method of generating the data packet by the data packet generator 23 will be described later.

The transmission buffer 24 outputs the main data packet during the active period and outputs the sub data packet during the horizontal blank period.

The receiver Rx is built in each of the plurality of source drive ICs SIC connected to the timing controller TCON, and restores the delimiter and data from the data packet provided from the transmitter Tx, and Generates an internal clock to sample data. To this end, the reception unit Rx includes a reception buffer 31 , a recovery circuit 32 , a reference clock generation unit 33 , an internal clock generation unit 34 , a phase correction unit 35 , and a sampling circuit 36 . include The receive buffer 31 receives the difference signal pair transmitted from the timing controller TCON through the data wire pair.

The restoration circuit 32 restores the delimiter and data from the data packet provided through the reception buffer 31 . The reference clock generator 33 generates the reference clock CLK_Ref based on the delimiter restored from the recovery circuit 32 . The internal clock generator 34 generates a plurality of internal clocks CLKs using the reference clock CLK_Ref. For this, the internal clock generator 34 uses a PLL or a DLL. The plurality of internal clocks CLKs may be used as latch signals for sampling data. The phase corrector 35 compares the plurality of internal clocks CLKs generated by the internal clock generator 34 with the reference clock CLK_Ref to correct the phases of the plurality of internal clocks CLKs. When the phase correction of the plurality of internal clocks CLKs is completed, the phase correction unit 35 outputs a lock signal LOCK.

The sampling circuit 36 samples and outputs the data restored from the restoration circuit 32 using a plurality of internal clocks CLKs.

3 to 5 are diagrams illustrating a method of a data packet generator generating a data packet.

As shown in FIG. 3 , the data packet generator 23 divides the input image data Data into main data MData and sub data SData. The following embodiment will be mainly described in which one input image data (Data) includes R, G, and B sub-pixel data, and each of the R, G, and B sub-pixel data consists of 10-bit grayscale values. . The data packet generator 23 divides R sub-pixel data in the input image data Data into 8-bit main data MData and 2-bit sub data SData. Similarly, the data packet generator 23 divides the G sub-pixel data and the B sub-pixel data into 8-bit main data MData and 2-bit sub-data SData, respectively.

The data packet generator 23 may classify the upper 8 bits as the main data Mdata and the lower 2 bits as the sub data SData.

4 is a diagram illustrating a main data packet generated by the data packet generation unit, and FIG. 5 is a diagram illustrating a sub data packet generated by the data packet generation unit. 6 is a diagram illustrating clock bits and UIs of a main data packet and a sub data packet.

When there are n pixel columns, the data packet generator 23 generates first to nth main data packets MDP1 to MDPn. The first main data packet MDP1 includes first main data MData. Similarly, the ith (i is a natural number less than or equal to n) main data packet MDPi includes the ith main data MData. The first sub data packet SDP1 includes first sub data SData to fourth sub data SData. As a result, when the number of pixel columns is n, the number of sub data packets SDP is n/4.

As shown in FIG. 6 , clock bits are included before and after the main data (MData) bits. Clock bits are allocated by 4 UI between the data bits of neighboring packets, and its logical value may be allocated as “0 0 1 1 (or L L H H)”. 1 bit transmission time is 1 UI (Unit Interval) time and varies depending on the resolution of the liquid crystal display panel (PNL) or the number of data bits. As a result, when the number of data bits of the main data packet MDP is 8 bits, one packet may include 24 UI RGB data bits and 4 UI clock bits.

7 is a waveform diagram illustrating first and second EPI signals.

Referring to FIG. 7 , the first EPI signal EPI1 includes a main data packet MDP, and the second EPI signal EPI2 includes a sub data packet SDP. The timing controller (TCON) transmits a clock training pattern signal (or preamble signal) of a constant frequency to the source drive ICs (SIC#1 to SIC#4) during the first phase (Phase-I) and connects the lock feedback signal wiring. When the lock signal LOCK of a high logic level is input through the , the second phase (Phase-II) signal transmission is performed. The timing controller TCON transmits control data to the source drive ICs SIC#1 to SIC#4 during the second phase-II period, and when the lock signal LOCK maintains a high logic level, the first Transmitting the video data (RGB Data) of the input image to the source drive ICs (SIC#1 to SIC#4) by shifting to the third phase (Phase-III) signal transmission.

"Tlock" is the output of the clock recovery circuit of the source drive ICs (SIC#1 to SIC#4) is locked after the clock training pattern signal is input to the source drive ICs (SIC#1 to SIC#4). It is the time until the lock signal is inverted to a high logic level (H). This time (Tlock) is at least one horizontal period or more. One horizontal period is a time required for data to be written into liquid crystal cells arranged in one horizontal line of the liquid crystal display panel PNL.

The timing controller TCON resumes clock training of the source drive ICs SIC#1 to SIC#4 when a LOCK signal of a low logic level (L) is input from the last source drive IC SIC#4. In order to do this, it moves to the first step (Phase-I) and transmits the clock training pattern signal to the source drive ICs SIC#1 to SIC#4.

8A is a diagram illustrating transmission timings of the data enable signal DE and the first EPI signal EPI1 and the second EPI signal EPI2 according to the present invention, and FIG. 8B is a comparison diagram. It is a diagram showing the data enable signal DE according to an example.

Referring to FIG. 8A , the first EPI signal EPI1 is transmitted in the active period TA, and the second EPI signal EPI2 is transmitted in the horizontal blank period HB. The active period TA is defined as a high-level period of the data enable signal DE, and is a period in which one horizontal line is scanned. The horizontal blank period HB is defined as a low-level period of the data enable signal DE and is a rest period between the active periods TA.

In the present invention, the horizontal blank period HB must be sufficiently secured to transmit the second EPI signal EPI2. To this end, the active period TA of the present invention is reduced compared to the conventional active period TA′ shown in FIG. 7B . Accordingly, the horizontal blank period HB of the present invention increases compared to the conventional horizontal blank period HB'.

8 shows the internal circuit configuration of the source drive ICs (SIC#1 to SIC#4) according to the present invention.

Referring to FIG. 8 , the source drive ICs SIC#1 to SIC#4 supply positive/negative data voltages to k (k is a positive integer) data lines D1 to Dk.

Each of the source drive ICs SIC#1 to SIC#4 includes a latch unit, first and second digital-to-analog converters DAC, and an output unit AMP.

The latch unit Latch responds to an internal clock signal sequentially input from a shift register (not shown) to the main data MData of the first EPI signal EPI1 and the sub data SData of the second EPI signal EPI2. It is output after sampling and latching. The latch unit Latch outputs data in synchronization with a rising edge of the source output enable signal SOE.

The first and second digital-to-analog converters DAC convert main data Mdata and sub data SData input from the latch unit Latch into gamma compensation voltages to generate analog data voltages.

The output unit AMP supplies the positive/negative analog video data voltage to the data lines D1 to Dn through the output buffer during the low logic period of the source output enable signal SOE.

As described above, the display device of the present invention can transmit image data of higher bits efficiently by dividing the bits of the image data by the timing controller and transmitting them. Accordingly, even if the grayscale value of the image data includes a grayscale value of “255' or higher, data transmission can be facilitated.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

TCON: Timing controller SIC#1~SIC#4: Source drive IC
GIC : Gate Drive IC

Claims (6)

a display panel including data lines, gate lines crossing the data lines, and pixels arranged in a matrix form;
The pixel data of the input image having k (k is a natural number) bits is divided into main data having j (j is a natural number less than k) bits and sub data having (kj) bits, and the main data is included a timing controller for transmitting a first EPI signal and a second EPI signal including the sub data through a data line pair; and
The pixel receives the first and second EPI signals from the data line pair, restores the main data and the sub data from the first and second EPI signals, respectively, and includes the restored main data and sub data It includes a source drive IC that converts data into data voltage and outputs it,
The first EPI signal is transmitted in an active period of a data enable signal, and the second EPI signal is transmitted in a horizontal blank period between the adjacent active periods. delete The method of claim 1,
The active period is defined as a first level period of the data enable signal, and the horizontal blank period is defined as a second level period of the data enable signal. The method of claim 1,
The main data includes a predetermined upper bit in the pixel data,
The sub data includes a predetermined lower bit in the pixel data. The method of claim 1,
The first EPI signal includes one pixel data,
The second EPI signal includes two or more pixel data,
The pixel data includes data grayscale values of R, G, and B sub-pixels. 6. The method of claim 5,
the first and second EPI signals each include a data packet having 24 bits;
The first EPI signal includes 8 bits of R, G, and B data, respectively,
The second EPI signal includes four pixel data, and each of two bits of R, G, and B data of one pixel data is included in the display device.

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