KR102668460B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, where control data including timing information of a first latch output control signal, a second latch control signal, and a source output enable signal are transmitted to the source drive ICs, and then pixel data is transmitted to the wiring. It includes a timing controller that transmits data to the source drive ICs.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device that can freely change the data output timing of each source drive IC.

Various flat panel displays, such as liquid crystal display devices (LCDs) and electroluminescent displays, are commercially available. Electroluminescent displays are roughly divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage.

Data is written to the pixels of a flat panel display in one pixel line per horizontal period. The load of the display panel may vary depending on the RC delay difference depending on the wiring length between the timing controller and source drive ICs. This variation in the load of the display panel may cause the data voltage charging rate of the pixels to vary depending on the location of the display panel, which may result in deterioration of image quality.

To solve this problem, a timing controller uses a source output enable signal (hereinafter referred to as “SOE”) that controls the output timing of source drive ICs (Integrated Circuits (ICs)). The timing controller can change the output timing of the data voltage output from the source drive ICs to a different time for each IC, and output the data voltage from the source drive ICs at the delayed timing. The delayed SOE signal along with the delayed pixel data may be transmitted to the source drive ICs in order to delay the pixel data. Pixel data is temporarily stored in a register, and the pixel data is transmitted to the source drive IC after a preset delay time.

The timing controller requires memory or registers because it transfers pixel data to the source drive ICs for delay. Since the SOE signal must output pulses only during the horizontal blank time within one horizontal period, the range in which the output timing of the source drive ICs can be controlled with the SOE signal alone is limited.

The present invention aims to solve the above-described needs and/or problems.

The purpose of the present invention is to provide a display device that can freely change the output timing of data voltages output from source drive ICs without adding memory or registers to the timing controller.

The problem of the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment of the present invention includes a plurality of source drive ICs each including a first latch, a second latch, and a digital-to-analog converter connected between a shift register and an output buffer; and a timing controller connected to each of the source drive ICs through wires separated for each IC.

The timing controller transmits control data including timing information of the first latch output control signal, the second latch control signal, and the source output enable signal to the source drive ICs, and then sends pixel data to the source drive through the wires. Transmit to ICs.

The first latch outputs the stored pixel data in response to the first latch output control signal and supplies it to the second latch. The second latch supplies stored pixel data to the digital-to-analog converter in response to the second latch output control signal. The output buffer outputs a data voltage from the digital-to-analog converter in response to the source output enable signal.

A display device according to another embodiment of the present invention transmits control data including timing information of a first latch output control signal, a second latch control signal, and a source output enable signal to first and second source drive ICs, , and a timing controller that transmits a first pixel data packet to the first source drive IC and simultaneously transmits a second pixel data packet to the second source drive IC.

Each of the first and second source drive ICs includes a first latch, a second latch, and a digital-to-analog converter connected between a shift register and an output buffer.

The first latch outputs the stored pixel data in response to the first latch output control signal and supplies it to the second latch. The second latch supplies stored pixel data to the digital-to-analog converter in response to the second latch output control signal. The output buffer outputs a data voltage from the digital-to-analog converter in response to the source output enable signal.

The data voltage output timing of the first source drive IC and the data voltage output timing of the second source drive IC are different from each other.

A display device according to another embodiment of the present invention transmits control data including timing information of a latch output control signal and a source output enable signal to first and second source drive ICs, and sends the first pixel data packet to the first and second source drive ICs. It includes a timing controller that transmits a second pixel data packet to the second source drive IC at the same time as transmitting the second pixel data packet to the first source drive IC.

Each of the first and second source drive ICs includes a latch that outputs stored data to a digital-to-analog converter in response to the latch output control signal; and an output buffer that outputs a data voltage from the digital-to-analog converter in response to the source output enable signal.

The data voltage output timing of the first source drive IC and the data voltage output timing of the second source drive IC are different from each other.

According to the present invention, the timing controller transmits control signal information for controlling the output timing of the latch and the output timing of the output buffer to each of the source drive ICs and then simultaneously transmits pixel data. Source drive ICs restore control signal information to generate a latch output control signal and a source output enable signal, output latch data in response to the latch output control signal, and output a data voltage in response to the source output enable signal.

Therefore, in the present invention, since there is no need to control the transmission timing of pixel data transmitted from the timing controller to the source drive ICs differently for each IC, the output timing of the source drive ICs can be controlled differently without adding memory or registers to the timing controller. You can.

Additionally, the present invention can freely change the latch data output timing and data voltage output timing of each source drive IC by coding the control signal information transmitted to each of the source drive ICs with different values.

Furthermore, the present invention can improve image quality by equalizing the data charging rate of pixels by controlling the output timing of the source drive ICs even if there is a difference in RC delay between the timing controller and the source drive ICs.

1 is a block diagram showing a display device according to an embodiment of the present invention.
Figure 2 is a diagram showing the EPI interface topology for connecting the timing controller and source drive ICs.
Figure 3 is a waveform diagram showing the signal transmission protocol of the EPI interface.
Figure 4 is a diagram illustrating one data packet in the EPI interface.
Figure 5 is a waveform diagram showing the EPI signal transmitted during the horizontal blank period.
Figure 6 is a waveform diagram showing the internal clock restored from the source drive.
Figure 7 is a block diagram showing the timing controller and source drive IC connected through the EPI interface.
Figures 8 and 9 are diagrams showing control packets in detail.
Figure 10 is a waveform diagram showing timing information of the SOE signal and CLAT signal stored in the control packet.
Figure 11 is a waveform diagram showing an example of a CLAT signal and a SOE signal.
Figure 12 is a diagram showing the EPI signal output timing of the timing controller and the data voltage output timing of the source drive IC.
Figure 13 is a block diagram showing the source drive IC in detail.
Figure 14 is a waveform diagram showing the input/output timing of the first and second latches controlled by the CLAT signal.
Figure 15 is a diagram showing an example of a CLAT signal that is individually controlled for each source drive IC.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms. The embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “comprises,” “includes,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two components is described as 'on top', 'on top', 'on the bottom', 'next to ~', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component. Since the patent claims are written focusing on essential components, the ordinal numbers preceding the component names of the patent claims and the ordinal numbers preceding the component names of the embodiments may not match.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

Hereinafter, various embodiments of the present specification will be described in detail with reference to the attached drawings.

The display device of the present invention can be applied to any flat panel display device including timing controller and source drive ICs.

Referring to FIGS. 1 and 2 , a display device according to an embodiment of the present specification includes a display panel 100 and a display panel driver.

The display panel 100 includes a screen AA on which an input image is reproduced. The screen AA includes a pixel array on which pixel data of the input image is displayed. The pixel array includes a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, and a plurality of pixels.

Pixels may be arranged on the screen AA in a matrix form defined by data lines DL and gate lines GL. In addition to the matrix form, pixels can be arranged on the screen AA in various ways, such as in a form that shares pixels emitting the same color, in a stripe form, or in a diamond form.

The pixel array includes a pixel column and pixel lines (L1 to Ln) that intersect the pixel column. A pixel column contains pixels arranged along the y-axis direction. A pixel line contains pixels arranged along the x-axis direction. One vertical period is one frame period required to write one frame worth of pixel data to all pixels on the screen. This is the time required to write 1 line worth of pixel data sharing a gate line to the pixels of 1 pixel line. 1 horizontal period is the time divided by 1 frame period by the number of m pixel lines (L1 to Lm).

Each pixel may be divided into a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel to implement color. Each of the pixels may further include a white subpixel. Each of the subpixels 101 includes the same pixel circuit.

For an organic light emitting display device, the pixel circuit may include a light emitting element, a driving element, one or more switch elements, and a capacitor. The light emitting device can be implemented as OLED. The current of the OLED can be adjusted according to the gate-source voltage of the driving element. The driving element and switch element may be implemented as transistors. The pixel circuit is connected to the data line (DL) and gate line (GL). In FIG. 1, “D1 to D3” shown in circles are data lines, and “Gn-2 to Gn” are gate lines. Each of the subpixels 101 may include the same pixel circuit.

Touch sensors may be disposed on the display panel 100. Touch input can be sensed using separate touch sensors or sensed through pixels. The touch sensors are of the on-cell type or add-on type, arranged on the screen (AA) of the display panel 100 or embedded in the pixel array. It can be implemented with touch sensors.

The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver writes pixel data of the input image to the pixels of the display panel 100 under the control of a timing controller (Timing controller, TCON) 130.

The data driver 110 converts the pixel data (SDATA) of the input image received from the timing controller 130 into a gamma compensation voltage using a digital to analog converter (hereinafter referred to as “DAC”) and provides a data voltage. occurs. The data driver 110 supplies data voltage to the data lines DL. The pixel data voltage is supplied to the data lines DL and applied to the pixel circuit of the subpixels 101 through the switch element. The data driver 110 may be implemented with one or more source drive ICs (SIC1 to SICn) as shown in FIG. 2.

The gate driver 120 may be formed in the bezel area BZ outside the screen of the display panel 100 where no image is displayed. The gate driver 120 sequentially supplies a gate signal synchronized to the data voltage to the gate lines GL under the control of the timing controller 130. The gate signal simultaneously selects the pixel line where the data voltage is charged.

The gate driver 120 outputs a gate signal and shifts the gate signal using one or more shift registers. The gate signal may include one or more scan signals and an emission control signal (EM).

The timing controller 130 receives pixel data (DATA) of an input image and a timing signal synchronized with the pixel data (DATA) from a host system (not shown). The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE). Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) can be omitted.

The timing controller 130 uses timing signals (Vsync, Hsync, DE) received from the host system to control the operation timing of the data driver 110, a source timing control signal (DDC), and a gate driver 120. Generates a gate timing control signal (GDC) to control operation timing. The source timing control signal (DDC) is the SOE signal that controls the output timing of each of the source drive ICs (SIC1 to SICn), and the latch output control that controls the output timing of the latch in each of the source drive ICs (SIC1 to SICn). Generates a signal (hereinafter referred to as “CLAT signal”). The SOE signal and CLAT signal control the latch output timing and buffer output timing of each of the source drive ICs (SIC1 to SICn) every horizontal period. Accordingly, pulses of the SOE signal and CLAT signal are generated every horizontal period.

The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel drivers 110 and 120 with a frame frequency of input frame frequency x i (i is a positive integer greater than 0) Hz. . The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) method and 50Hz in the PAL (Phase-Alternating Line) method.

The host system may be any one of a television (TV), set-top box, navigation system, personal computer (PC), home theater, mobile device, or wearable device. In mobile devices and wearable devices, the data driver 110, timing controller 130, level shifter 140, etc. may be integrated into one drive IC.

The level shifter 140 converts the voltage of the gate timing control signal (GDC) output from the timing controller 130 into a gate high voltage (VGH) and a gate low voltage (VGL) and supplies them to the gate driver 120. The low level voltage of the gate timing control signal (GDC) is converted to the gate low voltage (VGL), and the high level voltage of the gate timing control signal (GDC) is converted to the gate high voltage (VGH). is converted to

The timing controller 130 can transmit pixel data to the source drive ICs (SIC1 to SICn) through an Embedded Clock Point to Point Interface (EPI) interface. As shown in FIG. 2, the EPI interface connects the timing controller 130 and the source drive ICs (SIC1 to SICn) in a point-to-point manner to connect the timing controller 130 and the source drive ICs (SIC1 to SICn). ~SICn) can be minimized. The EPI (Embedded Clock Point to Point Interface) interface does not require separate clock wires and control wires because the EPI signal, including control data and pixel data with an embedded clock, is transmitted through the data wire pair 12.

The data wire pairs 12 are divided by source drive IC and can connect the timing controller 130 to the source drive ICs (SIC1 to SICn). The timing controller 130 and the source drive ICs (SIC1 to SICn) may be connected in series through the data wire pair 12.

In the case of the EPI interface, each of the source drive ICs (SIC1 to SICn) may include a clock recovery unit (not shown) for CDR (Clock and Data Recovery). The timing controller 130 transmits a clock training pattern (clock training pattern or preamble) signal to the source drive ICs (SIC1 to SICn) so that the output phase and frequency of the clock recovery unit can be locked. The clock recovery unit built into the source drive ICs (SIC1 to SICn) restores the clock signal when the clock training pattern signal and clock signal of the EPI signal received through the data wire pair 12 are input, and the multi-phase as shown in FIG. Generates an internal clock (CDR CLK).

When the phase and frequency of the internal clock (CDR CLK) are locked, the source drive ICs (SIC1 to SICn) send a high logic level lock signal (LOCK) that indicates a stable output state. Feedback is input to the timing controller 130. A high logic level DC power supply voltage (VCC) is input to the lock signal input terminal of the first source drive ICs (SIC1). The lock signal (LOCK) is fed back to the timing controller 130 through the lock feedback wire 13 connected to the timing controller and the last source drive IC (SICn).

In the signal transmission protocol of the EPI interface, the timing controller 130 transmits a clock training pattern signal to the source drive ICs (SIC1 to SICn) before transmitting control data and pixel data of the input image. The clock recovery unit of the source drive IC (SIC1 to SICn) performs a clock training operation based on the clock training pattern signal to restore the clock received through the data wire pair 12 to generate an internal clock. When the phase and frequency of the clock are stably fixed, a data link with the timing controller 130 is established.

The timing controller 130 transmits control data and pixel data to the source drive ICs (SIC1 to SICn) through the data wire pair 12 in response to the lock signal (LOCK) received from the last source drive IC (SICn). Let's begin. The output signal of the timing controller 130 is converted into a differential signal through the transmitting end buffer of the timing controller 130 and transmitted to the source drive ICs (SIC1 to SICn) through the data wire pair 12.

The source drive ICs (SIC1 to SICn) sample control data bits from signals received through the data wire pair 12 at internal clock timing, and generate a source timing control signal (DDC) from the sampled control data. can be restored. The control data may include a control signal that controls the functions of the source drive ICs (SIC1 to SICn) and the gate driver 120 along with the source timing control signal (DDC).

The source drive ICs (SIC1 to SICn) sample pixel data bits from the signal received through the wire pair 12 in accordance with the internal clock timing, and then use a latch to sample the sampled pixel data. Convert the bits into parallel data. The source drive ICs (SIC1 to SICn) convert pixel data into a gamma compensation voltage in response to the restored timing control signal (DDC) and output a data voltage. Data voltage is supplied to the data lines DL.

Figure 3 is a waveform diagram showing the signal transmission protocol of the EPI interface.

Referring to FIG. 3, the timing controller 130 transmits a clock training pattern signal (or Preamble signal) of a certain frequency to the source drive ICs (SIC1 to SICn) in the first phase (Phase-I) and lock feedback wire ( When a high logic level (high logic level or 1) lock signal (LOCK) is input through 13), the second step (Phase-II) is performed to transmit the EPI signal with data in the signal format defined in the EPI interface protocol. I start to do it. In the second phase (Phase-II), the control data packet (CTR) is transmitted to the source drive ICs (SIC1 to SICn).

EPI signals (EPI data) include control packets and pixel data in the interface signal transmission protocol. Following the second step (Phase-II), the timing controller 130 performs the third step (Phase-III) when the lock signal (LOCK) is maintained at a high logic level to collect the pixel data packet including the pixel data of the input image. Pixel data (DATA) is transmitted to source drive ICs (SIC1 to SICn).

The timing controller 130 scrambles pixel data to reduce EMI on the data wire pair 12. In Figure 3, DATA means pixel data.

In FIG. 3, “Tlock” is the time until the lock signal is inverted to the high logic level (H). During Tlock, the clock training pattern signal is input to the source drive ICs (SIC1 to SICn), and the frequency and phase of the internal clock output from the clock recovery unit of the source drive ICs (SIC1 to SICn) are locked, thereby locking the lock signal ( LOCK) can be inverted to a high logic level (H). This time (Tlock) may be one horizontal period or more.

The timing controller (TCON) performs the first step ( Phase-Ⅰ) is executed to transmit the clock training pattern signal to the source drive ICs (SIC1 to SICn). If the clock is not restored normally from the clock recovery unit in an unexpected situation during the execution of the second phase (Phase-II) signal and the third phase (Phase-III), any one of the source drive ICs (SIC1 to SICn) may send a lock signal ( Invert LOCK) to low logic level (L). In this case, the timing controller 130 receives a lock signal (LOCK) of low logic level (L) from the last source drive IC (SICn) in the second phase (Phase-II) signal or the third phase (Phase-III). When input, the first phase (Phase-I) is executed in response to the clock training pattern signal to be transmitted to the source drive ICs (SIC1 to SICn). At this time, control data (CTR) and pixel data (SDATA) are not received by the source drive ICs (SIC1 to SICn).

Figure 4 is a diagram illustrating one data packet in the EPI interface.

Referring to FIG. 4, one data packet of the EP signal transmitted from the EPI interface to the source drive ICs (SIC1 to SICn) includes data bits and clock bits (EPI CLK) allocated before and after the data bits. . Data bits are bits of control data or pixel data. 1 bit transmission time is 1 UI (Unit Interval) time. 1 UI varies depending on the resolution of the display panel (PNL) or the number of data bits.

Clock bits (EPI CLK) are allocated as much as 4 UI between neighboring data packets, and the logic value may be set to “0 0 1 1 (or L L H H)”, but is not limited to this. When the number of data bits is 10 bits, one pixel data packet may include 30 UI data bits and 4 UI clock bits. When the number of data bits is 8 bits, 1 packet contains 24 UI data bits including 8 bits of R subpixel data, 8 bits of G subpixel data, and 8 bits of B subpixel data, and 4 UIs of clock. May contain bits. When the number of data bits is 6 bits, 1 packet may include 18 UI of RGB data bits and 4 UI of clock bits, but is not limited to this.

1 The horizontal period (1H) is a horizontal blank period (HB in FIG. 11) in which pixel data is not transmitted to the source drive ICs (SIC1 to SICn), and the pixel data is transmitted to the source drive ICs (SIC1 to SICn). It can be divided into a horizontal active section (HA in FIG. 11) transmitted. Control data packets may be transmitted to the source drive ICs (SIC1 to SICn) in the horizontal blank section (HB).

In the EPI interface protocol, the first phase (Phase-I) and the second phase (Phase-II) are performed in the horizontal blank section (HB) of one horizontal period (1H). The horizontal blank section (HB) corresponds to the low logic level section of the data enable signal (DE). In FIG. 5, “DE” is a data enable signal (DE). One pulse period of the data enable signal (DE) is one horizontal period (1H). The high logic period of the data enable signal (DE) corresponds to the horizontal active period. The third stage (Phase-III) is executed within the high logic section of the data enable signal (DE), that is, the pulse width, and the pixel data packet including pixel data (DATA) is transmitted to the source drive ICs (SIC1 to SICn). do.

Figure 6 is a waveform diagram showing the internal clock restored from the source drive ICs (SIC1 to SICn). In FIG. 6, “EPI” is an EPI signal received by the source drive ICs (SIC1 to SICn) through the data wire pair 12. “CDR CLK” is a multi-phase internal clock output from the clock recovery unit of the source drive ICs (SIC1 to SICn).

Referring to FIG. 6, the clock recovery unit of each of the source drive ICs (SIC1 to SICn) uses a phase locked loop (PLL) or delay locked loop (DLL) to generate multi-phase internal clocks. (CDR CLK) is output. The clock recovery unit receives the clock training pattern signal received through the data wire pair 12 and generates an output. When the phase and frequency of the output are the same as the input clock, the clock recovery unit inverts the lock signal (LOCK) to a high level and then EPI By restoring the clock of the signal, a multi-phase internal clock (CDR CLK) is generated. The multi-phase internal clock (CDR CLK) is generated as clocks whose phases are sequentially delayed so that the rising edge of the clock is synchronized with each bit of the data packet. The source drive ICs (SIC1 to SICn) can sample bits of data on the rising edge of the internal clock (CDR CLK).

Figure 7 is a block diagram showing the timing controller and source drive IC connected through the EPI interface.

Referring to FIG. 7, the timing controller 130 may include a data link layer 131 and a physical layer 132.

The data link layer 131 is a digital processing unit that receives pixel data (digital data) of an input image from the host system and aligns it to the signal format defined in the EPI interface protocol. For example, the data link layer can generate control data packets to control the functions and input/output timing of each source drive IC before transmitting the pixel data packets and map them in front of the pixel data. The control data packet includes at least an SOE signal and a CLAT signal. This control data packet indicates the transmission timing of pixel data based on bit number information defined by the EPI interface protocol and may include pixel data packet information. Control data for controlling various functions of the source drive ICs (SIC1 to SICn) may be added to the control data packet. Furthermore, control data for controlling the gate driver 102 may be added to the control data packet.

The data link layer 131 transmits the pixel data packet to the source drive ICs (SIC1 to SICn) and then transmits a clock training pattern signal (or preamble signal) to the source drive ICs (SIC1 to SICn) before transmitting the next control packet. do.

The physical layer 132 is an analog processing unit. The physical layer 132 stores the EPI signal (EPI data) output from the timing controller 130 to meet the eye characteristic requirement level of the EPI signal (EPI data) received from the source drive ICs (SIC1 to SICn). Processes analog characteristics. For example, the physical layer 132 processes output swing level control and pre-emphasis of the EPI signal (EPI data).

The EPI signal (EPI data) is transmitted to each of the source drive ICs (SIC1 to SICn) through the data wire pair 12 connected between the timing controller 130 and the source drive ICs (SIC1 to SICn). The first EPI signal (EPI1) is transmitted to the first source drive IC (SIC1) through the first data wire pair 12. The second EPI signal (EPI2) is transmitted to the second source drive IC (SIC2) through the second data wire pair 12. The nth EPI signal (EPIn) is transmitted to the nth source drive IC (SICn) through the nth data wire pair 12.

Figures 8 and 9 are diagrams showing the control packet (CTR) in detail. Figure 10 is a waveform diagram showing timing information of the SOE signal and CLAT signal stored in the control packet.

8 to 10, the control packet (CTR) includes first to third control data (CTR1, CTR2, CTR3). At least one of the first to third control data (CTR1, CTR2, CTR3) may include timing information of the SOE signal and the CLAT signal. The timing information of the SOE signal and the CLAT signal may include information indicating the rising time of the pulse (ts1, ts2) and the pulse duration time (tw1, tw2), as shown in FIG. 10.

Figure 11 is a waveform diagram showing an example of a CLAT signal and a SOE signal.

Referring to FIG. 11, the timing controller 130 may transmit a CLAT signal and a SOE signal to each of the source drive ICs (SIC1 to SICn) by transmitting a control packet to each of the source drive ICs (SIC1 to SICn).

Each of the source drive ICs (SIC1 to SICn) restores the CLAT signal and SOE signal based on the timing information defined in the control packet. The source drive ICs (SIC1 to SICn) sample the bits of the pixel data packet received following the control packet at the internal clock timing and provide it to the latch. The latch receives bits of pixel data sequentially input from the shift register, stores them temporarily, and then outputs them in response to the pulse of the CLAT signal.

The CLAT signal can control the output timing of the latch in each of the source drive ICs (SIC1 to SICn) within a time period less than 1 horizontal period (1H). A pulse of the CLAT signal is generated every 1 horizontal period (1H). Therefore, one cycle of the CLAT signal is one horizontal period (1H). The CLAT signal may be generated in a horizontal blank section (HB) without pixel data, but is not limited to this.

The SOE signal indicates the output timing of the data voltage output from the DAC. A pulse of the SOE signal is generated every 1 horizontal period (1H).

Without the CLAT signal, the output timing of the latch cannot be controlled individually by the source drive IC. The SOE signal controls the output timing of the source drive ICs (SIC1 to SICn) with a period of 1 horizontal period (1H). If there is no CLAT signal, the transmission timing of pixel data must be delayed for each source drive IC using memory or registers within the timing controller 130. If the latch output timing is not delayed using the CLAT signal, the pulse of the SOE signal must be generated in the horizontal blank section (HB) every horizontal period.

The present invention can use the CLAT signal to delay the latch output timing of the source drive ICs (SIC1 to SICn) differently for each IC within a time less than one horizontal period in each horizontal period. The timing controller 130 individually controls the output timing of the source drive ICs (SIC1 to SICn) for each IC using the CLAT signal and the SOE signal without the need to individually control the transmission timing of the pixel data to be transmitted to the source drive ICs. You can control it. In an embodiment of the present invention, the SOE signal pulse may be generated in the horizontal active period (HA) because the latch output timing is delayed by the CLAT signal.

FIG. 12 is a diagram showing the EPI signal output timing of the timing controller 130 and the data voltage output timing of the source drive IC.

Referring to FIG. 12, the timing controller 130 simultaneously transmits EPI signals to the source drive ICs (SIC1 to SICn).

The timing controller 130 simultaneously transmits control data packets in which timing information of the SOE signal and the CLAT signal are individually set for each source drive IC to the source drive ICs (SIC1 to SICn). Next, the timing controller 130 simultaneously transmits pixel data packets to the source drive ICs (SIC1 to SICn). The timing controller 130 simultaneously transmits the EPI signal to the source drive ICs without delaying the EPI signal for each source drive IC.

Each of the source drive ICs (SIC1 to SICn) outputs the data voltage of the pixel data to the data lines (DL) of the pixel areas it is responsible for. The first source drive IC (SIC1) receives the first control data packet and the first pixel data packet, restores the CLAT signal and the SOE signal from the first control data packet, and connects the data lines of the first pixel area on the screen AA. Outputs data voltage. The mth (m is a natural number smaller than n) source drive IC (SICm) receives the mth control data packet and the mth pixel data packet, restores the CLAT signal and SOE signal from the mth control data packet, and displays the mth control data packet on the screen (AA). Data voltage is output to the data lines of the mth pixel area. The nth source drive IC (SICn) receives the nth control data packet and the nth pixel data packet and restores the CLAT signal and SOE signal from the nth control data packet to the data lines in the nth pixel area on the screen AA. Outputs data voltage.

Pixel data packets are simultaneously transmitted from the timing controller 130 to all source drive ICs (SIC1 to SICn), but the output timing of the source drive ICs (SIC1 to SICn) is determined by the CLAT signal and SOE signal individually set for each source drive IC. A time difference (Δt1, Δt2) may occur. For example, the output timing of the mth source drive IC (SICm) may be delayed by Δt1 compared to the output timing of the first source drive IC (SIC1). The output timing of the first source drive IC (SIC1) may be delayed by Δt2 compared to the output timing of the nth source drive IC (SICn). The output timing time difference between the source drive ICs (SIC1 to SICn) may vary depending on the RC delay difference depending on the wiring length between the timing controller 130 and the source drive ICs (SIC1 to SICn).

Figure 13 is a block diagram showing the source drive IC in detail. In Figure 13, the clock recovery unit is omitted. Figure 13 illustrates one source drive IC, and other source drive ICs also have the same configuration as Figure 13. Figure 14 is a waveform diagram showing the input/output timing of the first and second latches controlled by the CLAT signal.

13 and 14, the source drive IC includes a first latch (LAT1), a second latch (LAT2), a DAC, and an output buffer (BUF) disposed between the shift register (SR) and the output buffer (BUF). Includes.

The shift register (SR) sequentially samples bits of pixel data at the timing of the internal clock and supplies them to the first latch (LAT1). In FIG. 14 , N-1 DATA, N DATA, N+1 DATA, and N+2 data at the top represent the N-1th to N+1th pixel line data sampled by the shift register (SR). The N-1th pixel line data is pixel data to be written in pixels arranged on the N-1th pixel line. N-th pixel line data is pixel data to be written in pixels arranged on the N-th pixel line.

The first latch (LAT1) is connected between the shift register (SR) and the second latch (LAT2). The first latch LAT1 includes first switch elements SW1 connected to each of the channels of the second latch LAT2. The first switch elements (SW1) receive the first CLAT signal (CLAT1) and are turned on according to the pulse of the first CLAT signal (CLAT1) to output the pixel data stored in the first latch (LAT1). It is supplied to the second latch (LAT2).

The first latch LAT1 may store pixel data sequentially input from the shift register SR and output the pixel data in response to a pulse of the first CLAT signal CLAT1. As shown in FIG. 14 , the first switch elements SW1 may simultaneously output bits of the stored N-th pixel line data in synchronization with the rising edge of the first CLAT signal CLAT1. In Figure 14, Lout represents the output of the first latch (LAT1). Hiz represents a high impedance state with no output from the first latch (LAT1). Until the nth pulse of the first CLAT signal CLAT1 is input to the first latch LAT1, the nth pixel line data is stored in the first latch LAT1.

The pulse of the first CLAT signal CLAT1 may be generated in the horizontal blank section HB every horizontal period, as shown in FIGS. 11 and 15. The timing controller 130 transmits timing information of the first CLAT signal CLAT1, which has the same timing information, to the source drive ICs SIC1 to SICn. Accordingly, the source drive ICs (SIC1 to SICm) may generate the first CLAT signal (CLAT1) with no delay time difference between the ICs. In this case, the output timing of the first latch (LAT1) can be controlled equally among the source drive ICs (SIC1 to SICm).

The second latch (LAT2) is connected between the first latch (LAT2) and the DAC. The second latch LAT2 includes second switch elements SW2 connected to each of the channels of the DAC. The second switch elements SW2 receive the second CLAT signal CLAT2 and are turned on according to the pulse of the second CLAT signal CLAT2 to supply the pixel data stored in the second latch LAT2 to the DAC.

The second latch LAT2 may store pixel data input from the first latch LAT1 and output the pixel data in response to the pulse of the second CLAT signal CLAT2. As shown in FIG. 14 , the second switch elements SW2 may simultaneously input bits of the Nth pixel line data stored in synchronization with the rising edge of the second CLAT signal CLAT2 to the DAC. In FIG. 14, LAT2 represents pixel line data stored in the second latch (LAT2). In Figure 14, DAC Input represents pixel line data input to the DAC.

A pulse of the second CLAT signal CLAT2 may be generated every horizontal period. The pulse of the second CLAT signal CLAT2 may be generated in the horizontal blank section (HB) or the horizontal active section (HA). The timing controller 130 transmits timing information of the second CLAT signal CLAT2, which is individually set for each source drive IC, to the source drive ICs SIC1 to SICn. Accordingly, the source drive ICs (SIC1 to SICm) may generate a second CLAT signal (CLAT2) with a delay time difference between the ICs.

The delay time of the second CLAT signal CLAT2 is individually set for each source drive IC as shown in FIG. 15, so that the output delay time of the second latch LAT2 can be controlled differently between the source drive ICs SIC1 to SICn. Accordingly, the second CLAT signal CLAT2 may be individually supplied to each of the source drive ICs SIC1 to SICm.

The DAC generates a data voltage by converting pixel data input from the second latch (LAT2) into a gamma compensation voltage. A capacitor C may be connected to each of the wires between the output nodes of the second latch LAT2 and the input nodes of the DAC. The capacitor (C) may be connected between the wiring and ground (GND). The capacitor (C) can prevent the pixel data value input to the DAC from changing by suppressing leakage current on the wiring.

The output buffer (BUF) may be connected between the DAC and the data lines (DL). The output buffer BUF may include third switch elements SW3 that supply data voltage to the data lines DL in response to pulses of the SOE signal. The third switch elements SW3 may output a data voltage in synchronization with the falling edge of the SOE signal.

A pulse of the SOE signal is generated every horizontal period. The SOE pulse may be generated in the horizontal active period (HA) as shown in FIG. 11.

In FIGS. 14 and 15, Output DATA is the data voltage of pixel line data output from the output buffer (BUF).

Figure 15 is a diagram showing an example of a CLAT signal that is individually controlled for each source drive IC.

Referring to FIG. 25, a common first CLAT signal (CLAT1) with no delay time difference for each IC may be supplied to the source drive ICs (SIC1 to SICn).

The second CLAT signal CLAT2 may be set to a different delay time for each IC depending on the wiring length between the timing controller 130 and the source drive ICs SIC1 to SICn. The second CLAT signal (CLAT2) may be individually transmitted to the source drive ICs (SIC1 to SICn).

Timing information of the first and second CLAT signals (CLAT1, CLAT2) and the SOE signal may be coded in a control packet and transmitted to the source drive ICs (SIC1 to SICn).

The longer the wiring length between the timing controller 130 and the source drive ICs (SIC1 to SICn), the greater the RC delay. In the example of FIG. 15, the wiring length between the timing controller 130 and the first and nth source drive ICs (SIC1 and SICn) is the longest. The wiring length between the timing controller 130 and the mth source drive IC (SICm) is the shortest. As the distance from the upper center of the display panel 100 increases, the length between the timing controller 130 and the source drive ICs (SIC1 to SICn) becomes longer. In order to reduce the variation in the charging rate of pixels due to the difference in RC delay, the delay amount of the second CLAT signal (CLAT2) is inversely proportional to the wire length based on the first and nth source drive ICs (SIC1, SICn) with the largest RC delay. do. For example, based on the second CLAT signal (CLAT1, CLATn) input to the first and n-th source drive ICs (SIC1, SICn), the second and n-1th source drive ICs (SIC2 , while the amount of delay of the second CLAT signal (CLAT2) input to the mth source drive IC (SICm) can be set to be the largest. there is.

A display device according to various embodiments of the present invention can be described as follows.

Embodiment 1: A display device includes a plurality of source drive ICs each including a first latch, a second latch, and a digital-to-analog converter connected between a shift register and an output buffer; and a timing controller connected to each of the source drive ICs through separate wires for each IC.

The timing controller transmits control data including timing information of the first latch output control signal, the second latch control signal, and the source output enable signal to the source drive ICs, and then sends pixel data to the source drive through the wires. It can be transmitted to ICs.

The first latch may output stored pixel data in response to the first latch output control signal and supply it to the second latch. The second latch may supply stored pixel data to the digital-analog converter in response to the second latch output control signal. The output buffer may output a data voltage from the digital-analog converter in response to the source output enable signal.

Example 2: The pulse of the first latch output control signal may be generated without a delay time difference between the source drive ICs.

Example 3: Pulses of the second latch output control signal may be delayed between the source drive ICs.

Example 4: The amount of delay of the second latch output control signal may be inversely proportional to the wiring length between the timing controller and the source drive IC.

Example 5: Each of the source drive ICs can restore an internal clock using clock information input from the timing controller.

Embodiment 6: Each of the source drive ICs may further include a shift register for sampling pixel data received from the timing controller at the internal clock timing and sequentially supplying the sample to the first latch.

Embodiment 7: The first latch may include a plurality of first switch elements that output stored pixel data to the second latch in synchronization with a rising edge of the first latch output signal.

Embodiment 8: The second latch may include a plurality of second switch elements that output stored pixel data to the digital-analog converter in synchronization with the rising edge of the second latch output signal.

Embodiment 9: The output buffer may include a plurality of third switch elements that output the data voltage to data lines of the display panel in synchronization with the falling edge of the source output enable signal.

Embodiment 10: Each of the source drive ICs may further include a plurality of capacitors connected to each of the wires between the output nodes of the second latch and the digital-to-analog converter.

Example 11: Pulses of the first latch output signal, the second latch output signal, and the source output enable signal may be generated every horizontal period.

Example 12: One horizontal period may include a horizontal blank period in which the control data is transmitted to the source drive ICs and a horizontal active period in which the pixel data is transmitted to the source drive ICs.

A pulse of the first latch output signal may be generated in the horizontal blank section.

Example 13: A pulse of the source output enable signal may be generated in the horizontal active period.

Example 14: A pulse of the second latch output control signal may be generated in the horizontal blank period or the horizontal active period.

Embodiment 15: A display device transmits control data including timing information of a first latch output control signal, a second latch control signal, and a source output enable signal to the first and second source drive ICs, and selects a first pixel It may include a timing controller that transmits a data packet to the first source drive IC and simultaneously transmits a second pixel data packet to the second source drive IC.

Each of the first and second source drive ICs may include a first latch, a second latch, and a digital-to-analog converter connected between a shift register and an output buffer.

The first latch may output stored pixel data in response to the first latch output control signal and supply it to the second latch. The second latch may supply stored pixel data to the digital-analog converter in response to the second latch output control signal. The output buffer may output a data voltage from the digital-analog converter in response to the source output enable signal.

The data voltage output timing of the first source drive IC and the data voltage output timing of the second source drive IC may be different from each other.

Embodiment 16: A pulse of the first latch output control signal may be generated without a delay time difference between the first and second source drive ICs.

Example 17: Pulses of the second latch output control signal may be delayed between the first and second source drive ICs.

Embodiment 18: The amount of delay of the second latch output control signal may be inversely proportional to the wiring length between the timing controller and the first and second source drive ICs.

Embodiment 19: A display device transmits control data including timing information of a latch output control signal and a source output enable signal to first and second source drive ICs, and sends a first pixel data packet to the first source drive IC. It may include a timing controller that simultaneously transmits the second pixel data packet to the second source drive IC.

Each of the first and second source drive ICs includes a latch that outputs stored data to a digital-to-analog converter in response to the latch output control signal; and an output buffer that outputs a data voltage from the digital-to-analog converter in response to the source output enable signal.

The data voltage output timing of the first source drive IC and the data voltage output timing of the second source drive IC may be different from each other.

Embodiment 20: The amount of delay of the latch output control signal may be inversely proportional to the wiring length between the timing controller and the first and second source drive ICs.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

130: timing controller 110: data driver
SIC1~SICn: Source drive IC CLAT: Latch output control signal
SOE: Source output enable signal

Claims (20)

A plurality of source drive ICs each including a first latch, a second latch, and a digital-to-analog converter connected between the shift register and the output buffer; and
Includes a timing controller connected to each of the source drive ICs through wires differentiated for each IC,
The timing controller is,
A first latch output control signal and a second latch output control signal that control the output timing of each of the source drive ICs, and a source output that controls the output timing of the first latch and the second latch in each of the source drive ICs. Generate control data packets including an enable signal and transmit them to the source drive ICs, then transmit pixel data to the source drive ICs through the wires,
The first latch is,
outputting pixel data stored in the first latch and supplying it to the second latch in response to the first latch output control signal included in the control data packet;
The second latch is,
Supplying pixel data stored in the second latch to the digital-analog converter in response to the second latch output control signal included in the control data packet,
The output buffer is,
Outputting a data voltage from the digital-to-analog converter in response to the source output enable signal included in the control data packet,
A pulse of the second latch output control signal is delayed between the source drive ICs,
A display device wherein the amount of delay of the second latch output control signal is inversely proportional to the wiring length between the timing controller and the source drive IC. According to claim 1,
The pulse of the first latch output control signal is,
A display device generated without delay time between the source drive ICs. delete delete According to claim 1,
Each of the source drive ICs,
A display device that restores an internal clock using clock information input from the timing controller. According to claim 5,
Each of the source drive ICs,
The display device further includes a shift register that samples pixel data received from the timing controller at the internal clock timing and sequentially supplies the sample to the first latch. According to claim 1,
The first latch is,
A display device comprising a plurality of first switch elements that output pixel data stored in the first latch to the second latch in synchronization with a rising edge of the first latch output control signal. According to claim 7,
The second latch is,
A display device comprising a plurality of second switch elements that output pixel data stored in the second latch to the digital-analog converter in synchronization with a rising edge of the second latch output control signal. According to claim 8,
The output buffer is,
A display device comprising a plurality of third switch elements that output the data voltage to data lines of a display panel in synchronization with a falling edge of the source output enable signal. According to clause 9,
Each of the source drive ICs,
The display device further includes a plurality of capacitors connected to each of the wires between the output nodes of the second latch and the digital-to-analog converter. According to claim 1,
A display device in which pulses of the first latch output control signal, the second latch output control signal, and the source output enable signal are generated every horizontal period. According to claim 11,
1 horizontal period includes a horizontal blank period in which the control data is transmitted to the source drive ICs, and a horizontal active period in which the pixel data is transmitted to the source drive ICs,
A display device in which a pulse of the first latch output control signal is generated in the horizontal blank section. According to claim 12,
A display device in which a pulse of the source output enable signal is generated in the horizontal active period. According to claim 13,
A display device in which a pulse of the second latch output control signal is generated in the horizontal blank period or the horizontal active period. A first latch output control signal and a second latch output control signal that control the output timing of each of the first and second source drive ICs, and a signal of the first latch and the second latch in each of the first and second source drive ICs. Control data packets including a source output enable signal for controlling output timing are transmitted to the first and second source drive ICs, and a first pixel data packet is transmitted to the first source drive IC while simultaneously transmitting a second pixel data packet to the first source drive IC. A timing controller transmitting data packets to the second source drive IC,
Each of the first and second source drive ICs,
each comprising a first latch, a second latch, and a digital-to-analog converter connected between the shift register and the output buffer;
The first latch is,
outputting pixel data stored in the first latch and supplying it to the second latch in response to the first latch output control signal included in the control data packet;
The second latch is,
Supplying pixel data stored in the second latch to the digital-analog converter in response to the second latch output control signal included in the control data packet,
The output buffer is,
Outputting a data voltage from the digital-to-analog converter in response to the source output enable signal included in the control data packet,
The data voltage output timing of the first source drive IC and the data voltage output timing of the second source drive IC are different from each other,
A pulse of the second latch output control signal is delayed between the source drive ICs,
A display device wherein the amount of delay of the second latch output control signal is inversely proportional to the wiring length between the timing controller and the source drive IC. According to claim 15,
The pulse of the first latch output control signal is,
A display device generated without a delay time difference between the first and second source drive ICs. delete delete delete delete