KR101696458B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and a timing controller of the liquid crystal display device transmits digital video data to source drive ICs on a IC-by-IC basis through a plurality of data wire pairs. The source control data includes source start information defining a pulse rising time of the source output enable signal, and pulse width information defining a pulse duration of the source output enable signal. The start information transmitted to one of the source drive ICs and the start information transmitted to the other one of the source drive ICs are different from each other. Each of the source drive ICs generates a source output enable signal based on start information and pulse width information of individually received source control data.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is rapidly applied to a television, thereby rapidly replacing a cathode ray tube.

The liquid crystal display device includes a plurality of source drive integrated circuits (hereinafter referred to as "IC") for supplying data voltages to the data lines of the liquid crystal display panel, gate pulses (or scan pulses ), And a timing controller for controlling the drive ICs, and the like. The timing controller supplies digital video data, a clock signal for sampling digital video data, a control signal for controlling the operation of the source drive ICs, and the like to the source drive ICs through an interface such as mini LVDS (Low Voltage Differential Signaling) do. The source driver ICs convert the digital video data serially inputted from the timing controller into a parallel system, and then convert the analog data voltage using the gamma compensation voltage and supply the analog data voltage to the data lines.

The timing controller supplies the necessary signals to the source drive ICs in a multi-drop scheme that applies clock and digital video data commonly to the source drive ICs. This data transfer scheme includes control wirings for controlling the R data transfer wiring, the G data transfer wiring, the B data transfer wiring, the output of the source drive ICs, and the operation timing of the polarity change operation between the timing controller and the source drive ICs, Clock transmission wiring, and so on.

For example, the mini-LVDS interface method of transmitting RGB data in a mini-LVDS interface system transmits RGB digital video data and a clock in a differential signal pair, so that when transmitting odd data and excellent data simultaneously, At least 14 wires are required between the controller and the source drive ICs for RGB data transfer. If the RGB data is 10-bit data, 18 wires are required. Therefore, it is difficult to reduce the width of the printed circuit board (PCB) disposed between the timing controller and the source drive ICs because many wirings must be formed thereon.

According to the trend of high resolution and high image quality of the liquid crystal display device, the source drive ICs output a large amount of data at the same time, resulting in a lot of electromagnetic interference (EMI). In order to reduce the EMI, there is a method of distributing the operation timing of the source drive ICs by installing an EMI abatement circuit for delaying the control signals for controlling the source drive ICs on the PCB. However, this method is required to install an EMI reduction circuit on the PCB, which not only increases the cost, but also makes it difficult to design a slim PCB. In addition, since the EMI reduction circuit can not adjust the delay value of the delay circuit, it has to be redesigned when the application model is changed, so that the compatibility is deteriorated.

The present invention provides a liquid crystal display device and a method of driving the same that minimizes signal transmission lines between the timing controller and the source drive ICs and reduces EMI.

As one aspect of the present invention, the liquid crystal display of the present invention includes source drive ICs and a timing controller for controlling the source drive ICs. Each of the source drive ICs generates a source output enable signal based on start information and pulse width information of the source control data received individually. The start information defines a pulse rising point of the source output enable signal. The pulse width information defines source start information, a pulse duration of the source output enable signal.
The start information transmitted to one of the source drive ICs and the start information transmitted to the other one of the source drive ICs are different from each other.

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The present invention can reduce the EMI by coding the start information and the pulse width information of the source output enable signal differently for each source drive IC to distribute the output timing of each source drive IC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The component names used in the following description are selected in consideration of easiness of specification, and may be different from the parts names of actual products.

1 and 2, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel 10, a timing controller TCON, source drive ICs (SDIC # 1 to SDIC # 8) ICs (GDIC # 1 to GDIC # 4).

A liquid crystal layer is formed between the glass substrates of the liquid crystal display panel 10. The liquid crystal display panel 10 includes m x n liquid crystal cells Clc arranged in a matrix form by an intersection structure of m data lines DL and n gate lines GL.

A pixel array including data lines DL, gate lines GL, TFTs, and a storage capacitor Cst is formed on a lower glass substrate of the liquid crystal display panel 10. [ The liquid crystal cells Clc are driven by the electric field between the pixel electrode to which the data voltage is supplied through the TFT and the common electrode to which the common voltage Vcom is supplied. The gate electrode of the TFT is connected to the gate line GL, and the drain electrode thereof is connected to the data line DL. The source electrode of the TFT is connected to the pixel electrode of the liquid crystal cell. The TFT is turned on according to the gate pulse supplied through the gate line GL to supply the positive / negative analog video data voltage from the data line DL to the pixel electrode of the liquid crystal cell Clc.

On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, a common electrode, and the like are formed.

The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode in the driving method.

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed. A spacer for maintaining a cell gap of the liquid crystal cell Clc is formed between the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10. [

The liquid crystal display of the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. Further, the liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device, and the like. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller TCON receives vertical / horizontal synchronizing signals Vsync and Hsync, an external data enable signal, and the like through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a TMDS (Transition Minimized Differential Signaling) (Data Enable, DE), and a dot clock (CLK).

The timing controller TCON supplies the source drive ICs (SDIC # 1 to SDIC # 8) 1: 1, that is, in a point-to-point manner, to the source drive ICs (SDIC # 1 to SDIC # # 8) in series. The timing controller TCON outputs a differential signal pair such as a preamble signal for initializing the source drive ICs (SDIC # 1 to SDIC # 8), a source control data packet, an external clock signal, and an RGB digital video data packet To one or more source drive ICs (SDIC # 1 to SDIC # 8) through a data wire pair (DATA & CLK). The external clock signal may be serially transferred from the timing controller TCON to the source drive ICs (SDIC # 1 to SDIC # 8) via a separate clock wiring pair. The frequency of the external clock signal is as low as 1 / N (N is the number of bits of RGB digital video data). For example, if the RGB digital video data is 10 bits, the frequency of the clock signal is 1/10 of the RGB data transmission frequency. The source control data packet is a bit stream including clock bits, control data bits related to polarity control, and control data related to source output. The source control data packet may include gate control data for controlling the gate drive IC. The RGB data packet is a bit stream including a clock bit, an internal data enable bit, and an RGB data bit. The timing controller TCON generates gate control signals for controlling the operation timings of the gate drive ICs (GDIC # 1 to GDIC # 4) using an external timing signal, and supplies gate control signals to the gate drive IC (GDIC # 1 to GDIC # 4).

The timing controller TCON may be connected to the first and eighth source driver ICs (SDIC # 1 and SDIC # 8) via the lock check line LCS1. The timing controller TCON outputs a lock signal for checking whether the output of the internal clock generated in the source drive ICs (SDIC # 1 to SDIC # 8) is stable, through a lock check wiring (LCS1) And supplies it to the IC (SDIC # 1). The source drive ICs (SDIC # 1 to SDIC # 8) can be cascade-connected via a wire (dotted line) for transferring a lock signal (Lock). When the frequency and phase of the internal clock for data sampling are fixed, the first source drive IC (SDIC # 1) transfers the high logic lock signal to the second source drive IC (SDIC # 2) SDIC # 2 fixes the frequency and phase of the internal clock, and then transfers the high logic lock signal to the third source drive IC (SDIC # 3). In this way, if the clock output frequency and phase of the source drive ICs (SDIC # 1 to SDIC # 8) are fixed and then the clock output frequency and phase of the last source drive IC (SDIC # 8) are fixed, (SDIC # 8) feeds back the high logic lock signal to the timing controller TCON through the feedback lock check wiring LCS2. The timing controller TCON starts transmitting the source control data packet and the RGB data packet to the source drive ICs (SDIC # 1 to SDIC # 8) after receiving the feedback input of the lock signal (Lock).

The timing controller TCON controls the chip identification code CID of the source drive ICs SDIC # 1 to SDIC # 8 and the chip individual control data SDIC # 1 to SDIC # 8 for controlling the functions of the source drive ICs SDIC # To the source drive ICs (SDIC # 1 to SDIC # 8) through the control wiring pair (SCL / SDA1, SCL / SDA2). The control wiring pair SCL / SDA1 and SCL / SDA2 can be connected in common between the timing controller TCON and the source drive ICs SDIC # 1 to SDIC # 8.

The source drive ICs (SDIC # 1 to SDIC # 8) are connected to the timing controller (TCON) in a point-to-point fashion via a data wire pair (DATA & CLK). Each of the source drive ICs (SDIC # 1 to SDIC # 8) can be connected to the data lines of the liquid crystal display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The source drive ICs (SDIC # 1 to SDIC # 8) receive a preamble signal, a source control data packet, a clock signal, an RGB digital video data packet, and the like through a data wire pair (DATA & CLK). The source drive ICs (SDIC # 1 to SDIC # 8) generate the number of bits of RGB digital video data × 2 internal clocks by using a clock recovery circuit that restores and multiplies the external clock signal input from the timing controller (TCON) And samples the RGB digital video data according to the internal clock signal and converts it into a parallel data system. The clock recovery circuit may include a phase locked loop (PLL) or a delay locked loop (DLL). The source drive ICs (SDIC # 1 to SDIC # 8) restore the source control data input via the data wire pair (DATA & CLK). The source drive ICs (SDIC # 1 to SDIC # 8) convert the RGB digital video data converted into the parallel system according to the source control data into positive / negative analog data voltages and supply them to the data lines. If the source control data packet input from the timing controller TCON contains gate control data, the source drive ICs (SDIC # 1 to SDIC # 8) restore the gate control data in the source control data packet to the gate drive IC GDIC # 1 to GDIC # 4).

Each of the source drive ICs (SDIC # 1 to SDIC # 8) restores the clocks input through the data wire pair (DATA & CLK) to generate an internal clock signal. Therefore, wiring between the source drive ICs (SDIC # 1 to SDIC # 8) and the clock carry and RGB data is not required. The source control data packet is transmitted through the data line pair (DATA & CLK) connected between the timing controller TCON and the source drive ICs (SDIC # 1 to SDIC # 8), so that the timing controller TCON and the source drive ICs SDIC # There is no need for a wiring for transmitting a source control signal such as a polarity control signal POL and a source output enable signal SOE between the control signal lines SD1 to SDIC # 8. The polarity control signal POL is a control signal for controlling the polarity of the data voltage output from the source drive ICs (SDIC # 1 to SDIC # 8). The source output enable signal SOE is a control signal for controlling the output timings of the source drive ICs (SDIC # 1 to SDIC # 8).

Korean Patent Application No. 10-2008-0127458 (2008.12.15), Korean Patent Application No. 10-2008-0127456 (December 15, 2008), Korean Patent Application No. 10-2008-0132466 (2008.12 Korean Patent Application No. 10-2008-0132479 (December 23, 2008), Korean Patent Application No. 10-2008-0132493 (December 23, 2008), Korean Patent Application No. 10-2009-0047672 (2009.05.29 12 / 533,996 (2009.08.19), United States Patent Application 12 / 461,652 (2009.08.19), United States Patent Application 12 / 537,341 (2009.08.07), United States Patent Application 12 / A signal transmission protocol between a timing controller (TCON) and a source drive ICs (SDIC # 1 to SDIC # 8) based on a point-to-point system has been described in detail.

The gate drive ICs (GDIC # 1 to GDIC # 4) are connected to the gate lines of the lower glass substrate of the liquid crystal display panel 10 through a TAP process, or connected to gate lines of the lower glass substrate of the liquid crystal display panel 10 by a GIP (Gate In Panel) Can be formed directly on the glass substrate. The gate drive ICs GDIC # 1 to GDIC # 4 receive gate pulses from the timing controller TCON or gate lines according to gate control data supplied through the source drive ICs (SDIC # 1 to SDIC # 8) (GL). The gate control data includes a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and the like. The gate start pulse (GSP) controls the start horizontal line at which the scan starts from one vertical period in which one screen is displayed. The gate shift clock signal GSC is a clock signal that is input to a shift register in the gate drive ICs GDIC # 1 to GDIC # 4 to sequentially shift the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive ICs (GDIC # 1 to GDIC # 4).

3 is a block diagram showing an internal circuit configuration of the source drive ICs (SDIC # 1 to SDIC # 8).

Referring to FIG. 3, each of the source drive ICs (SDIC # 1 to SDIC # 8) includes positive and negative polarity data voltages for k (k is a positive integer smaller than m) data lines D1 to Dk Supply.

Each of the source drive ICs (SDIC # 1 to SDIC # 8) includes a data sampling and deserializer 21, a digital to analog converter (DAC) 22 and an output circuit 23, and the like.

The data sampling and serial-to-parallel converter 21 generates internal clock signals using a PLL or a DLL, samples and latches RGB digital video data serially input through a pair of data lines according to the internal clock signals, Data.

The data sampling and serial / parallel conversion unit 21 restores the control data input through the data wire pair (DATA & CLK) by a code mapping method to generate source control data. Also, when the gate control data is encoded in the control data, the data sampling and serial / parallel conversion unit 21 restores the gate control data from the control data input through the pair of data lines and transmits it to the gate drive IC (GIC) . The source control data includes a source output enable signal SOE, a polarity control signal POL, and the like.

The DAC 22 converts the RGB digital video data from the data sampling and serial-to-parallel conversion unit 21 into a positive gamma compensation voltage GH and a negative gamma compensation voltage GL in response to the polarity control signal POL Thereby generating a positive / negative analog video data voltage.

The output circuit 23 performs charge sharing on the data voltages supplied through the neighboring data lines during the high logic period of the source output enable signal SOE or charges the common voltage Vcom to the data lines (D1 to Dk). The output circuit 23 supplies the positive / negative analog video data voltages to the data lines D1 to Dk through the output buffer during the low logic period of the source output enable signal SOE. The charge sharing voltage is generated when a data line to which a positive voltage is supplied and a data line to which a negative voltage is supplied are short-circuited, and has an average voltage level of the positive voltage and the negative voltage.

4 is a diagram showing an example of data transferred from the timing controller TCON to the source drive ICs (SDIC # 1 to SDIC # 8).

4, the timing controller TCON transmits the preamble signals to the source drive ICs (SDIC # 1 to SDIC # 8) in the first step (PI) to generate the source drive ICs (SDIC # 1 to SDIC # 8). ≪ / RTI > Subsequently, the timing controller TCON transfers the source control data packet to each of the source drive ICs (SDIC # 1 to SDIC # 8) in the second step PII and then, in the third step (PIII) And transmits the video packet in series to each of the source drive ICs (SDIC # 1 to SDIC # 8).

The source control data packet includes control start information CTR_Start, SOE start information SOE_Width, first and second option control information CRT1 and CTR2, and the like.

The control start information (CTR_Start) is an identification code for indicating the start of the source control data packet, and is generated with a code value different from data start data (DATA START) indicating the start of the RGB digital video data. For example, the control start data (CTR_Start) is generated as '101010' as shown in FIG. 8, whereas the data start data (DATA Start) can be generated as '010101'.

The SOE start information (SOE_Start) defines the number of external clocks from the control start information (CTR_Start) to the pulse rising point of the source output enable signal (SOE). The source drive ICs (SDIC # 1 to SDIC # 8) increase the pulse of the source output enable signal at the point of time when the SOE start information (SOE_Start) × external or internal clock time elapses. The delay value until the pulse of the source output enable signal SOE starts to rise is proportional to the value of the SOE start information (SOE_Start). Therefore, the pulse rising time of the source output enable signal SOE can be adjusted according to the SOE start information (SOE_Start) value.

The SOE width information defines a high logic duration (or a high logic duration) in the pulse of the source output enable signal (SOE). The control data mapping unit 46 outputs a pulse of the source output enable signal SOE until the time point after the rising time of the source output enable signal SOE by the SOE width information x SOE Width x external or internal clock time High logic and then inverted to low logic. That is, the high logic duration of the source output enable signal SOE is proportional to the value of the SOE width information (SOE Width). Thus, the high logic duration of the source output enable signal SOE is adjustable according to the SOE width value.

The first and second option control data CRT1 and CTR2 may include control information necessary for controlling the source drive ICs (SDIC # 1 to SDIC # 8) in addition to the source output enable signal SOE. The first and second option control data CRT1 and CTR2 include a polarity control signal POL, a charge share mode on / off, a horizontal polarity reversal period H2DOT, a source drive ICs SDIC # The output power of the source drive ICs (SDIC # 1 to SDIC # 8), the channel selection of the source drive ICs (SDIC # 1 to SDIC # 8), the gate start pulse (GSP) And source control data and gate control data can be defined. The rising time, the pulse width, etc. of the source output enable signal SOE may be changed or turned on / off every horizontal period for improving picture quality.

In order to reduce EMI, the present invention distributes the output timing of each of the source drive ICs (SDIC # 1 to SDIC # 8) by coding the SOE start information (SOE_Start) with a different value for each source drive IC. Also, according to the present invention, the SOE width information (SOE Width) can be coded with different values for each source drive IC, and the output duration of data output from the source drive ICs (SDIC # 1 to SDIC # 8) can be adjusted differently. For example, according to the present invention, the SOE start information (SOE_Start) and the SOE width information (SOE Width) of the first source drive ICs (SDIC # 1) are denoted by S1 and W1, respectively, The SOE start information (SOE_Start) and the SOE width information (SOE Width) of the ICs (SDIC # 2) are set to S2 and W2, respectively, and the SOE start information SOE_Start) and the SOE width information (SOE Width) to 'S8' and 'W8', respectively. The larger the value of the SOE start information (SOE_Start), the slower the rising time of the source output enable signal, and the higher the SOE width information (SOE Width), the longer the high logic duration of the source output enable signal. The SOE start information (SOE_Start) and the SOE width information (SOE Width) can be adjusted according to the driving characteristic of the liquid crystal display and the EMI measurement result.

5 to 8 show examples in which the output timings of the source drive ICs (SDIC # 1 to SDIC # 8) are distributed by setting the SOE start information (SOE_Start) and the SOE width information (SOE Width) They are waveform diagrams.

5 to 7, the SOE start information (SOE_Start) and the SOE width information (SOE width) may be set to different values in each of the source drive ICs (SDIC # 1 to SDIC # 8).

For example, if the value of the SOE start information (SOE_Start) of the first source drive IC (SDIC # 1) is set to be the smallest and the values of the SOE start information (SOE_Start) set to the eighth source drive IC (SDIC # 8) , The source output enable signals (SOE_SDIS # 1 to SOE_SDIC # 8) of the source drive ICs (SDIC # 1 to SDIC # 8) are sequentially delayed as shown in FIG.

The SOE start information (SOE_Start) value of the first source drive IC (SDIC # 1) is set to be the smallest and the values of the fifth source drive IC (SDIC # 5), the second source drive IC (SDIC # (SDIC # 6), a third source drive IC (SDIC # 3), a seventh source drive IC (SDIC # 7), a fourth source drive IC (SDIC # (SOE_SDIS # 1 to SOE_SDIC # 8) of the source drive ICs (SDIC # 1 to SDIC # 8) as shown in FIG. 6 when the SOE start information (SOE_Start) The first source output enable signal SOE_SDIS # 1, the fourth source output enable signal SOE_SDIS # 4, the second source output enable signal SOE_SDIS # 2, the fifth source output enable signal SOE_SDIS # 5, a third source output enable signal SOE_SDIS # 3, a sixth source output enable signal SOE_SDIS # 6, a fourth source output enable signal SOE_SDIS # 5, an eighth source output enable signal SOE_SDIS # 8) .

The SOE start information (SOE_Start) value of the fourth source drive IC (SDIC # 4) is set to be the smallest and the fifth source drive IC (SDIC # 5), the third source drive IC (SDIC # (SDIC # 6), a second source drive IC (SDIC # 2), a seventh source drive IC (SDIC # 7), a second source drive IC (SDIC # When the SOE start information (SOE_Start) value is gradually increased in the order of the first source drive IC (SDIC # 1), the source output enable signals (SDIC # 1 to SDIC # 8) of the source drive ICs SOE_SDIS # 1 to SOE_SDIC # 8 are the fourth source output enable signal SOE_SDIS # 4, the fifth source output enable signal SOE_SDIS # 5, the third source output enable signal SOE_SDIS # 3, A sixth source output enable signal SOE_SDIS # 6, a second source output enable signal SOE_SDIS # 2, an eighth source output enable signal SOE_SDIS # 8, a first source output enable signal SOE_SDIS # 1) It grows.

Referring to FIG. 8, SOE start information (SOE_Start) and SOE width information (SOE width) may be set to different values for each source drive IC group. The source drive IC group includes two or more source drive ICs to which the source output enable signal SOE having the same delay value is supplied.

For example, the SOE start information (SOE_Start) value of the fourth and fifth source drive ICs (SDIC # 4 and SDIC # 5) is set to be the smallest and the third and sixth source drive ICs (SDIC # (SOE_Start) value (SOE_Start) in the order of the first and the second source drive ICs (SDIC # 2, SDIC # 3, SDIC # The delay values of the source output enable signals SOE_SDIS # 1 to SOE_SDIC # 8 of the scan drive ICs SDIC # 1 to SDIC # 8 are set to the fourth and fifth source output enable signals SOE_SDIS # 4 and SOE_SDIS # 5), the third and sixth source output enable signals SOE_SDIS # 3 and SOE_SDIS # 6, the second and seventh source output enable signals SOE_SDIS # 1 and the eighth source output enable signals SOE_SDIS # 1 and SOE_SDIS # 8.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a block diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a detailed view showing the wiring between the timing controller and the source drive ICs shown in FIG.

3 is a block diagram showing the internal structure of the source drive IC shown in FIG.

4 is a diagram showing an example of data transferred from the timing controller to the source drive ICs.

5 to 8 are waveform diagrams showing examples in which SOE start information and SOE width information are set differently for each source drive IC to distribute output timings of the source drive ICs.

Description of the Related Art

TCON: Timing controller SDIC # 1 to SDIC # 8: Source drive IC

GDIC # 1 to GDIC # 4: Gate drive IC

Claims (7)

1. A liquid crystal display comprising a plurality of source drive ICs and a timing controller for controlling the source drive ICs, The timing controller includes: Transferring source control data to each of the source drive ICs through a plurality of data wire pairs, Each of the source drive ICs generates a source output enable signal based on start information and pulse width information of the source control data received individually, Wherein the start information defines a pulse rising time of the source output enable signal, the pulse width information defines source start information, a pulse duration of the source output enable signal, Wherein the start information transmitted to one of the source drive ICs and the start information transmitted to the other one of the source drive ICs are different from each other. The method according to claim 1, One of the plurality of source drive ICs is referred to as a first source drive IC and the other of the plurality of source drive ICs is referred to as a second source drive IC, The timing controller First source control data including first start information and first pulse width information to the first source drive IC and second source control data including second start information and second pulse width information to the second source Drive IC, The first source drive IC includes: Generating a first source output enable signal based on the first start information and the first pulse width information of the first source control data received from the timing controller and generating a first source output enable signal based on the first source output enable signal, And outputs the data voltage generated in the source drive IC to the data lines connected to the first source drive IC, The second source drive IC, Generating the second source output enable signal based on second start information and second pulse width information of the second source control data received from the timing controller and outputting the second source output enable signal based on the second source output enable signal, 2 data lines generated in the source drive IC to the data lines connected to the second source drive IC, Wherein the first start information and the second start information are coded with different values so that the rising time of the first source output enable signal and the rising time of the second source output enable signal are different from each other. Device. The method according to claim 1, And the delay time of the rising time of the source output enable signal is proportional to the value of the start information. 3. The method of claim 2, Wherein the first pulse width information and the second pulse width information have different values. 5. The method of claim 4, Wherein the high logic duration of the source output enable signal is proportional to the value of the pulse width information. 3. The method of claim 2, Wherein the first source control data includes a first polarity control signal for controlling a polarity of a data voltage output from the first source drive IC, And the second source control data includes a second polarity control signal for controlling a polarity of a data voltage output from the second source drive IC. The method according to claim 6, The first source drive IC includes: And a polarity control circuit for selecting the polarity of the data voltage to be supplied to the data line of the liquid crystal display panel according to the first polarity control signal, The second source drive IC, Wherein the second polarity control signal is restored from the second source control data and the polarity of the data voltage to be supplied to the data line of the liquid crystal display panel is selected according to the second polarity control signal.

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