KR101263532B1 - Liquid crystal dusplay device and method driving for the same - Google Patents

Abstract

The present invention discloses a liquid crystal display device and a driving method thereof capable of displaying a large number of gray levels and improving image quality.

The liquid crystal display according to the present invention includes a liquid crystal panel, a gate and data driver for driving the liquid crystal panel, a timing controller for supplying j bits of R, G, and B data to the data driver, and the timing controller and the data driver. And m transmission lines formed therebetween, wherein the m transmission lines have a relationship of (3 + α) n.

R, G, B data, 10-bit, driver IC

Description

Liquid crystal display device and method for driving the same {Liquid crystal dusplay device and method driving for the same}

1 is a view showing a conventional liquid crystal display device.

2 shows a data structure supplied to the timing controller of FIG.

3 illustrates an ordered 8-bit data format supplied to the data driver IC of FIG.

4 is a view showing a liquid crystal display device according to the present invention.

FIG. 5 illustrates a 10-bit data format supplied to the timing controller of FIG. 4. FIG.

FIG. 6 shows a 10-bit data format supplied to the data driver IC of FIG. 4; FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

102: liquid crystal panel 104: gate driver IC

106: Date driver IC

108a, 108b: first and second data PCB

110: timing controller 112: control signal generator

114a: first data alignment unit 114b: second data alignment unit

116: system

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for outputting 10-bit real data by aligning input 10-bit data.

As the information society develops, the demand for display devices is increasing in various forms. In response to this, various flat panel display devices such as LCD (Liquid Crystal Display Device), PDP (Plasma Display Panel) and ELD (Electro Luminescent Display) have been studied. It is used as a display device.

Among them, liquid crystal displays are the most widely used, replacing CRTs for mobile image display devices because of their excellent image quality, light weight, thinness, and low power consumption. In addition to the mobile use, such as a variety of TV monitors have been developed.

1 is a view showing a conventional liquid crystal display device.

As shown in FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2 in which a predetermined image is displayed, a gate driver IC 4 for driving the liquid crystal panel 2, and first to fourth data. A driver controller 6a to 6d, a timing controller 10 for controlling the gate driver IC 4 and the first to fourth data driver ICs 6a to 6d, and the first to fourth data driver ICs. 6a to 6d and first and second data PCBs 8a and 8b for electrically connecting the timing controller 10.

The liquid crystal display further includes a system 16 for supplying data, clock signals, synchronization signals, and the like to the timing controller 10.

The system 16 supplies 8-bit R, G, and B data to the timing controller 10 in a Low Voltage Differential Signaling (LVDS) scheme.

The differential signal transmission method transmits desired data by using a voltage difference between two lines through which positive and negative signals having opposite polarities are transmitted, respectively. Even if the difference is low, the data can be easily recognized.

The system 16 supplies 8 bits of R, G, and B data to the timing controller 10 through the LVDS method through four pairs of connection lines.

The timing controller 10 generates a control signal generation unit 12 for generating a predetermined control signal using the vertical / horizontal synchronization signal Vsync / Hsync and the data enable signal DE supplied from the system 16. And first and second alignment portions 14a and 14b for aligning the R, G and B data supplied from the system 16.

The 8-bit R, G, and B data signals arranged in the first data alignment unit 14a are supplied to the first data PCB 8a through a six pair connection line, and the second data alignment unit 14b is provided. The 8-bit R, G, and B data signals arranged in Fig. 8) are supplied to the second data PCB 8b through six pairs of connection lines.

At this time, when the 8-bit R, G, and B data signals arranged in the timing controller 10 are supplied to the first and second data PCBs 8a and 8b, they are supplied using the mini-LVDS scheme.

FIG. 2 is a diagram illustrating a data structure supplied to the timing controller of FIG. 1.

As shown in FIGS. 1 and 2, the system 16 and the timing controller 10 are electrically connected through first to eighth connection lines Data1 to Data8. The first to eighth connection lines Data1 to Data8 mean connection lines of the four pairs.

The system 16 transmits 8-bit R, G, and B data signals and a first clock signal CLK-1 to the timing controller 10 through the first to eighth connection lines Data1 to Data8. It supplies a data enable (DE) signal and a vertical / horizontal sync signal (Vsync / Hsync).

The R, G, and B data signals supplied from the first to eighth connection lines Data1 to Data8 are data signals corresponding to two pixels of the liquid crystal panel 2. That is, the R, G, and B data signals supplied through the first to eighth connection lines Data1 to Data8 are data signals corresponding to the odd and even pixels of the liquid crystal panel 2, respectively.

The timing controller 10 recognizes the R, G, and B data, the data enable signal DE, and the vertical / horizontal synchronization signal Vsync / Hsync during a predetermined period of the first clock signal CLK-1.

The 8-bit R, G, and B data are supplied to the first and second data alignment units 14a and 14b to align 8-bit R data, 8-bit G data, and 8-bit B data, respectively. . The eight bits of data arranged in the first and second data alignment units 14a and 14b are supplied to the first and second data PCBs 8a and 8b, respectively.

Respective 8-bit R, G, and B data supplied to the first and second data PCBs 8a and 8b are respectively supplied to the first to fourth data driver ICs 6a to 6d.

FIG. 3 is a diagram illustrating an aligned 8-bit data format supplied to the data driver IC of FIG. 1.

As shown in FIGS. 1 to 3, 8 bits of R, G, and B data aligned in the first and second data alignment units 14a and 14b are respectively used for the first and second data PCBs 8a,. When supplied to the first to fourth data driver ICs 6a to 6d in 8b), it is supplied in a mini-LVDS manner. As mentioned above, the mini-LVDS transmits data in the same manner as the LVDS.

For convenience of description, only the 8-bit data format supplied to the first data PCB 8a and the first and second data driver ICs 6a and 6b electrically connected to the first data PCB 8a will be described. Shall be.

A total of six pairs of connection lines Data1 to Data12 exist between the first data PCB 8a and the first and second data driver ICs 6a and 6b.

Each of the 8-bit R, G, and B data is supplied to the first and second data driver ICs 6a and 6b through the six pairs of connection lines Data1 to Data12.

Each 8-bit R, G, and B data supplied through the six pairs of connection lines Data1 to Data12 are data values corresponding to two pixels of the liquid crystal panel 2.

The 8-bit R data signal of the first pixel of the liquid crystal panel 2 is supplied through the first and second connection lines Data1 and Data2 of the six pairs of connection lines Data1 to Data12. The 8-bit G data signal of the first pixel is supplied through third and fourth connection lines Data3 and Data4, and the 8-bit B of the first pixel is provided through fifth and sixth connection lines Data5 and Data6. The data signal is supplied.

The 8-bit R data signal of the second pixel of the liquid crystal panel 2 is supplied through the seventh and eighth connection lines Data7 and Data8. The 8-bit G data signal of the second pixel is supplied through the ninth and tenth connection lines Data9 and Data10, and the 8-bit B of the second pixel is provided through the eleventh and twelfth connection lines Data11 and Data12. The data signal is supplied.

As such, the 8-bit R, G, and B data signals corresponding to the first and second pixels of the liquid crystal panel 2 are connected to the first and second data PCBs 8a and 8b through the six pairs of connection lines. The first to fourth data driver ICs 6a to 6d are supplied through the first and fourth data driver ICs.

On the other hand, as the number of bits of data supplied to the data driver ICs 6a to 6d increases, more gray scales can be displayed.

As described above, the liquid crystal display aligns 8 bits of data input from the system 16 so that the first to fourth data driver ICs 6a to 6d correspond to the aligned 8 bits of data. Processing to output a data voltage.

When 10-bit data is input from the system 16 to display more gray levels than the 8-bit data, the 10-bit data is sorted unlike the method of sorting the input 8-bit data. New ways to do this are required.

The existing method of sorting 8-bit data corresponds to the case where 8-bit data is input from the system, and when the 10-bit data is input from the system, a method of sorting the 10-bit data should be newly studied.

An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of processing 10-bit R, G, and B data without increasing the driving clock.

The liquid crystal display device according to the present invention for achieving the above object is a liquid crystal panel, a gate and data driver for driving the liquid crystal panel, a timing controller for supplying j bits of R, G, B data to the data driver and the And m transmission lines formed between the timing controller and the data driver, wherein the m transmission lines have a relationship of (3 + α) n.

A driving method of a liquid crystal display device according to the present invention for achieving the above object is a driving method of a liquid crystal display device comprising a liquid crystal panel, a gate driver and a data driver for driving the liquid crystal panel, j, R, G, Supplying B data, supplying the j, R, G, and B data to the data driver through m transmission lines, and supplying the j, R, G, and B data to the data driver. And displaying corresponding images, wherein the m transmission lines have a relationship of (3 + α) n.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

4 is a view showing a liquid crystal display device according to the present invention.

As shown in FIG. 4, the liquid crystal display according to the present invention includes a liquid crystal panel 102 in which a predetermined image is displayed, a gate driver IC 104 for driving the liquid crystal panel 102, and first to first to second liquid crystal displays. A fourth data driver IC 106a to 106d, a timing controller 110 that controls the gate driver IC 104 and the first to fourth data driver ICs 106a to 106d, and the first to fourth First and second data PCBs 108a and 108b electrically connecting the data driver ICs 106a to 106d and the timing controller 110.

The data signal supplied from the timing controller 108 to the first to fourth data driver ICs 106a to 106d is j bits, and the j bit data signal is provided through the m transmission lines. The data driver ICs 106a to 106d are supplied. J is greater than m.

The m transmission lines are formed with the following equation.

M denotes a transmission line, and 3 denotes R, G, and B data signals, that is, three types of data signals, and means the number of transmission lines through which the lower bits of the R, G, and B data signals are transmitted. Α denotes a transmission line through which upper bits of the R, G, and B data signals are transmitted, and α may be 1 or 2.

N means a pair of m which is the transmission line. N may be 2, 3, 4, or the like.

In an embodiment of the present invention, j is 10, m is 8, α is 1, and n is 2.

That is, the timing controller 110 supplies the 10-bit R, G, B, and data signals to the first to fourth data driver ICs 106a to 106d through eight transmission lines.

Based on this, it will be described an embodiment according to the present invention.

The liquid crystal display further includes a system 116 for supplying data, a clock signal, a synchronization signal, and the like to the timing controller 110.

A plurality of gate lines and a plurality of data lines (not shown) are arranged in the liquid crystal panel 102, and a thin film transistor TFT and a pixel electrode electrically connected to the thin film transistor TFT are formed at an intersection thereof. . The plurality of gate lines and the plurality of data lines define a plurality of pixels.

The liquid crystal panel 102 may include a first substrate having a plurality of pixels defined by the plurality of gate lines and a plurality of data lines, a second substrate having a color filter having red, green, and blue colors, It consists of a liquid crystal layer formed between the first and second substrates.

The gate driver IC 104 sequentially supplies a scan signal to the plurality of gate lines according to a gate control signal supplied from the timing controller 110. The gate line is electrically connected to the thin film transistor TFT. When the scan signal is supplied to the gate line, the thin film transistor TFT is turned on.

The first to fourth data driver ICs 106a to 106d convert the 10-bit R, G, and B data signals supplied from the timing controller 110 into analog voltages using a digital-to-analog converter to convert the plurality of data signals. Supply to the data line.

The timing controller 110 uses the vertical / horizontal synchronization signal Vsync / Hsync, the data enable signal DE, and the predetermined clock signal CLK supplied from the system 116. And gate and data control signals for controlling the first to fourth data driver ICs 106a to 106d.

In addition, the timing controller 110 properly aligns the R, G, and B data supplied from the system 116 to match the mode of the liquid crystal panel 102 so that the first to fourth data driver ICs 106a to. 106d).

As described above, the timing controller 110 includes a control signal generator 112 for generating a gate and data control signal, and a first and a second data for aligning R, G, and B data supplied from the system 116. Second data alignment units 114a and 114b.

The first data alignment unit 114a supplies the R, G, and B data aligned to the first and second data driver ICs 106a and 106b, and the second data alignment unit 114b is configured to supply the third data. And R, G, and B data arranged to the fourth data driver ICs 106c and 106d.

In this case, the first data alignment unit 114a is electrically connected to the first and second data driver ICs 106a and 106b through a first data PCB 108a and the second data alignment unit 114b. ) Is electrically connected to the third and fourth data driver ICs 106c and 106d via a second data PCB 108b.

The system 116 transmits the vertical / horizontal synchronization signal (Vsync / Hsync), the data enable (DE) signal, the predetermined clock signal (CLK), and 10-bit R, G, and B data signals using differential signal transmission. The timing controller 110 is supplied to the timing controller 110.

The differential signal transmission method transmits desired data by using a voltage difference between two lines through which positive and negative signals having opposite polarities are transmitted, respectively. Even if the difference is low, the data can be easily recognized.

There are five pairs of connection lines (Data1 to Data10) between the system 116 and the timing controller 110, and the system 116 is connected to the vertical / via the five pairs of connection lines (Data1 to Data10). The horizontal synchronization signal Vsync / Hsync, the data enable signal DE, the predetermined clock signal CLK, and the 10-bit R, G, and B data signals are supplied to the timing controller 110.

Eight pair connection lines exist between the timing controller 110 and the first and second data PCBs 108a and 108b, 10-bit R arranged in the timing controller 110 through the eight pair connection lines. G and B data signals are supplied to the first and second data PCBs 108a and 108b.

10-bit R, G, and B data signals supplied to the first data PCB 108a are supplied to the first and second data driver ICs 106a and 106b. 10-bit R, G, and B data signals supplied to the second data PC 108b are supplied to the third and fourth data driver ICs 106a and 106b.

FIG. 5 is a diagram illustrating a 10-bit data format supplied to the timing controller of FIG. 4.

As shown in FIGS. 4 and 5, the timing controller 110 is perpendicular to the 10-bit R, G, and B data supplied from the system 110 during a predetermined period of the first clock signal CLK-1. The horizontal synchronization signal Vsync / Hsync, the data enable signal DE, and the predetermined clock signal CLK are recognized.

The system 116 supplies 10-bit R, G, and B data to the timing controller 110, as described above. In this case, the 10-bit R, G, and B data are supplied to the timing controller 110 through the first to tenth connection lines Data1 to Data10 that are five pairs.

The 10-bit R, G, and B data are supplied to the timing controller 110 in a form listed in no order, as shown in FIG. 5.

10-bit R, G, and B data supplied at one time through the first to tenth connection lines Data1 to Data10 are data values corresponding to two pixels of the liquid crystal panel 102.

The 10-bit R, G, and B data signals are supplied to the timing controller 110 and properly aligned to match the mode of the liquid crystal panel 102.

That is, the 10-bit R, G, and B data are supplied to the first and second data alignment units 114a and 114b of the timing controller 110 to provide 10-bit R data, 10-bit G data, and 10-bit B data. Are sorted by.

10-bit R, G, and B data respectively aligned in the first and second data alignment units 114a and 114b are transferred through the patterns patterned on the first and second data PCBs 108a and 108b. To fourth data driver ICs 106a to 106d.

FIG. 6 is a diagram illustrating a 10-bit data format supplied to the data driver IC of FIG. 4.

For convenience of description, the 10-bit R, G, and B data supplied to the first and second data driver ICs 106a and 106b through the first data PCB 108a will be described.

10-bit R, G, B data formats supplied to the third and fourth data driver ICs 106c, 106d and 10-bit R, G, supplied to the first and second data driver ICs 106a, 106b. Since the B data formats are the same, the description of the 10-bit R, G, and B data supplied to the third and fourth data driver ICs 106c and 106d is omitted.

4 and 6, first to sixteenth connection lines Data1 to Data16 exist between the first data PCB 108a and the first and second data driver ICs 106a and 106b. do.

10-bit R data, 10-bit G data, and 10-bit B data arranged in the first data alignment unit 114a through the first to sixteenth connection lines Data1 to Data16 are the first data PCBs. The first and second data driver ICs 106a and 106b are supplied via 108a.

The lower 8-bit R data signal of the first pixel of the liquid crystal panel 102 is supplied through the first and second connection lines Data1 and Data2 of the eight pairs of connection lines Data1 to Data16. The most significant two-bit R data signal of the first pixel of the liquid crystal panel 102 is supplied through the seventh and eighth connection lines Data7 and Data8.

As a result, a 10-bit R data signal is supplied to the first pixel of the liquid crystal panel 102.

The lower 8 bit G data signal of the first pixel of the liquid crystal panel 102 is supplied through the third and fourth connection lines Data3 and Data4 among the eight pairs of connection lines Data1 to Data16. The most significant two-bit G data signal of the first pixel of the liquid crystal panel 102 is supplied through the seventh and eighth connection lines Data7 and Data8.

As a result, a 10-bit G data signal is supplied to the first pixel of the liquid crystal panel 102.

The lower 8-bit B data signal of the first pixel of the liquid crystal panel 102 is supplied through the fifth and sixth connection lines Data5 and Data6 of the eight pairs of connection lines Data1 to Data16. The most significant two-bit B data signal of the first pixel of the liquid crystal panel 102 is supplied through the seventh and eighth connection lines Data7 and Data8.

As a result, a 10-bit B data signal is supplied to the first pixel of the liquid crystal panel 102.

The lower 8-bit R data signal of the second pixel of the liquid crystal panel 102 is supplied through the ninth and tenth connection lines Data9 and Data10 of the eight pairs of connection lines Data1 to Data16. The most significant two-bit R data signal of the second pixel of the liquid crystal panel 102 is supplied through the fifteenth and sixteenth connection lines Data15 and Data16.

As a result, a 10-bit R data signal is supplied to the second pixel of the liquid crystal panel 102.

The lower 8-bit G data signal of the second pixel of the liquid crystal panel 102 is supplied through the eleventh and twelfth connection lines Data11 and Data12 of the eight pairs of connection lines Data1 to Data16. The most significant two-bit G data signal of the second pixel of the liquid crystal panel 102 is supplied through the fifteenth and sixteenth connection lines Data15 and Data16.

As a result, a 10-bit G data signal is supplied to the second pixel of the liquid crystal panel 102.

The lower 8 bit B data signal of the second pixel of the liquid crystal panel 102 is supplied through the 13th and 14th connection lines Data13 and Data14 of the 8 pairs of connection lines Data1 to Data16. The most significant two-bit B data signal of the second pixel of the liquid crystal panel 102 is supplied through the fifteenth and sixteenth connection lines Data15 and Data16.

The pair of connection lines Data1 to Data16 of the eight pairs has two pairs of pairs, and as described above, both ends of the two lines through which the positive (+) and the negative (-) signals having opposite polarities are transmitted, respectively. The desired data is transmitted using the voltage difference of.

The first and second data driver ICs 106a and 106b are supplied through the first data PCB 108a to an edge section of the second clock signal CLK-2 supplied from the timing controller 110. 10-bit R data, 10-bit G data, and 10-bit B data will be recognized.

The 10-bit R data R00 to R09 are connected to the first subpixel of the three subpixels constituting the first pixel on the liquid crystal panel 102 through the first and second connection lines Data1 and Data2. ), The lower 8 bits of R data (R00 to R07) are supplied.

In addition, the second subpixel of the three subpixels constituting the first pixel includes a lower 8-bit G of the 10-bit G data G00 to G09 through the third and fourth data connection lines Data3 and Data4. Data G00 to G07 are supplied.

The lower 8-bit B data B00 of the 10-bit B data B00 to B09 is connected to the third subpixel of the three subpixels constituting the first pixel through the fifth and sixth connection lines Data5 and Data6. ~ B07) is supplied.

Most significant two bits (R08, R09) of the 10-bit R data (R00-R09), Most significant two bits (G08, G09) of the 10-bit G data (G00-G09) and the 10-bit B data (B00-) The most significant two bits B08 and B09 of B09 are supplied to the first to third subpixels SP1 to SP3 of the first pixel through the seventh and eighth connection lines Data7 and Data8.

The 10-bit R data R00 to R09, the 10-bit G data G00 to G09, and the 10-bit B data B00 to B09 are supplied to the first and second data driver ICs 106a and 106b. The 10-bit R data R00 to R09, 10-bit G data G00 to G09, and 10-bit B data B00 to B09 are converted into data voltages.

The converted data voltages are respectively supplied to the first to third subpixels of the first pixel of the liquid crystal panel 102, and thus, are converted to the first pixel due to the combination of the data voltages supplied to the first to third subpixels. The predetermined image is displayed.

Among the three subpixels constituting the second pixel defined on the liquid crystal panel 102, the first subpixel includes the 10-bit R data R10 to R19 through the ninth and tenth connection lines Data9 and Data10. Lower 8-bit R data R10 to R17 are supplied.

The lower 8-bit G data G10 of the 10-bit G data G10 to G19 is connected to the second subpixel of the three subpixels constituting the second pixel through the eleventh and twelfth connection lines Data11 and Data12. G17) is supplied.

The lower 8-bit B data B10 to B17 of the 10-bit B data B10 to B19 are connected to the third subpixel of the three subpixels constituting the second pixel through the thirteenth and fourteenth connection lines Data13 and Data14. ) Is supplied.

Most significant two bits (R18, R19) of the 10-bit R data (R10 to R19), Most significant two bits (G18, G19) and the 10-bit B data (B10 to B19) of the 10-bit G data (G10 to G19) The two most significant bits B18 and B19 are supplied to the first to third subpixels of the second pixel through the fifteenth and sixteenth connection lines Data15 and Data16.

Thus, the 10-bit R data (R10 to R19), the 10-bit G data (G10 to G19) and the 10-bit B data (B10 to B19) are the first and second data driver ICs (106a, 106b) ) Is converted into data voltages corresponding to the 10-bit R data R10 to R19, the 10-bit G data G10 to G19, and the 10-bit B data B10 to B19.

The converted data voltages are respectively supplied to the first to third subpixels of the second pixel of the liquid crystal panel 102, and thus, are converted to the second pixel due to the combination of the data voltages supplied to the first to third subpixels. The predetermined image is displayed.

As described above, 10-bit R data (R00 to R09, R10 to R19) and 10-bit G data (G00 to G09, G10 to G19) supplied to the first and second data driver ICs 106a and 106c. , 10-bit B data (B00 to B09, B10 to B19) means data corresponding to two pixels at a time.

As such, the 10-bit R, G, and B data of the first data alignment unit 114a supplied through the first data PCB 108a may correspond to the first data PCB 108a and the first and second data. The first and second data driver ICs 106a and 106b are supplied to the first and second data driver ICs 106b through the eight pairs of connection lines Data1 to Data16 provided between the driver ICs 106a and 106b.

As a result, 10-bit R, G, and B data supplied from the system 116 are output by the data voltage corresponding to 10-bit R, G, and B data from the first and second data driver ICs 106a and 106b. do.

Therefore, the liquid crystal display according to the present invention can display more grayscales than the liquid crystal display which outputs data voltage corresponding to 8-bit R, G, and B data.

In addition, the liquid crystal display device according to the present invention is a first data PCB (108a) and the first and second data driver IC (106a, 106b) in the conventional liquid crystal display device for processing 8-bit R, G, B data Two pairs of connection lines (Data7, Data8, Data15, Data16) can be added between the 10-bit R, G, and B data.

As described above, the liquid crystal display according to the present invention adds two pairs of connection lines to the existing 8-bit R, G, and B data without increasing the driving clock, thereby adding 10-bit R, G, and B data. Can be easily processed.

As mentioned above, the liquid crystal display according to the present invention adds two pairs of connection lines to the existing liquid crystal display device for processing 8-bit R, G, and B data, and adds two pairs of connection lines. By supplying bit R, G, and B data, 10-bit R, G, and B data can be easily implemented without increasing the driving clock.

As described above, the LCD according to the present invention adds two pairs of connection lines to the existing LCD to process 8-bit R, G, and B data, and adds two pairs of connection lines. By supplying bit R, G, and B data, 10-bit R, G, and B data can be easily implemented without increasing the driving clock.

In addition, since the liquid crystal display according to the present invention processes 10-bit R, G, and B data, it is possible to display more gray levels than the conventional liquid crystal display device that processes 8-bit R, G, and B data.

Claims (14)

A liquid crystal panel; Gate data and a data driver for driving the liquid crystal panel; A timing controller for supplying j bits of R, G, and B data to the data driver; And M transmission line formed between the timing controller and the data driver, The m transmission line has a relationship of (3 + alpha) n. The method of claim 1, [Alpha] denotes a transmission line to which the most significant two bits of R, G and B data are supplied among the j bits of R, G and B data. The method of claim 1, 3 denotes first to third transmission lines, and the first transmission line is supplied with R data of the lowest a bit of the R data of the j bits, and the lowest transmission rate of G data of the j bit is supplied to the second transmission line. A bit G data is supplied and the third transmission line is supplied with the lowest a bit B data of the j bit B data. The method of claim 1, And n is a pair of the m transmission lines. The method of claim 1 J is 10, wherein the liquid crystal display device is characterized in that. The method of claim 1, Wherein α is 1; The method of claim 1, N is 2, the liquid crystal display device. The method of claim 3, Wherein a is eight. The method of claim 1, The m transmission line is a differential signal transmission method, characterized in that for supplying the j-bit R, G, B data to the data driver. 10. The method of claim 9, The differential signal transmission method is a low voltage differential signaling (LVDS) method. A driving method of a liquid crystal display device comprising a liquid crystal panel, a gate driver and a data driver for driving the liquid crystal panel, supplying j bits of R, G, and B data; Supplying the j bits of R, G, and B data to the data driver through m transmission lines; Displaying an image corresponding to the R, G, and B data of the j bits supplied to the data driver, And the m transmission lines have a relationship of (3 + α) n. 12. The method of claim 11, J is 10. The method of claim 10, wherein the j is 10. 13. The method of claim 12, And the two most significant bits of the 10-bit R, G, and B data are supplied to a transmission line having the number of α. 13. The method of claim 12, And the lower 8 bits of the 10 bits of R, G, and B data are supplied to a transmission line having the number of 3.

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