KR100864976B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device for simplifying a control PCB.

The liquid crystal display device comprises: a liquid crystal display panel including first and second data line groups and a LOG wiring separated from the data line groups; A control PCB for outputting timing control signals and data through a single output port and generating a driving voltage; A first data circuit group including first data ICs for supplying the timing control signal, the data and the driving voltage to the first data line group; A first source PCB to which the first data circuit group is connected; A second data circuit group including second data ICs for supplying the timing control signal, the data, and the driving voltage to the second data line group supplied through the LOG wiring; A second source PCB to which the second data circuit group is connected; And a connection portion for electrically connecting the control PCB and the first source PCB; The line width of the dummy line for transmitting the driving voltage in the dummy lines formed in at least one of the first and second data circuit groups may be wider than the line width of the other dummy lines.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

1 is an equivalent circuit diagram showing a liquid crystal cell of a liquid crystal display device.

2 shows a liquid crystal display device having a single source PCB.

3 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 4 is a diagram showing in detail the connection structure of the timing controller and data ICs shown in FIG. 3; FIG.

FIG. 5 is a plan view illustrating dummy wirings formed in a source COF and LOG wirings formed on a substrate of a liquid crystal display panel. FIG.

6 is a block diagram illustrating in detail a data processor of the timing controller illustrated in FIGS. 3 and 4.

7 and 8 are waveform diagrams illustrating an output example of the data modulator shown in FIG. 6;

FIG. 9 is a diagram illustrating a signal transmission path between the timing controller and data ICs shown in FIG. 4; FIG.

FIG. 10 is a block diagram showing in detail the data IC shown in FIG. 4; FIG.

FIG. 11 is a circuit diagram illustrating in detail a gamma compensation voltage generation unit illustrated in FIG. 10.

12 is a circuit diagram showing in detail the DAC shown in FIG.

13 and 14 illustrate an example in which a source PCB is separated and an output port of a timing controller is configured as a double output port.

<Description of Symbols for Main Parts of Drawings>

30 liquid crystal display panel 31 timing controller

32: data driving circuit 33: gate driving circuit

40: Control PCB 41A, 41B, 131A, 131B: Source PCB

42: source COF 43, 113A, 113B: FFC

44, 114A, 114B: Wiring 61, 121: 2-port extension

62, 122: data modulator 63: single output port

91: shift register 92: data recovery unit

93, 94: latch 95: gamma voltage generator

96: DAC 97: Charge Share Circuit

98: output circuit 101: P-decoder

102: N-decoder 103: multiplexer

120: left / right data separator 141, 142: double output port

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device for simplifying a control printed circuit board (hereinafter referred to as "PCB").

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The active matrix type liquid crystal display device switches the data voltage supplied to the liquid crystal cells by using a thin film transistor (hereinafter referred to as TFT) formed for each liquid crystal cell Clc as shown in FIG. 1. By actively controlling data, the display quality of moving images can be improved. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining a data voltage charged in a liquid crystal cell Clc, “DL” denotes a data line to which a data voltage is supplied, and “GL”. Denotes a gate line to which a scan voltage is supplied.

In recent years, LCDs have been developed in large and medium sized models as well as small and large TVs and monitors. 2, the control PCB 20, the source PCB 22, the cable 21 connected to the source PCB 22 and the control PCB 20, the source PCB 22, and the liquid crystal display panel 25 as shown in FIG. 2. ) And a plurality of source COFs (Chip on film: 24).

The source COF 24 is electrically connected to the data PCBs of the source PCB 22 and the liquid crystal display panel 25. A data integrated circuit (hereinafter referred to as "IC") 23 is mounted on this source COF 24.

Source wirings 22 are provided with signal wirings for transmitting digital video data and timing control signals from the control PCB 20.

The control circuit 20 includes a control circuit and a data transmission circuit. The control PCB 20 supplies timing control signals for supplying data to the data IC 23 of the source PCB 22 and controlling the operation of the data IC 23 to the source PCB 22 through the cable 21. Supply.

In the liquid crystal display device of FIG. 2, when the liquid crystal display panel 25 becomes larger, the data lines and the source COFs 24 become larger, and as a result, the source PCB 22 becomes larger. In this case, alignment of the source PCB 22 and the source COF 24 becomes difficult. As the source PCB 22 grows larger, automated mounting devices, such as conventional Surface Mount Technology (SMT) equipment, are designed based on a relatively small size of the source PCB 22 and thus cannot handle the large source PCB 22. In addition, as the size of the LCD increases, the number of circuit elements such as a memory increases and the number of output pins increases, thereby increasing the cost of manufacturing the control PCB 20.

Accordingly, an object of the present invention is to provide a liquid crystal display device which divides a source PCB and reduces the size of the control PCB and the number of output pins.

Another object of the present invention is to provide a liquid crystal display device which minimizes a variation in driving voltage between divided source PCBs.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel including a first and second data line group, and a LOG wiring separated from the data line group; A control PCB for outputting timing control signals and data through a single output port and generating a driving voltage; A first data circuit group including first data ICs for supplying the timing control signal, the data and the driving voltage to the first data line group; A first source PCB to which the first data circuit group is connected; A second data circuit group including second data ICs for supplying the timing control signal, the data, and the driving voltage to the second data line group supplied through the LOG wiring; A second source PCB to which the second data circuit group is connected; And a connection portion for electrically connecting the control PCB and the first source PCB; The line width of the dummy line for transmitting the driving voltage in the dummy lines formed in at least one of the first and second data circuit groups may be wider than the line width of the other dummy lines.

The dummy wires are formed in any one of a chip on film (COF) and a tape carrier package (TCP) on which the first and second data ICs are mounted.

The timing control signal and the data are transmitted through the other dummy wires.

The control PCB, the timing controller for outputting the timing control signal and the data through a single output port; And a power generation circuit for generating the driving voltage.

The connection unit, a cable for electrically connecting the first source PCB and the control PCB; And a connection line formed on the control PCB to electrically connect the single output port and the output terminal of the power generation circuit to the cable.

The timing controller may include: a two-port expansion unit for dividing the data input at an input frequency into odd pixel data and even pixel data, and outputting the data at a half frequency of the input frequency; And a data modulator for modulating data from the two-port expansion unit and outputting the data at a frequency twice higher than the input frequency through the single output port.

The data modulator modulates the data using any one of a mini low-voltage differential signaling (LVDS) scheme and a reduced swing differential signaling (RSDS) scheme.

Each of the data ICs includes a data recovery unit for recovering the modulated data.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 14.

Referring to FIG. 3, the liquid crystal display according to the exemplary embodiment includes a liquid crystal display panel 30, a timing controller 31, a data driving circuit 32, and a gate driving circuit 33.

In the liquid crystal display panel 30, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 30 includes m × n liquid crystal cells Clc in which m data lines D1 to Dm and n gate lines G1 to Gn are arranged in a matrix by a cross structure. Include.

The lower glass substrate of the liquid crystal display panel 30 includes data lines D1 to Dm, gate lines G1 to Gn, TFTs, pixel electrodes 1 of a liquid crystal cell Clc connected to a TFT, and The storage capacitor Cst and the like are formed. On the lower organic substrate of the liquid crystal display panel 30, line on glass wirings (hereinafter referred to as "LOG") for transmitting data, a data timing control signal, a driving voltage, and the like are formed between source COFs described below. do.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 30. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 30, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment film for setting the pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

The timing controller 31 receives timing signals such as a vertical / horizontal synchronization signal, a data enable signal, a clock signal, and generates timing control signals for controlling the operation timing of the data driver circuit 32 and the gate driver circuit 33. do. The timing control signals include gate timing control signals such as a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate driving circuit and is a timing control signal for sequentially shifting the gate start pulse GSP, and is generated with a pulse width corresponding to the ON period of the TFT. The gate output signal GOE indicates the output of the gate driving circuit 33. In addition, the timing control signals include data timing control signals including a source sampling clock (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like. The source sampling clock SSC instructs a latch operation of data in the data driving circuit 32 based on a rising or falling edge. The source output enable signal SOE indicates the output of the data driving circuit 32. The polarity control signal POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 30. In addition, the timing controller 31 separates the digital video data into odd pixel data RGBodd and even pixel data RGBeven and supplies the data to the data driving circuit 32. In order to reduce the swing width of the EMI and the data voltage on the data transmission path, the timing controller 31 modulates the data by mini-low-voltage differential signaling (LVDS) or reduced swing differential signaling (RSDS). 32).

The data driving circuit 32 latches the digital video data RGBodd and RGBeven under the control of the timing controller 31. The data driving circuit 32 converts the digital video data into an analog positive / negative gamma compensation voltage according to the polarity control signal POL to generate a positive / negative analog data voltage and converts the data voltage into data lines. It supplies to (D1-Dm).

The gate driving circuit 33 includes a shift register and a level shifter for converting the output signal of the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn, respectively. It consists of a number of gate ICs, including. The gate driving circuit 33 sequentially outputs scan pulses. The ICs of the gate driving circuit 33 are mounted in a COF or Tape Carrier Package (TCP) and connected to gate pads formed on the lower glass substrate of the liquid crystal display panel 30 using an anisotropic conductive film (ACF). In addition, the gate driving circuit 33 may simultaneously use the liquid crystal display panel 30 together with data lines D1 to Dm, gate lines G1 to Gn, and TFTs formed in the pixel array using a gate in panel process. It can be formed directly on the lower glass substrate of the. In addition, the IC of the gate driving circuit 33 may be directly bonded to the lower glass substrate of the liquid crystal display panel 30 by a chip on glass (Ghip On Galss) method.

FIG. 4 is a view showing an assembled state of the liquid crystal display panel 30, the data driving circuit 32, and the timing controller 31 shown in FIG. FIG. 5 illustrates dummy wirings formed in the source COF and LOG wirings formed on the substrate of the liquid crystal display panel 30.

4 and 5, the data driving circuit 32 includes a plurality of first and second data ICs 32a and 32b.

Multiple data ICs 32a and 32b are each mounted in source COF 42. The source COF 42 may be replaced with a source Tape Carrier Package (TCP). Source COFs 42 are divided into two divided first and second source PCBs 41A, 41B. The input terminals of the source COFs 42 are electrically connected to the output terminals of the first and second source PCBs 41A and 41B, and the output terminals of the source COFs 42 are connected to the liquid crystal display panel through the ACF. 30 is electrically connected to the data pads formed on the lower glass substrate of 30). The source COFs 42 are formed with dummy wirings 51 for transmitting a data timing control signal and a driving voltage as shown in FIG. 5. The dummy wires 51 may include first dummy wires 51a for transmitting data timing control signals including digital video data RGBodd and RGBeven, a carry signal, a high potential power voltage Vdd, and a low potential voltage power supply ( Vss), and second dummy wires 51b for transmitting driving voltages such as gamma reference voltages. Among the source COFs 42 connected to the first source PCB 41A, the source COF 42 neighboring the second source PCB 41B and the source COFs 42 connected to the second source PCB 41B. 1 Between the source PCB 41A and the neighboring source COFs 42, the lower glass substrate of the liquid crystal display panel 30 has data timing control signals and drive including data and carry signals between the source COFs 42. LOG wires 45 are formed which transmit voltage. The LOG lines 45 have a large line resistance due to process characteristics, and the sum of the line resistances may be replaced with an equivalent resistance Rlog as shown in the dotted line of FIG. 5. Due to the voltage drop by the equivalent resistance Rlog, the magnitude of the driving voltage supplied from the second source PCB 41B is reduced compared to the magnitude of the driving voltage supplied from the first source PCB 41A. The deviation of the driving voltages in both of the source PCBs 41A and 41B causes variation in the gamma compensation voltages VGH and VGL generated from the gamma compensation voltage generator 95 of FIG. 10 in response to the same digital video data. do. Therefore, in the exemplary embodiment of the present invention, as shown in FIG. 5, the line widths of the second dummy wires 51b for transmitting the driving voltage are wider than the line widths of the first dummy wires 51a for transmitting the data timing control signal. In addition, the line widths of the second LOG wires 45b electrically connected to the second dummy wires 51b are also larger than those of the first LOG wires 45a electrically connected to the first dummy wires 51a. It is preferable to enlarge. In general, since the size of the resistor is proportional to the length of the resistor and inversely proportional to the unit area of the resistor, increasing the line width of the second dummy wirings 51b reduces the amount of voltage drop due to the line resistance. For reference, the line widths of the first dummy wires 51a need not be widened. This is because the first dummy wires 51a transmit data timing control signals including the digital video data RGBodd and RGBeven and a carry signal, and thus are not affected by the line resistances of the first LOG wires 45a.

The first and second source PCBs 41A and 41B have bus wirings for transmitting digital video data RGBodd and RGBeven, bus wirings for transmitting data timing control signals, and bus wirings for driving voltages. do.

The input terminals of the first source PCB 41A are electrically connected to the connection wires 44 formed on the control PCB 40 via the flexible flat cable 43. The second source PCB 41B is not connected to the control PCB 40. The divided source PCBs 41A and 41B are electrically connected via the LOG wirings and the source COFs 42. Accordingly, the first source PCB 41A supplies digital video data (RGBodd, RGBeven), data timing signals and driving voltages from the control PCB 40 via the connection wires 44 formed on the control PCB 40. The second source PCB 41B receives the digital video data RGBodd, RGBeven, data timing signals and driving voltages from the first source PCB 41A via the LOG wirings 45 and the source COFs 42. To be supplied.

The control PCB 40, along with circuits such as a DC-DC converter for generating a driving voltage of the timing controller 31, the EEPROM 31a, and the liquid crystal display panel 30, is connected to the wiring lines ( 44) is formed. The driving voltages generated by the DC-DC converter are gate high voltage (Vgh), gate low voltage (Vgl), common voltage (Vcom), high potential supply voltage (Vdd), low potential supply voltage (Vss), and high potential supply voltage. A plurality of gamma reference voltages, etc., which are divided between Vdd and the low potential power supply voltage Vss. The gamma reference voltages are subdivided into analog gamma compensation voltages corresponding to each gray level in the data ICs 32a and 32b by the number of gray levels that can be represented by the number of bits of the digital video data RGBodd and RGBeven. The gate high voltage Vgh and the gate low voltage Vgl are swing voltages of the scan pulse. The EEPROM 31a stores waveform option information for timing control signals generated from the timing controller 31 for each of a plurality of modes, and supplies waveform information to the timing controller 31 in a corresponding mode according to a command from a user. The timing controller 31 generates timing control signals in different forms in each mode according to the waveform option information from the EEPROM 31a.

The connection wires 44 formed on the control PCB 40 connect the single output port 63 of the timing controller 31 shown in FIG. 6 to the FFC 43. Digital video data (RGBodd, RGBeven) and timing control signals generated from the timing controller 31 and driving voltages generated from the DC-DC converter are transmitted to the FFC 43 through the connection wires 44. .

6 is a diagram illustrating a data processing portion in the timing controller 31.

Referring to FIG. 6, the timing controller 31 includes a two port extension unit 61 and a data modulator 62.

The two-port expansion unit 61 separates the digital video data RGB inputted from the mainboard of the system at a predetermined input frequency f into odd pixel data RGBodd and even pixel data RGBeven. RGBodd and RGBeven are supplied to the data modulator 62 at 1/2 frequency (1/2 f). Here, the reason for reducing the frequency by 1/2 is to reduce the electromagnetic interference (EMI). The swing widths of the data RGBodd and RGBeven output from the two-port extension 61 are relatively high at 3.3V, which is a transistor-to-transistor (TTL) level.

The data modulator 62 modulates the data using the mini LVDS method to reduce the swing width of the data RGBodd and RGBeven from the 2-port expansion unit 61 to about 300 mV to 600 mV and to adjust the frequency of the data according to the 4x mini LVDS clock. Increase to 2 times (2f) of input frequency (f). Even if the frequency of the data output from the data modulator 62 is twice as high as the input frequency f, the swing widths of the data RGBodd and RGBeven are significantly lowered to about 300 mV to 600 mV as described above. EMI is hardly increased. The signals output from the data modulator 62 include three pairs of RGB pixel data RGBodd, three pairs of even pixel data RGBeven and a pair of mini clocks Mini CLK. Each pair includes a positive signal and a negative signal. Meanwhile, the data modulator 62 may modulate data using the RSDS method.

7 and 8 illustrate an example of data output from the data modulator 62, which is an example of data modulated by the mini LVDS method.

In FIG. 7, "Data CLK" is a data clock generated from the main board of the system, and "mini LVDS CLK" is a clock generated from the data modulator 62 and transmitted with the data. &Quot; mini LVDS RGB " is a positive data waveform modulated by the data modulator 62 including a reset waveform. The data modulator 62 generates the negative data waveform in the inverse phase of the positive data waveform, and each of six pairs of data including the positive data waveform P and the negative data waveform N as shown in FIG. 8. And a pair of mini LVDS clocks to the data ICs 32a and 32b. The data IC sampling the first data recognizes a start pulse (start) following the reset waveform as the data sampling start time and starts sampling data supplied after the start pulse (start). Therefore, the timing controller 31 does not generate a source start pulse SSP through a separate wiring.

9 shows a signal transmission path between the timing controller 31 and the data ICs 32a and 32b.

9, among the digital video data modulated by the mini LVDS method or the RSDS method by the timing controller 31, the right data RGBodd and RGBeven are connected to the single output port 63 of the timing controller 31. The wiring 44 is transferred to the first data ICs 32a connected to the first source PCB 41A via the FFC 43. The right data RGBodd and RGBeven are data to be displayed on the right half screen of the liquid crystal display panel 30. The left data RGBodd and RGBeven, which are modulated by the timing controller 31 in the mini LVDS method or the RSDS method, include the single output port 63, the connection line 44, and the first source PCB 41A of the timing controller 31. ), The dummy wiring 51 of the source COF 42, and the second data ICs 32b connected to the second source PCB 41B via the LOG wiring 45 of the liquid crystal display panel 30. do. The left data RGBodd and RGBeven are data to be displayed on the left half screen of the liquid crystal display panel 30.

The data timing control signals generated by the timing controller 31 together with the data are transmitted to the first source PCB 41A via the single output port 63 of the timing controller 31, the connection wiring 44, and the FFC 43. Are transmitted to the first data ICs 32a connected to the. In addition, the data timing control signals include the single output port 63 of the timing controller 31, the connection wiring 44, the first source PCB 41A, the dummy wiring 51 of the source COF 42, and the liquid crystal display panel. It is transmitted to the second data ICs 32b connected to the second source PCB 41B via the LOG wiring 45 of 30.

The leftmost data IC 32b sampling the first data samples a carry signal indicating the sampling timing of the next data after sampling the data after the start pulse by the number of output channels thereof in FIGS. 7 and 8. Is generated and supplied to the data IC 32b immediately neighboring to the right. Similarly, the carry signal is sequentially transmitted to neighboring data ICs 32b. A carry signal is transmitted between the first and second source PCBs 41A and 41B through a LOG line 45 formed in the liquid crystal display panel 30. On the other hand, the data sampling direction of the data ICs 32a and 32b can be reversely adjusted. In this case, a carry signal is transmitted in the opposite direction between the first and second source PCBs 41B.

The driving voltages generated from the DC-DC converter mounted on the control PCB 40 are connected to the first source PCB 41A via the output terminal of the DC-DC converter, the connection wiring 44 and the FFC 43. Are transmitted to the first data ICs 32a. In addition, the driving voltages may include the output terminal of the DC-DC converter, the connection wiring 44, the first source PCB 41A, the dummy wiring 51 of the source COF 42, and the LOG wiring of the liquid crystal display panel 30. 45 is sent to the second data ICs 32b connected to the second source PCB 41B.

10 to 12 are circuit diagrams showing the first data IC 32a in detail.

10 to 12, each of the first data IC 32a may include a shift register 91, a data recovery unit 92, a first latch array 93, a second latch array 94, and a gamma compensation voltage. A generator 95, a digital-to-analog converter (hereinafter referred to as "DAC") 96, a charge share circuit 97 and an output circuit 98 are included.

The data recovery unit 92 temporarily stores odd pixel data RGBodd and even pixel data RGBeven separated by the timing controller 31 and modulates the demodulation method corresponding to the modulation method by the timing controller 31. Restore the data. For example, as illustrated in FIG. 8, the data recovery unit 92 generates '1' when the positive data is high logic and generates '0' when the positive data is low logic to restore the data. The data recovery unit 92 supplies the restored data RGBodd and RGBeven to the first latch array 93.

The shift register 91 shifts the sampling signal according to the source sampling clock SSC. In addition, the shift register 91 generates a carry signal Carry when data exceeding the number of latches of the first latch array 93 is supplied. The shift register 91 of the first data IC 32a sampling the first data determines the reset signal supplied before the data through the data bus and the data supplied following the start pulse as the first data to be sampled.

The first latch array 93 samples the digital video data RGBeven and RGBodd from the data restoring unit 92 in response to a sampling signal sequentially input from the shift register 91, and stores the data RGBeven, RGBodd) is latched by one horizontal line, and then one horizontal line of data is output at the same time.

The second latch array 94 latches one horizontal line of data input from the first latch array 93 and then, during the low logic period of the source output enable signal SOE, the second latch array of other data ICs. At the same time as 94, the latched digital video data RGBeven and RGBodd are output.

The gamma compensation voltage generation unit 95 stores a plurality of gamma reference voltages divided between the high potential power voltage Vdd and the low potential power voltage Vss with the common voltage Vcom therebetween as shown in FIG. 11. The gamma compensation voltages VGH0 to VGH (i-1) and the negative gamma compensation voltages corresponding to each gray level are further subdivided by the number of gray levels i represented by the number of bits RGBodd and RGBeven. VGL0 to VGL (i-1)). To this end, the gamma compensation voltage generator 95 includes a plurality of voltage divider resistors R01 to Ri1 and R02 to Ri2 connected in series between a high potential power voltage Vdd and a low potential power voltage Vss. A resistance string is provided.

The DAC 96 includes a P-decoder (PDEC) 101 supplied with a positive gamma compensation voltage (VGH) and an N-decoder (NDEC) 102 supplied with a negative gamma compensation voltage (VGL) as shown in FIG. And a multiplexer 103 for selecting the output of the P-decoder 101 and the output of the N-decoder 102 in response to the polarity control signals POL. The P-decoder 101 decodes the digital video data RGBeven and RGBodd input from the second latch array 94 and outputs a positive gamma compensation voltage VGH corresponding to the grayscale value of the data. The decoder 102 decodes the digital video data RGBeven and RGBodd input from the second latch array 94 and outputs a negative gamma compensation voltage VGL corresponding to the gray value of the data. The multiplexer 103 selects the positive gamma compensation voltage VGH and the negative gamma compensation voltage VGL in response to the polarity control signal POL.

The charge share circuit 97 shorts the neighboring data output channels during the high logic period of the source output enable signal SOE to output the average value of the neighboring data voltages as the charge share voltage, or the source output enable signal. The common voltage Vcom is supplied to the data output channels during the high logic period of the SOE to reduce the sudden change of the positive data voltage and the negative data voltage.

The output circuit 98 includes a buffer to minimize signal attenuation of the analog data voltage supplied to the data lines D1 to Dk.

The second data IC 32b also has a configuration substantially the same as that of the first data IC 32a.

Meanwhile, as shown in FIG. 13, the source PCBs 131A and 131B are separated into two, and the output controller of the timing controller 111 is separated into two and configured as a double output port, thereby gamma between the two source PCBs 131A and 131B. A method of eliminating the deviation of the compensation voltage may be considered, but in this case, the timing controller 111 and the control PCB 110 may be large.

This will be described in detail as follows.

Assuming that the output ports of the timing controller 111 are divided into two, the timing controller 111 includes a left / right data separator 120, a two-port expansion unit 121, and a data modulator 122 as shown in FIG. 14. It is provided.

The left / right data separator 120 separates the input digital video data RGB input at the input frequency f into left data RGBl and right data RGBr using a frame memory. The data RGBl and RGBr output from the left and right data separators 120 are supplied to the two-port expansion unit 121 at 1/2 frequency f / 2 of the input frequency.

Due to the left / right data separator 120 and the two FFCs 113A and 113B, when the output port of the timing controller 111 is separated into the double output ports 141 and 142, the size of the timing controller 111 is increased. It can only grow.

The two-port expansion unit 121 stores the left and right data RGBl and RGBr inputted from the left and right data separation unit 120 at 1/2 frequency f / 2 and the odd pixel data RGBlodd and RGBrodd. The data is separated into even pixel data RGBleven and RGBreven, and the data RGBodd and RGBeven are supplied to the data modulator 122 at 1/4 frequency f / 4.

The data modulator 122 increases the frequency of the data (RGBlodd, RGBrodd, RGBleven, RGBreven) from the two-port expansion unit 121 according to the 4x mini LVDS clock when modulating data in the mini LVDS method. The left data RGBrodd and RGBleven and the right data RGBrodd and RGBreven are divided and output to different output ports 141 and 142 at the same frequency f. Since the left data RGBlodd and RGBleven and the right data RGBrodd and RGBreven each include three pairs of odd pixel data, three pairs of even pixel data, and one pair of mini clocks, the output pins of the timing controller 111 The number is required twice or more as compared to the embodiment of the present invention described above. The right data RGBrodd and RGBreven are transmitted to the first source PCB 131A via the first output port 141, the first connection line 114A, and the first FFC 113A of the timing controller 111. . Left data RGBlodd and RGBleven are transmitted to the second source PCB 131B via the second output port 142, the second connection line 114B, and the second FFC 113B of the timing controller 111. .

As a result, when separating the source PCB, it is preferable to configure the output port of the timing controller as a single port in order to reduce the number of timing controllers and their output pins and to reduce the size of the control PCB.

As described above, the LCD according to the present invention can reduce the size of the control PCB and the number of output pins by dividing the source PCB and configuring the output port of the timing controller as a single output port.

Furthermore, the liquid crystal display according to the present invention can simplify the connection structure between the source PCB and the control PCB and reduce the number of components by removing one FFC by using the LOG wiring formed on the liquid crystal display panel.

Furthermore, the liquid crystal display according to the present invention forms a line width of the dummy wires formed in the source COF or the source TCP to transmit the driving voltage to be wider than that of other dummy wires transmitting the data timing control signal. As a result, the present invention can minimize the voltage drop due to the LOG wiring resistance to eliminate the deviation of the gamma compensation voltage between the first source PCB and the second source PCB.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

A liquid crystal display panel including first and second data line groups and a LOG wiring separated from the data line groups; A control PCB for outputting timing control signals and data through a single output port and generating a driving voltage; A first data circuit group including first data ICs for supplying the timing control signal, the data and the driving voltage to the first data line group; A first source PCB to which the first data circuit group is connected; A second data circuit group including second data ICs for supplying the timing control signal, the data, and the driving voltage to the second data line group supplied through the LOG wiring; A second source PCB to which the second data circuit group is connected; And A connection portion for electrically connecting the control PCB and the first source PCB; And a line width of the dummy line for transmitting the driving voltage in the dummy lines formed in at least one of the first and second data circuit groups is wider than that of the other dummy lines. The method of claim 1, The dummy wires, And at least one of a chip on film (COF) and a tape carrier package (TCP) on which the first and second data ICs are mounted. The method of claim 1, And the timing control signal and the data are transmitted through the other dummy wires. The method of claim 1, On the control PCB, A timing controller configured to output the timing control signal and the data through a single output port; And And a power generation circuit for generating the driving voltage. The method of claim 4, wherein The connecting portion, A cable for electrically connecting the first source PCB and the control PCB; And And a connection line formed on the control PCB to electrically connect the single output port and the output terminal of the power generation circuit to the cable. The method of claim 4, wherein The timing controller, A two-port expansion unit for dividing the data input at an input frequency into odd pixel data and even pixel data and outputting the data at a frequency 1/2 of the input frequency; And And a data modulator for modulating data from the two-port expansion unit and outputting the data at a frequency two times higher than the input frequency through the single output port. The method of claim 6, The data modulator, A liquid crystal display device characterized by modulating the data by any one of a mini low-voltage differential signaling (LVDS) scheme and a reduced swing differential signaling (RSDS) scheme. The method of claim 7, wherein Each of the data ICs, And a data recovery unit for restoring the modulated data.

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