KR102279494B1 - Liquid Crystal Display - Google Patents

Abstract

A liquid crystal display according to the present invention includes pixels, dummy pixels, a data line, a timing controller, and a data driver. The pixels display an image, and the dummy pixels are disposed adjacent to the pixels. The data line is connected to the dummy pixels and the pixels. The timing controller separates the vertical blank period and the image display period, and generates dummy data provided to the dummy pixels during the vertical blank period. The data driver generates a dummy data voltage based on the dummy data, generates a data voltage based on the image data, and outputs the dummy data voltage during the vertical blank period and the data voltage during the image display period.

Description

Liquid Crystal Display {Liquid Crystal Display}

The present invention relates to a liquid crystal display device.

An active matrix driving type liquid crystal display uses a thin film transistor (hereinafter referred to as "TFT") as a switching element to display a moving picture. This liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), so it is not only applied to displays in portable information devices, office devices, computers, etc., but also to televisions, which is rapidly replacing cathode ray tubes.

Pixels of the liquid crystal display device include TFTs at which data lines and gate lines cross, and are connected to the intersections. The TFT supplies the data voltage supplied through the data line to the pixel electrode of the liquid crystal cell in response to a gate pulse from the gate line. The liquid crystal cell is rotated by an electric field generated according to a voltage difference between the voltage of the pixel electrode and the common voltage Vcom applied to the common electrode to adjust the amount of light passing through the polarizing plate. The storage capacitor is connected to the pixel electrode of the liquid crystal cell to maintain the voltage of the liquid crystal cell. A ripple phenomenon may occur in the common voltage Vcom applied to the common electrode due to electrical coupling with the pixel electrode.

The ripple phenomenon of the common voltage Vcom is proportional to the amount of change of the data voltage with time. Accordingly, when the first image data is received following the vertical blank period, the ripple of the common voltage also increases because the amount of change in the data voltage is large. The ripple phenomenon of the common voltage Vcom causes a line dim phenomenon along the horizontal direction, thereby degrading display quality.

An object of the present invention is to provide a liquid crystal display capable of improving a horizontal dim phenomenon caused by a ripple phenomenon of a common voltage.

A liquid crystal display according to the present invention includes pixels, dummy pixels, a data line, a timing controller, and a data driver. The pixels display an image, and the dummy pixels are disposed adjacent to the pixels. The data line is connected to the dummy pixels and the pixels. The timing controller separates the vertical blank period and the image display period, and generates dummy data provided to the dummy pixels during the vertical blank period. The data driver generates a dummy data voltage based on the dummy data, generates a data voltage based on the image data, and outputs the dummy data voltage during the vertical blank period and the data voltage during the image display period.

In the present invention, since dummy data is input during the vertical blank period to induce the ripple phenomenon of the common voltage to occur while avoiding the display period, the dim phenomenon caused by the ripple phenomenon of the common voltage during the display period can be improved.

1 is a block diagram showing the configuration of a display device according to the present invention.
2 is a block diagram showing the configuration of a data driver according to the present invention.
3 and 4 are waveform diagrams illustrating an output signal of a timing controller and a data voltage output by a data driver according to the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a block diagram showing the configuration of a liquid crystal display device according to the present invention.

Referring to FIG. 1 , the liquid crystal display according to the present invention includes a liquid crystal display panel 100 , a timing controller 200 , a data driver 300 , and a gate driver 400 . The data driver 300 includes a plurality of source drive ICs. The gate driver 400 includes a plurality of gate drive ICs.

The liquid crystal display panel 100 includes a TFT array substrate, a color filter array substrate facing the TFT array substrate, and a liquid crystal layer formed between the TFT array substrate and the color filter array substrate. In the liquid crystal layer between the TFT array substrate and the color filter array substrate, pixels are arranged in a matrix form defined by a cross structure of the data lines DL and the gate lines GL.

The liquid crystal display panel 100 includes dummy pixels arranged in dummy horizontal lines HL_D1 and HL_D2 and pixels arranged in horizontal lines HL1 to HLm. The pixels receive a data voltage from the data line DL to display an image. The dummy pixels are located closer to the data driver 300 than the pixels.

The TFT array substrate is a TFT formed at intersections of the data lines DL1 to DLn, the gate lines GL1 to GLm, and the data lines DL1 to DLn and the gate lines GL1 to GLm formed on the lower glass substrate. and a pixel electrode 1 connected to the TFTs 1:1, a storage capacitor Cst, and the like. The color filter array substrate includes a black matrix and a color filter formed on an upper glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate, and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 facing the pixel electrode 1 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and IPS (In Plane Switching) mode and It is formed on the lower glass substrate together with the pixel electrode 1 in a horizontal electric field driving method such as a Fringe Field Switching (FFS) mode.

The liquid crystal display panel 100 applicable in the present invention may be implemented in any liquid crystal mode as well as TN mode, VA mode, IPS mode, and FFS mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. A backlight unit is required in a transmissive liquid crystal display device and a transflective liquid crystal display device. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 200 supplies digital video data DATA of an input image input from a system board (not shown) to the data driver 300 during the display period. In addition, the timing controller 200 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a dot clock (CLK) from the system board and receives the data driver Control signals for controlling the operation timing of the 300 and the gate driver 400 are generated. The control signals include a gate timing control signal for controlling the operation time of the gate driver 400 and a data timing control signal for controlling the operation timing of the data driver 300 and the vertical polarity of the data voltage.

The timing controller 200 generates dummy data output during the vertical blank period. The dummy data DDATA is provided to the dummy horizontal lines HL_D1 and HL_D2. The timing controller 200 may set the same data as the image data provided to the first horizontal line HL1 as the dummy data DDATA.

The timing controller 200 does not output the gate timing control signals GSP, GSC, and GOE during the vertical blank period and maintains the source output enable signal SOE at a low logic level.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC that generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls outputs of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE), etc. includes The source start pulse SSP controls the data sampling start timing of the data driver 102 . The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source drive ICs based on a rising or falling edge. The polarity control signal POL controls polarity inversion timing of data voltages output from each of the source drive ICs. The source output enable signal SOE controls the output timing of the data driver 102 . When digital video data to be input to the data driver 300 is transmitted in the mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

The data driver 300 includes a plurality of source drive ICs SIC#1 to SIC#4, and supplies data voltages to the data lines DL1 to DLn. Each of the first to fourth source drive ICs SIC#1 to SIC#4 may be connected to the data lines of the liquid crystal display panel 10 through a Chip On Glass (COG) process or a Tape Automated Bonding (TAB) process. there is.

The configuration of each of the source drive ICs SIC#1 to SIC#4 will be described with reference to FIG. 2 .

Each of the first to eighth source drive ICs SIC#1 to SIC#8 includes a shift register unit 241 , a first latch 243 , a second latch 245 , and a digital-to-analog converter 247 (Digital). to Analog Converter (hereinafter referred to as “DAC”) and an output unit 249 .

The shift register unit 241 samples the RGB digital video data bits of the input image by using the data control signals SSC and SSP provided from the timing controller 200 .

The first latch 243 samples and latches digital video data bits according to a clock sequentially provided from the shift register unit 241 , and simultaneously outputs the latched data. The second latch 245 latches data received from the first latch 243 and is synchronized with the second latches 245 of other source drive ICs 240 in response to the source output enable signal SOE. Outputs one data at the same time.

The DAC 247 converts the video data input from the second latch 245 into a positive gamma compensation voltage GMAH and a negative gamma compensation voltage GMAL to convert the positive/negative analog video data voltage ADATA. Occurs. The DAC 247 inverts the polarity of the data voltage ADATA for each frame in response to the polarity control signal POL.

The output unit 249 outputs the data voltage to the data lines DL1 and DL2 through the output buffer during the low logic period of the source output enable signal SOE. If the source drive ICs (SIC#1 to SIC#4) perform charge sharing, the output unit 340 performs charge sharing for the positive data voltage and the negative data voltage during the high logic period. The average voltage or the common voltage Vcom is supplied to the data lines DL1 to DLn through the output buffer. During the charge sharing time, the output channels to which the positive data voltage is supplied and the output channels to which the negative data voltage is supplied from the source drive ICs (SIC#1 to SIC#4) are short circuited so that the positive data voltage and the positive data voltage are short circuited. The average voltage of the negative data voltage is supplied to the data lines DL1 to DLn.

The gate driver 400 uses a shift register (not shown) and a level shifter (not shown) to generate a gate pulse in response to the gate timing control signals GSP, GSC, and GOE input from the timing controller 200 during the display period. is sequentially supplied to the gate lines GL1 to GLm. The gate driver 400 is mounted on the gate TCP (not shown) and bonded to the TFT array substrate of the liquid crystal display panel by the TAB process, or directly on the TFT array substrate simultaneously with the pixel array by the GIP (Gate In Panel) process. can be formed.

The gate driver 400 does not output the gate pulse because the gate timing control signals GSP, GSC, and GOE are not generated during the vertical blank period BL. Accordingly, since the TFTs of the TFT array substrate maintain an off state, a target voltage is not supplied to the liquid crystal cells Clc.

3 and 4 are diagrams illustrating driving signals according to an embodiment of the present invention. A driving method using dummy data will be described in more detail with reference to FIGS. 1 to 3 .

The timing controller 200 generates the dummy data enable signal DDE within the vertical blank period. The timing controller 200 may detect the vertical synchronization signal Vsync and the data enable signal DE, and detect a predetermined section in which the data enable signal DE is not detected as the vertical blank period.

The timing controller 200 generates the dummy data enable signal DDE for a predetermined period within the vertical blank period. The pulse width of the dummy data enable signal DDE is the same as the pulse width of the data enable signal DE. A section in which the dummy data enable signal DDE is output is proportional to the number of dummy horizontal lines HL_D1 and HL_D2 to be driven. For example, when two dummy horizontal lines HL_D1 and HL_D2 are to be driven, the dummy data enable signal DDE is maintained for two or more horizontal periods (2H). The timing controller 200 provides dummy data to the data driver 300 in response to the output of the dummy data enable signal DDE.

The data driver 300 outputs the dummy data voltage DDATA based on the dummy data enable signal DDE and the dummy data DDATA within the vertical blank period.

The timing controller 200 does not output the gate start pulse GSP and maintains the source output enable signal SOE at a low logic level during the vertical blank period. During the vertical blank period, the gate shift clock GSC and the gate enable signal GOE may be output. This is because, during the vertical blank period, the gate driving circuit 103 does not generate an output (gate pulse) if the gate start pulse GSP is not input even when the gate shift clock GSC and the gate enable signal GOE are input. am. Accordingly, the gate driver 400 does not output the gate pulse during the vertical blank period.

And, during the display period, the timing controller 200 provides data timing control signals SSP, SSC, SOE so that digital video data DATA of the input image can be addressed to the liquid crystal cells Clc of the liquid crystal display panel 100 . , POL) and gate timing control signals GSP, GSC, and GOE.

The data driver 300 outputs the data voltage ADATA according to the data timing control signals DDC and the digital video data DATA during the display period. The data driver 300 outputs the data voltage ADATA having the same polarity as the dummy data voltage ADDATA by the polarity control signal POL during the display period.

As described above, since the liquid crystal display device according to the embodiment of the present invention outputs the dummy data voltage during the vertical blank period, the period in which the data voltage ADATA swings widely is moved to the vertical blank period instead of the display period. make it That is, a region in which a ripple of the common voltage Vcom may occur is moved from a horizontal line for displaying an image to a dummy horizontal line for not displaying an image. Since the dummy horizontal line is not a section for outputting the data voltage ADATA of the effective digital video data DATA, it is possible to improve the occurrence of a horizontal dim in the display period.

In particular, in the present invention, since the size of the dummy data is set to have the same size as the data voltage provided to the first horizontal line, it is possible to minimize the amount of data change in the process of outputting the image data voltage following the dummy data voltage. Accordingly, it is possible to improve the occurrence of a dim phenomenon in the horizontal line displaying the first image data due to the ripple of the common voltage.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (4)

pixels displaying an image;
dummy pixels disposed adjacent to the pixels;
the dummy pixels and a data line connected to the pixels;
a timing controller for dividing a vertical blank period and an image display period and generating dummy data provided to the dummy pixels during the vertical blank period; and
a data driver for generating a dummy data voltage based on the dummy data, generating a data voltage based on image data, and outputting the dummy data voltage during a vertical blank period and outputting the data voltage during an image display period;
The dummy data is
A liquid crystal display having the same value and the same polarity as the first image data provided to the pixels arranged in a first horizontal line.
The method of claim 1,
The dummy pixels are arranged in one or more columns in a horizontal direction.
delete delete

Images