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KR100248792B1 - 단일층 세라믹 기판을 이용한 칩사이즈 패키지 반도체 - Google Patents

단일층 세라믹 기판을 이용한 칩사이즈 패키지 반도체 Download PDF

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Publication number
KR100248792B1
KR100248792B1 KR1019960067617A KR19960067617A KR100248792B1 KR 100248792 B1 KR100248792 B1 KR 100248792B1 KR 1019960067617 A KR1019960067617 A KR 1019960067617A KR 19960067617 A KR19960067617 A KR 19960067617A KR 100248792 B1 KR100248792 B1 KR 100248792B1
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KR
South Korea
Prior art keywords
chip
substrate
wire bonding
size
package semiconductor
Prior art date
Application number
KR1019960067617A
Other languages
English (en)
Other versions
KR19980048962A (ko
Inventor
공병식
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019960067617A priority Critical patent/KR100248792B1/ko
Priority to US08/992,259 priority patent/US5920118A/en
Priority to JP36412197A priority patent/JP3491003B2/ja
Priority to GB9726869A priority patent/GB2320616B/en
Priority to CN97114383A priority patent/CN1190795A/zh
Publication of KR19980048962A publication Critical patent/KR19980048962A/ko
Application granted granted Critical
Publication of KR100248792B1 publication Critical patent/KR100248792B1/ko

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Abstract

1. 청구범위에 기재된 발명이 속한 기술분야
단일층 세라믹 기판을 이용한 칩사이즈 패키지 반도체
2. 발명이 해결하려고 하는 기술적 과제
단일층의 세라믹 기판을 제공하여 LOC 방식의 반도체 칩을 수용함으로써, 기존의 칩사이즈 패키지보다 경박 소형화할 수 있으면서 신뢰성을 보다 향상시킬 수 있는 칩사이즈 패키지 반도체를 제공하고자 함.
3. 발명의 해결 방법의 요지
와이어 본딩 패드가 중앙부에 형성된 칩; 중앙부에 소정 크기의 사각 형상의 슬롯이 형성된 소정 크기의 세라믹 판재로서, 상기 칩을 상면에 설치하는 기판; 상기 칩을 상기 기판의 상면에 부착하기 위한 부착 부재; 상기 신호회로의 상기 볼 장착부에 각각 장착되어 외부 회로와 연결되는 볼; 상기 칩과 상기 기판 사이에 충전되어 상기 칩 및 기판을 지지 및 보호하는 코팅부를 포함하여 이루어진 칩사이즈 패키지 반도체를 제공함.
4. 발명의 중요한 용도
종래의 패키지보다 신뢰성을 향상시키면서 보다 경박 소형화가 가능하며, 제작 공정에서 공정의 단축이 가능하여 제작비용의 절감, 작업성 및 생산성을 향상시키는 효과가 있다

Description

단일층 세라믹 기판을 이용한 칩사이즈 패키지 반도체
본 발명은 칩사이즈 패키지(CSP: Chip Size Package) 반도체에 관한 것으로, 특히, 단일층으로 특수하게 고안된 구조의 세라믹 기판(sub-strate)을 이용하여 LOC(lead on chip) 방식의 칩을 수용하는 새로운 칩사이즈 패키지 반도체에 관한 것이다.
일반적으로, 칩사이즈 패키지 반도체(이하, CSP 반도체라고 함)는 완성된 패키지 크기가 칩 크기와 동일하거나 또는 칩 크기보다 최대 1㎜ 또는 20% 정도 큰 패키지를 가리킨다. 상기 CSP 반도체는 경박 소형화를 목적으로 여러 가지 방식으로 개발되어 있다. 이하, 종래의 CSP 반도체를 간단히 설명한다.
도1은 LOC 방식의 칩을 수용하는 종래의 CSP 반도체를 도시하고 있다. 상기 CSP 반도체는 LOC용 칩(1); 상기 칩(1)의 하면 소정 위치에서 부착 테이프(4)를 통해 지지하는 리드 프레임(2)으로 구성되며, 상기 칩(1)과 리드 프레임(2) 사이는 와이어 본딩 되어 상호 접속되며, 전체 구성의 지지, 보호, 및 절연을 위하여 몰딩 콤파운드로 성형된다. 그러나, 상기 CSP 반도체는 사전에 일정 형태로 형성된 종래의 리드 프레임을 이용하므로 작업성이 저하되며, 몰딩 작업시, 칩과 리드 프레임 사이에 몰딩 컴파운드가 충전되지 않은 공동부가 발생할 우려가 있고 리드 프레임이 변형될 우려가 있다, 또한, 트림(trim) 공정시, 리드 프레임 부근에 패키지 칩핑(chipping) 및 균열이 발생할 가능성이 있으며, 패키지의 두께를 조정하기 곤란한 문제점이 있었다.
따라서, 상기 문제점을 해소하기 위해 고열 가공된 세라믹(co-fired ceramic) 기판을 이용한 CSP 구조가 제안되었다. 즉, 세라믹 기판 상에 신호회로를 형성한 후, 기판의 양면의 신호 경로를 비아-홀(via-hole)로서 연결시킨 구조의 상면에 범퍼가 형성된 칩을 실장하고 언더-필 코팅한 CSP 반도체가 제안되었다.
그러나, 상기 세라믹 기판을 이용한 CSP 반도체는 기판을 성형한 후, 기판 양면의 신호 경로를 연결하기 위한 구멍의 가공이 용이하지 않으므로, 기판 제작비용이 증대되며, 대량생산이 곤란하며, 기판과 칩 사이에 범퍼가 개입되므로 패키지 두께의 축소가 제한되는 문제점이 있었다.
따라서, 상기한 제반 문제점을 해결하기 위하여 안출된 본 발명은, 단일층으로 특수하게 제작된 세라믹 기판을 제공하여 LOC 방식의 반도체 칩을 수용함으로써, 기존의 CSP 패키지보다 보다 경박 소형화할 수 있으면서 신뢰성을 보다 향상시킬 수 있으며, 저렴하게 대량생산이 가능한 칩사이즈 패키지 반도체 제공하는데 그 목적이 있다.
도1은 종래의 칩사이즈 패키지 반도체를 나타낸 단면도이며;
도2A 및 도2B는 본 발명에 따른 칩사이즈 패키지 반도체를 나타낸 사시도 및 단면도이며;
도3은 본 발명에 따른 칩사이즈 패키지 반도체의 기판을 나타낸 측면도, 상부 평면도 및 하부 평면도이며;
도4는 도3의 기판 상부에 LOC 부착용 테이프가 부착된 조립 상태를 나타낸 단면도 및 평면도이며;
도5는 도4의 조립 상태에서 테이프 상에 칩이 설치된 조립 상태를 나타낸 단면도 및 평면도이며;
도6은 도5의 조립 상태에서 기판과 칩 사이를 와이어로 접속한 조립 상태를 나타낸 단면도 및 평면도이며;
도7은 도6의 조립 상태에서 언더-필(under-fill) 용액으로 코팅한 상태를 나타낸 단면도 및 평면도이며;
도8은 도7의 조립 상태에서 기판 하면 볼 장착부에 볼이 장착되어 조립 완료된 상태를 나타낸 단면도 및 평면도이다.
* 도면의 주요 부분에 대한 부호의 설명
21: 칩 22: 기판
22a: 슬롯22b: 기판 상면
22c: 기판 하면23: 테이프
24: 와이어25: 볼
26: 언더-필 코팅부30: 신호회로
31: 볼 장착부
상기 목적을 달성하기 위하여, 본 발명은 와이어 본딩 패드가 중앙부에 형성된 칩; 중앙부에 소정 크기의 사각 형상의 슬롯이 형성된 소정 크기의 세라믹 판재로서, 상기 칩을 상면에 설치하는 기판; 상기 칩을 상기 기판의 상면에 부착하기 위한 부착 부재; 상기 신호회로의 상기 볼 장착부에 각각 장착되어 외부 회로와 연결되는 볼; 및 상기 칩과 상기 기판 사이에 충전되어 상기 칩 및 기판을 지지 및 보호하는 코팅부를 포함하여 이루어진 칩사이즈 패키지 반도체를 제공한다.
이하, 첨부된 도면을 참조하여 본 발명에 따른 칩사이즈 패키지 반도체의 일실시예 구성을 상세하게 설명한다. 도2A는 본 발명에 따른 CSP 반도체의 전체 형상을 도시하며, 도2B는 도2A의 CSP 반도체의 단면구조를 도시하며, 도3은 본 발명에 따른 CSP 반도체의 단일층 세라믹 기판의 단면, 상면, 하면 구조를 도시하고 있다. 도2 및 도3을 참조하면, 도면 부호 "21"은 칩, "22"는 기판, "22a"는 슬롯, "22b"는 기판 상면, "22c"는 기판 하면, "23"은 테이프, "24"는 와이어, "25"는 볼, "26"은 언더-필 코팅부, "30"은 신호회로, "31"은 볼 장착부를 각각 나타낸다.
도시된 바와 같이 본 발명은, LOC 방식의 칩(21); 중앙부에는 소정 크기의 슬롯(22a)이 형성되고 하면(22c)에는 신호회로(30) 패턴이 형성되며, 상기 칩을 상면에 실장하는 단일층 세라믹 기판(22); 상기 칩(21)을 상기 기판(22)의 상면(22b)에 부착하기 위한 LOC 부착용 테이프(23); 상기 기판(22)의 슬롯(22b)을 통해 상기 칩(21)과 상기 기판(22) 하면(22c)에 형성된 신호회로(30)의 와이어 본딩부를 접속시키는 와이어(24); 상기 신호회로(30) 상에 형성된 다수의 볼 장착부(31)에 각각 장착되어 외부 회로를 구성하는 볼(25); 및 상기 구성 요소를 지지하고 보호하기 위한 언더-필 코팅부(26)로 구성된다.
본 발명의 주요 특징인 상기 기판을 다시 설명하면, 도3에 도시된 바와 같이, 상기 기판은 단일층의 세라믹재로서 본 발명에 따른 CSP 반도체의 베이스로서 역할을 하며, 중앙부 소정 위치에 소정 크기의 슬롯(22a)이 형성되며, 그 상면(22b)에는 아무 패턴이 형성되지 않고 그 하면(22c)에만 신호회로(30)의 패턴이 형성된다. 상기 패턴의 형성은 무전해 도금법으로 기판 하면(22c) 상에 니켈도금을 한 후, 전해 도금으로 금도금을 실시하여 형성시킨다. 상기 신호회로(30)는 도3에서 점선으로 나타낸 와이어 본딩부 및 상기 신호회로(30)의 단부에 형성된 볼 장착부(31)로 구성되며, 상기 와이어 본딩부는 상기 슬롯(22a)을 통해 와이어(24)로 직접적으로 칩(21)에 접속되고 각각의 상기 볼 장착부(31)에는 볼(25)이 각각 장착되어 PCB(printed circuit board)의 패턴과 연결된다. 또한, 상기 서브-스트레이트(22)의 하면(22c)에는 상기 와이어 본딩부 및 상기 볼 장착부를 제외한 부분은 유전체 물질로 도포하여 절연시킨다. 전술한 바와 같이, 본 발명에서는 하면(22c)에만 신호회로 패턴이 형성된 단일층의 세라믹 서브-스트레이트가 적용되고, 칩과 기판 사이는 범퍼가 필요 없이 와이어로 직접적으로 접속되므로 패키지 두께가 종래의 CSP 반도체 경우보다 더 얇게 제작하는 것이 가능하고, 상기 기판에는, 종래의 기판 상에 정확한 위치에 다수의 구멍이 형성될 필요 없이, 중앙부에 소정 크기의 단일 슬롯이 형성되므로, 가공 및 제작이 용이하게 된다. 따라서, 제작비용의 절감과 대량생산이 가능하게 될 수 있다. 세라믹의 양호한 열 방출로 칩 동작시 발생하는 열이 용이하게 방출되어 열적 응력이 저하되므로 칩의 수명을 연장시킬 수가 있다.
이하, 도4 내지 도8을 참조하여, 전술한 단일층 세라믹 기판을 이용한 CSP 반도체를 조립하는 과정을 설명한다.
먼저, 도4에 도시된 바와 같이, 상기 기판(22)의 상면(22b)에 LOC 부착용 테이프(23)를 부착하되, 중앙에 형성된 슬롯(22a)의 양측에 각각 부착한다.
이어서, 도5에 도시된 바와 같이, 상기 기판(22)의 슬롯(22a) 상부에 칩(21)의 중심이 정렬되도록, 상기 테이프(23) 위에 칩을 장착시킨다.
이어서, 도6에 도시된 바와 같이, 상기 기판(22)의 중앙 슬롯(22a) 사이에 배열되어 있는 와이어 본딩 패드와 상기 기판(22)의 하면(22c)에 노출된 신호회로(30)의 와이어 본딩부(점선으로 표시된 부분)를 와이어로 접속한다.
이어서, 와이어 본딩이 완료된 후, 도8에 도시된 바와 같이, 엑폭시계 수지와 같은 코팅 용액을 주입하여 언더-필 코팅부(26)를 형성한다. 이때, 상기 용액은 모세관 형상으로 칩(21)과 기판(22)이 형성한 좁은 틈새 내로 자연스럽게 충전된다. 주입되는 상기 용액의 량은 칩(21)의 선단까지 완전히 채워질 수 있도록 조절한다. 상기 언더-필 용액의 충전이 완료된 후에는 경화시키기 위하여 큐어링(curing)을 실시한다. 그 결과, 종래의 CSP 반도체에서의 몰딩 작업이 생략되며, 몰딩 작업 중에 발생할 수도 있는 패키지 내부의 공동부의 발생 및 기판에서의 변형 문제가 제거되는 효과가 있다. 상기 효과는, 전술한 바와 같이, 칩과 서브-스트레이트 사이에 형성된 틈새로 모세관 현상을 이용하여 코팅 용액을 자연스럽게 충전하므로써 달성될 수 있는 것이다.
이어서, 전술한 공정이 완료된 제품은 상기 기판(22)의 하면(22c) 신호회로(30)의 단부에 형성된 다수의 볼 장착부(31)를 용재(flux)로 처리하며, 도8에 도시된 바와 같이, 상기 볼 장착부(31) 상에 볼(25)을 올려놓고, 적외선 가열로 등에서 가열하여 볼(25)을 장착한다.
이상의 설명에서, 각각의 단계를 거쳐 한 개의 본 발명에 따른 CSP 반도체가 조립되는 과정을 설명하였으나, 전술한 세라믹 기판을 멀티(multi) 기판 형태 제작하여 전술한 조립 단계로 CSP 반도체 조립 작업을 수행한 후, 기형성된 절단선을 따라 절단하면, 단일 CSP 반도체를 대량으로 생산 가능하게 된다. 그 결과, CSP 반도체 조립공정 전체에 걸친 생산성 및 작업성을 향상시킬 수가 있다.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
상기와 같이 구성된 본 발명에 따르면, 종래의 패키지보다 신뢰성이 향상시키면서 보다 두께가 얇은 패키지를 얻을 수 있으며, 열 방출 능력이 향상되어 칩의 수명을 연장하며, 제작 공정에서 공정의 단축, 제작비용의 절감 및 작업성 및 생산성을 향상시키는 효과가 있다.

Claims (4)

  1. LOC 방식의 실리콘 칩을 이용한 칩사이즈 패키지 반도체에 있어서, 와이어 본당 패드가 중앙붕에 구비된 칩:
    중앙부에 소정의 크기의 슬록이 형성된 세라믹 판재로서, 그 일측면에는 다수의 와이어 본딩부 및 다수의 볼 장착부가 구비된 신호회로패턴이 형성되고, 상기 칩이 상면에 장착되는 기판;
    상기 칩을 상기 기판의 상면에 부착하기 위한 적어도 하나의 부착부재;
    상기 신호회로패턴의 볼 장착부에 각각 장착되며, 외부회로와 연결되는 다수의 볼;
    상기 칩가 상기 기판 사이에 충전되어 상기 칩과 기판을 지지 및 보호하는 코팅부; 및
    상기 칩의 와이어 본딩 패드와 상기 기판의 와이어 본딩부를 접속시키기 위한 다수의 와이어를 포함하여 이루어진 칩사이즈 패키지 반도체.
  2. 제1항에 있어서,
    상기 기판의 신호회로가 형성된 면에는 상기 와이어 본딩부 및 볼 장착부를 제외한 나머지 부분이 유전체 물질로 도포된 것을 특징으로 하는 칩사이즈 패키지 반도체.
  3. 제1항에 있어서,
    상기 기판의 슬롯은 상기 와이어 본딩부와 상기 칩의 와이어 본딩 패드에 각각 접속하여 내부 회로를 구성하는 와이어 경로인 것을 특징으로 하는 것을 칩사이즈 패키지 반도체.
  4. 제1항에 있어서,
    상기 코팅부는, 소정 량의 코팅 용액이 상기 기판에 형성된 슬롯을 통하여 주입되어 상기 기판과 칩 사이 틈새를 충전하므로써 형성된 것을 특징으로 하는 칩사이즈 패키지 반도체.
KR1019960067617A 1996-12-18 1996-12-18 단일층 세라믹 기판을 이용한 칩사이즈 패키지 반도체 KR100248792B1 (ko)

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US08/992,259 US5920118A (en) 1996-12-18 1997-12-17 Chip-size package semiconductor
JP36412197A JP3491003B2 (ja) 1996-12-18 1997-12-17 チップサイズパッケージ半導体
GB9726869A GB2320616B (en) 1996-12-18 1997-12-18 An improved chip-size package semiconductor
CN97114383A CN1190795A (zh) 1996-12-18 1997-12-18 采用单层陶瓷基板的芯片大小组件半导体

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GB9726869D0 (en) 1998-02-18
JPH10275880A (ja) 1998-10-13
CN1190795A (zh) 1998-08-19
GB2320616A (en) 1998-06-24
US5920118A (en) 1999-07-06
JP3491003B2 (ja) 2004-01-26
GB2320616B (en) 2002-01-16

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