JPS6346881A - Digital outline correcting circuit - Google Patents

Abstract

PURPOSE:To realize the outline blur due to band limitation of a transmission line without an unnatural feeling and hardware extension by generating the absolute value of a difference value of a picture signal and the difference value to detect a picture outline part and modulating the data rate of an input signal by the signal indicating the outline part. CONSTITUTION:A digital picture signal D1 is inputted to a subtractor 33 not only directly but also through a unit delay element 32 to output a primary difference signal D3, and this signal is converted to an absolute value signal D4 by an absolute value circuit 34. The signal D4 is inputted to a subtractor 36 not only directly but also through a unit delay element 36 to obtain a secondary difference signal D6. A dead zone characteristic is given to the signal D6 by a noise eliminating memory 37, and the signal is sent to data input parts of RAM 38 and 39. The picture signal D1 is inputted to these input parts through a delay circuit 40. Secondary difference signals D8 and D10 and digital picture signals D9 and D11 read out from RAM 38 and 39 are inputted to selectors 44 and 45. The signal from either of RAM is selected by the switching signal from a terminal 48, and an outline-corrected picture signal D13 is outputted from the selector 45 through a D/A converter 46.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is directed to a digital contour correction circuit used in a television signal processing system.

(Conventional technology) In recent years, digital integrated circuits have become more highly integrated and faster.

With the trend towards low G' and K sensitivity, digitization of signal processing is becoming widespread in television receivers as well. This digitization has made it possible to enhance additional functions and further improve image quality, which was not possible with conventional analog circuit technology. One such image quality improvement is image contour correction.Generally, the transmitted television image signal loses wide-range components of the image due to the bandwidth limit of its transmission path. Therefore, no matter how high resolution a camera or television monitor is used, due to the above-mentioned band limitations, the entire image will be blurred, but this is especially noticeable in the edges of the image. The technique is contour correction and is effectively achieved by digital circuit technology.

FIG. 3 shows a conventional contour correction circuit.

A digitized image signal S1 is supplied to the terminal 1. The image signal S1 is supplied to the contour detection circuit 2. A unit delay element 3 having a delay amount of one sample and an adder 5 are supplied. The output S2 of the unit delay element 3 is supplied to the unit delay element 4 and the adder 9.

The output S3 of the 111th delay element 4 is supplied to the adder 5. The output of the adder 5 is multiplied by 1/2 in a multiplier 6 and supplied to a subtracter 7 as a signal S4. The subtracter 7 performs subtraction processing on the signals S4 and 82 to obtain a high frequency component signal S5 for edge enhancement. This signal S5 undergoes gain control in the multiplier 8 using the contour detection signal S6 from the contour detection circuit 2, and is supplied to the adder 9 as a signal S7. Therefore, in this adder 9, the signals S2 and 87 are added, and the high-frequency enhanced contour-corrected video signal S8
is obtained and output to the output terminal 10.

The contour detection circuit 2 is a circuit that generates a signal for controlling the multiplication coefficient K of the multiplier 8 in order to prevent an unnecessary increase in noise in the flat portion of the signal gain. The contour detection circuit 2 includes unit delay elements 21 . Subtractor 22° absolute value circuit 23. Comparator 2
Consists of 4. A difference output S9 is obtained from the subtracter 22, and its absolute value is taken by the absolute value circuit 23. The output signal SIO of the absolute value circuit 23 is supplied to a comparator 24 and compared with a set value RE to obtain a signal indicating whether or not it exceeds the set value RE, that is, a contour detection signal S6.

If the signal S10 exceeds the set value RE, it is determined that it is a contour part, and if it does not exceed it, it is determined that it is not a contour part.

FIG. 4 is a diagram showing the contour correction operation by the above-mentioned circuit using changes in sample data. A in FIG. 4 shows the input image signal S1, but excluding the sample delay, the signal S2. S3 has the same shape.

This signal A shows a contour where the brightness level changes stepwise from low to high, but as mentioned above, the response is not steep due to the band limitation. In FIG. 3, B in FIG. 4 represents the output signal S7 when the count of the multiplier 6 is 1/21 and the count of the multiplier 8 is 1.

Since it is determined that the portions of samples a1 to a6 of A in FIG. 4 are the outline of the image, and the other portions are not the outline, bi of B in FIG. 4 is It is expressed by the following formula.

bj-ai-fa(1-1)+a(i+l)l/2
(When al is an outline part) bi-0 (When al is not an outline part) Therefore, in the adder 9, the signal A in FIG. 4 and the signal B in FIG. This is the C signal.

(Problems to be Solved by the Invention) The conventional circuit described above reduces the blurring of the image by emphasizing and outputting the high frequency portion.

However, this method does not provide any essential improvement. For example, in FIG. 4C, if the dynamic range is from level 01 to 07, samples c3 and 06 completely overshoot the dynamic range.

Therefore, samples c3 and c6 receive the clip,
c3 must be at the level of cl, and c6 must be at the level of cl.

In such a case, the signal will not be different from the original signal A in FIG. In order to avoid such a lip, it is necessary to make the output dynamic range of the contour compensation circuit larger than the input dynamic range, but doing so would result in an increase in hardware. Furthermore, even if the above-mentioned clipping problem is solved, there is a problem that overshoots and undershoots appearing in samples c3 to c6 become ringing on a television screen and are accompanied by unnaturalness.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a contour correction circuit that can eliminate contour blurring of an image caused by band limitation of a transmission path without causing an unnatural feeling and without increasing hardware. It is something.

[Structure of the Invention] (Means for Solving the Problems) This invention provides a first-order difference calculation circuit that differentiates an input digital signal, an absolute value circuit that takes the absolute value of the output of this circuit, and an output of this absolute value circuit. a second-order difference circuit 2 for differentiating the second-order difference circuit 2; a contour detection circuit comprising a nonlinear input/output characteristic circuit that receives the output of the second-order difference circuit; and a memory to which the digital signal and the output of the contour detection circuit are supplied. means for digital-to-analog conversion of the output of the storage means; means for receiving a clock as an input and creating a plurality of clocks with different phases; selecting and supplying a clock to the digital-to-analog converter and a read address generator of the storage means, selecting an intermediate phase clock of the plurality of phase clocks when the output of the storage means is zero; As the output of the storage means increases, one of the plurality of phases with a delayed phase is sequentially selected, and conversely, as the output of the storage means decreases, one with a phase lead among the stages of the plurality of phases is sequentially selected. and a selector for supplying the data.

(Function) With the above means, it is possible to detect the outline of the image by creating the absolute value of the difference value of the image signal and the difference value of this absolute value, and the signal indicating this outline is used to detect the data of the input digital signal. By making samples compressed in the time axis direction during the rate change, that is, in the image contour area, it is possible to perform contour correction within the dynamic range and without increasing hardware. .

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which an input terminal 31 is supplied with a digital image signal D1. This digital image signal D1 is supplied to the unit delay element 32 and also inputted to the subtracter 33. This subtracter 33 performs a subtraction process between the output signal D2 of the unit delay element 32 and the input side signal D1 to obtain a first-order difference signal D3. This signal D3
is input to the absolute value circuit 34 and converted into its absolute value signal D4. This absolute value signal D4 is transmitted to the unit delay element 35.
is supplied to the subtracter 36. This subtracter 36 performs a subtraction process between the signal D4 and the output signal D5 from the unit delay element 35 to obtain a second-order difference signal D6.

This secondary difference signal D6 is stored in a noise removal memory (ROM).
37, it is given a dead band characteristic and is supplied as a signal D7 to the data input of a memory (RAM) 38, 39. Further, the image signal D1 is supplied to the data input section of the RAM 38, 39 after being time-adjusted by a delay circuit 40.

Data is written to and read from the RAMs 38 and 39 alternately, for example, every horizontal period. The write address and read address at this time are determined by the write address generator 41. The read address generator 42 generates the read address. Selector 43
supplies a write address to one of the RAMs and a read address to the other, and the supply destination is switched by an external switching signal SW from a terminal 48.

The secondary difference signal D8 read from the RAM 38 is supplied to the selector 44, and the digital image signal D9 is supplied to the selector 45. Further, the secondary differential signal DIO read out from the three RAMs is supplied to the selector 44, and the digital image signal Dll is supplied to the selector 45. The selectors 44 and 45 also select and derive a signal from one of the RAMs in response to the switching signal SW from the terminal 48.

The output signal D12 of the selector 45 is supplied to a digital-to-analog converter 46, and is outputted to an output terminal 47 as a contour-corrected image signal D1B.

On the other hand, the output signal D 1.4 of the selector 44 is a second-order difference signal, which is supplied to the control terminal of the selector 50 .

The selector 50 selects one clock from a plurality of clocks with different phases according to a control signal (secondary difference signal), and supplies it to the clock input terminal of the read address generator 42. , to the clock input terminal of the digital-to-analog converter 46. The plurality of clocks are generated by supplying the clock CK supplied to the clock input terminal 51 to the delay elements 5]-1 to 5]n connected in series. Each delay element 511-51
The clocks of the human power section and the output section of n are supplied to the selector 50. Further, among the plurality of phase clocks, for example, the clock at the center position is used as the clock for the write address generator 41.

The present invention is constructed as described above, and the contour correction operation will be explained below with reference to FIG. 2.

2a in FIG. 2 shows sampling data of the contour portion of the digital image signal D1, and the contour portion is dull due to band limitation. 2b is the long signal of this part. Further, 2c represents the output signal of the ROM 37 and the selector 44.
This corresponds to the output second-order difference signal.

When the secondary difference signal becomes large, the selector 50 selects a clock whose phase is delayed according to the magnitude of the second-order difference signal and supplies this to the read address generator 42 and the digital-to-analog converter 46 as a clock. Conversely, when the secondary difference signal becomes smaller, a clock whose phase is advanced is selected and supplied as a clock to the read address generator 42 and the digital-to-analog converter 46. Therefore, in the illustrated example, the clock phase is modulated as shown at 2d. As a result, the contour portion 2e of the output image signal has a sharp change as shown in the figure, and the image contour can be made clear.

This invention described above does not simply emphasize high frequencies as in the prior art, so it does not cause the phenomena of overshoot and undertone. This circuit is capable of producing steep changes in the contour signal within a predetermined bit range.

(Effects of the Invention) As explained above, the present invention provides contour correction that can correct the blurring of the image contour caused by the band limitation of the transmission path without causing an unnatural feeling and without increasing the amount of hardware. The circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart shown to explain the invention in detail, FIG. 3 is a diagram showing a conventional digital contour correction circuit, and FIG. 4 is a diagram showing a conventional digital contour correction circuit. The figure is shown to explain the circuit of FIG. 3 (it is also a time chart. 32. 35... Unit delay element, 34... Absolute value circuit,
33.36...Subtractor, 37...ROM, 38.39
...RAM, 41...Write address generator, 42
. . . Activation address generator, 43, 44, 45° 50 . . . Selector, 46 . . . Digital-to-analog converter. Applicant's agent: Patent attorney Takehiko Suzue. 1 ;'iJA 4t j*';'I j in s 81
f. 2d i + + + j jJI
i j + + +○ 28. . . .・ . Mu7Jji'-Evening Figure 2

Claims (1)

[Claims] A first-order difference circuit that differentiates the input digital signal, an absolute value circuit that takes the absolute value of the output of this circuit, a second-order difference circuit that differentiates the output of this absolute value circuit, and the output of the second second-order difference circuit as input. a contour detection circuit comprising a nonlinear input/output characteristic circuit; storage means to which the digital signal and the output of the contour detection circuit are supplied; means for digital-to-analog conversion of the output of the storage means; and a clock input. means for creating a plurality of clocks with different phases; selecting and supplying a clock with an intermediate phase among the plurality of phase clocks as a clock to the write address generator of the storage means; The clock for the read address generator of the storage means is as follows:
When the output of the storage means is zero, a clock with an intermediate phase among the plurality of clocks is selected, and as the output of the storage means increases, one of the plurality of phases with a delayed phase is sequentially selected, and vice versa. A digital contour correction circuit comprising: a selector that sequentially selects and supplies one of the plurality of phases whose phase is advanced as the output of the storage means becomes smaller.