JPH08163510A - Video signal processing circuit - Google Patents

Abstract

PURPOSE: To minimize deterioration in image quality due to a fog of an image in the case of reduction while eliminating line flicker. CONSTITUTION: In the video signal processing circuit where a video signal from a personal computer is subject to reduction processing by a reduction circuit 2 and the reduced video signal is converted into a video signal of the interlace scanning NTSC system, a vertical direction use low pass filter 1 for line flicker prevention is inserted to a pre-stage of the reduction circuit 2 and a filter coefficient K of the low pass filter 1 is changed depending on the reduction rate. More concretely, the filter coefficient K is set larger depending on an increase in the reduction rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for subjecting an input first type video signal to reduction processing and converting the reduced video signal into an interlaced second type video signal. .

[0002]

2. Description of the Related Art In recent years, in the era of multimedia, a video signal of a personal computer, a high-definition television or the like is subjected to reduction processing, and the video signal after the reduction processing is converted to the standard television system NTSC system. There has been a demand for conversion into a video signal.

In such a circuit, the output N
Since the video signal of the TSC system is a signal for interlaced display, line flicker occurs, which causes deterioration of image quality. Therefore, conventionally, a vertical low-pass filter is provided in the preceding stage of the reduction processing circuit, and the line flicker is removed by this low-pass filter.

[0004]

The low-pass filter for preventing the line flicker described above reduces the resolution in the vertical direction. Therefore, if the filter coefficient is erroneously selected, the image becomes blurred and the image quality deteriorates. There is a fear. In addition, when the reduction processing is performed, the degree of influence of the line flicker varies depending on the reduction rate. Therefore, for example, even if the reduction rate close to 1/1 is displayed with high image quality,
When the reduction ratio increases to about 2, there arises a problem that image quality deterioration due to blurring becomes severe. However, in the conventional circuit configuration, the filter coefficient of the low pass filter is set to a fixed value.

[0005]

According to the present invention, a video signal of the first system is subjected to a reduction process by a reduction circuit, and the reduced video signal is converted into a video signal of the second system for interlaced display. In the video signal processing circuit, the above problem is solved by inserting a vertical low-pass filter for line flicker prevention in the preceding stage of the reduction circuit and changing the filter coefficient of the low-pass filter according to the reduction ratio. It is a thing.

Then, the present invention uses the filter coefficient
It is characterized in that it is set to a large value in accordance with an increase in the reduction rate.

[0007]

According to the present invention, since the filter coefficient changes according to the reduction ratio, the filter effect changes according to the reduction ratio, and the deterioration of the image quality due to the blurring of the image can be suppressed to the minimum.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Reference numeral 1 denotes a video signal from a non-interlaced personal computer which is input as a digital signal through an AD converter (not shown). Vertical low-pass filter,
Reference numeral 2 is a reduction circuit for performing reduction processing according to the reduction ratio on the video signal output from the low-pass filter 1, and reference numeral 3 is a frame memory 4 connected to the input synchronization signal of the personal computer and NT.
A scanning line conversion circuit for converting scanning lines on the basis of an SC synchronizing signal, a display control 5 for performing display control such as window display on the converted video signal and converting a digital video signal into an analog video signal for output. A circuit, 6 is a control circuit for controlling each circuit.

FIG. 2 is a specific circuit diagram of the low-pass filter 1. Here, a filter effect is obtained by weighting the signals of three lines in the vertical alignment of the n-1, n, and n + 1 lines, respectively. There are two delay elements 1 that delay the signal by one horizontal sync signal (1H).
0, 11 and signals of each line of n-1, n, n + 1,
Each of them is composed of multipliers 12, 13, 14 for multiplying multipliers of (1-K) / 2, K, (1-K) / 2, and an adder 15 for adding outputs of three multipliers. There is.

Therefore, when the coefficient K is 1, the filter effect disappears, and the filter effect increases as K gradually decreases from 1. Therefore, when the reduction ratio is designated to the control circuit 6 by the control signal, the control circuit 6 determines the coefficient K according to the designated reduction ratio, and determines the multiplier of the multiplier in the low-pass filter 1 based on the coefficient K. change. Specifically, K is increased in accordance with an increase in the reduction rate, and as a result, the filter effect is lost as the reduction rate increases. That is,
If K is constant, the image becomes more blurred as the reduction rate increases. However, in the embodiment, the filter effect is reduced as the reduction rate increases, so that the image blur is suppressed. Therefore, the deterioration of the image quality due to this blur is prevented.

As described above, in the low-pass filter 1, line flicker removal processing is performed on the input video signal so as to minimize the blurring of the image, and thereafter,
The reduction circuit 2 performs reduction processing according to the reduction ratio designated by the control unit 6. Next, the reduced video signal is subjected to scanning line conversion processing based on the synchronizing signal in the scanning line conversion circuit 3 by using the frame memory 4, and then reduced through the display control circuit 5 in the NTSC system. Is output as a video signal.

As a method of determining the coefficient K, a table in which the correspondence between the reduction ratio and K is registered may be prepared in advance and read from there, or a simple arithmetic circuit may be used. You may use. By the way, in the above-mentioned embodiment, an example in which the non-interlaced personal computer video output is converted into the NTSC interlaced video signal is not limited to this. Video signal is standard NTS
The present invention can be applied to the case of conversion into a C system interlaced video signal.

[0013]

According to the present invention, since the filter effect of the low-pass filter is changed according to the reduction ratio, it is possible to minimize the deterioration of the image quality due to the image blur while removing the line flicker. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a low-pass filter in the example.

[Explanation of symbols]

 1 Low-pass filter 2 Reduction circuit 3 Scan line conversion circuit 4 Frame memory 5 Display control circuit 6 Control circuit 10, 11 Delay element 12, 13, 14 Multiplier 15 Adder

Claims (2)

[Claims] 1. A video signal processing circuit for subjecting a video signal of a first system to reduction processing by a reduction circuit and converting the reduced video signal into a video signal of a second system interlaced for display. A video signal processing circuit, characterized in that a vertical low-pass filter for preventing line flicker is inserted in the preceding stage of the reduction circuit, and the filter coefficient of the low-pass filter is changed according to the reduction ratio. 2. The video signal processing circuit according to claim 1, wherein the filter coefficient is set to be large in accordance with an increase in the reduction rate.