JPS6320253U - - Google Patents
Info
- Publication number
- JPS6320253U JPS6320253U JP11141586U JP11141586U JPS6320253U JP S6320253 U JPS6320253 U JP S6320253U JP 11141586 U JP11141586 U JP 11141586U JP 11141586 U JP11141586 U JP 11141586U JP S6320253 U JPS6320253 U JP S6320253U
- Authority
- JP
- Japan
- Prior art keywords
- address
- signals
- data signals
- stored
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 claims 1
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Multi Processors (AREA)
Description
第１図はこの考案の実施例のブロツク図、第２
図は第１図のタイムチヤート、第３図は他の実施
例のブロツク図、第４，５図は従来のデータ伝送
装置の説明図である。
１，２……バツフア回路、３，４……ラツチ回
路、５……ランダムアクセスメモリ、８……ナン
ド回路、９，１２……インバータ。
Figure 1 is a block diagram of an embodiment of this invention;
The figures are a time chart of FIG. 1, FIG. 3 is a block diagram of another embodiment, and FIGS. 4 and 5 are explanatory diagrams of a conventional data transmission device. 1, 2... Buffer circuit, 3, 4... Latch circuit, 5... Random access memory, 8... NAND circuit, 9, 12... Inverter.
Claims (1)
信号と共に一時的に記憶保持するラツチ回路３，
４と、該ラツチ回路３，４に記憶保持されたデー
タ信号を書込みアドレス指定用のアドレス信号に
対応するアドレスに書込み記憶するランダムアク
セスメモリ５と、該ランダムアクセスメモリ５に
読出しアドレス指定用のアドレス信号を供給し該
アドレス信号に対応するアドレスに書込み記憶さ
れているデータ信号を読出し出力するバツフア回
路１，２と、前記ランダムアクセスメモリ５から
のデータ信号の読出しを検出しその検出時に該ラ
ンダムアクセスメモリ５へのデータ信号の書込み
を禁止する制御回路８，１２とを備えてなること
を特徴とするデータ伝送装置。 A latch circuit 3 that temporarily stores and holds the data signal together with the address signal for specifying the write address;
4, a random access memory 5 for writing and storing data signals stored and held in the latch circuits 3 and 4 at an address corresponding to an address signal for writing address designation; Buffer circuits 1 and 2 supply signals and read and output data signals written and stored at addresses corresponding to the address signals, and buffer circuits 1 and 2 detect reading of data signals from the random access memory 5 and upon detection, buffer circuits 1 and 2 read and output data signals written and stored at addresses corresponding to the address signals; A data transmission device comprising: control circuits 8 and 12 for inhibiting writing of data signals to memory 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11141586U JPH0248916Y2 (en) | 1986-07-22 | 1986-07-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11141586U JPH0248916Y2 (en) | 1986-07-22 | 1986-07-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6320253U true JPS6320253U (en) | 1988-02-10 |
| JPH0248916Y2 JPH0248916Y2 (en) | 1990-12-21 |
Family
ID=30991317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11141586U Expired JPH0248916Y2 (en) | 1986-07-22 | 1986-07-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0248916Y2 (en) |
-
1986
- 1986-07-22 JP JP11141586U patent/JPH0248916Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0248916Y2 (en) | 1990-12-21 |
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