JPS5958843U - Random access memory initialization circuit - Google Patents
Random access memory initialization circuitInfo
- Publication number
- JPS5958843U JPS5958843U JP15197082U JP15197082U JPS5958843U JP S5958843 U JPS5958843 U JP S5958843U JP 15197082 U JP15197082 U JP 15197082U JP 15197082 U JP15197082 U JP 15197082U JP S5958843 U JPS5958843 U JP S5958843U
- Authority
- JP
- Japan
- Prior art keywords
- random access
- access memory
- flop
- flip
- initialization circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、１フレ一ム分のビデオ信号を記憶するために
予め割当てられたエリア１、ビデオ信号の書込みが実際
に行われるエリア２、記憶内容が不定のまま残るエリア
３、ビデオ信号の読出しが一実際に行われるエリア２，
４を示す図、第２図は、本考案によるＲＡＭのイニシャ
ライズ回路の構成を示すブロック図である。
１１・・・・・・ＲＡＭ、１２・・・・・・アンドゲー
ト、１３・・・・・・書込みアドレス発生回路、１５・
・・用電源オンリセット回路、１６・・・・・・フリッ
プ・フロップ、ＣＲ・・・・・・キャリイ信号、ＲＰ・
・・・・・リセットパルス、ＷＤ・・・・・・書込みデ
ータ。Figure 1 shows area 1 allocated in advance to store one frame worth of video signal, area 2 where the video signal is actually written, area 3 where the stored content remains undefined, and area 3 where the video signal is stored. Area 2, where reading is actually performed;
4 and FIG. 2 are block diagrams showing the configuration of a RAM initialization circuit according to the present invention. 11...RAM, 12...AND gate, 13...Write address generation circuit, 15...
...power-on reset circuit, 16...flip-flop, CR...carry signal, RP...
...Reset pulse, WD...Write data.
Claims (1)
を発生すや電源オンリセット回路と、前記リセットパル
スによってセットされるフリップ・フロップと、前記フ
リップ・フロップがセット状態中、書込みデータをイン
ヒビットするアンドケートと、前記フリップ・フロップ
がセット状態中先頭番地から順次アドレスを指定し、前
記アンドゲートの出力信号の書込みを行い、最終番地の
書込みが終るとキャリイ信号を出力し、これによって前
記フリップ・フロップをリセットする書込みアドレス発
生面路とを具備することを特徴とするランダムアクセス
メモリのイニシャライズ回廣Ｖa power-on reset circuit that generates a reset pulse when the random access memory is powered on; a flip-flop that is set by the reset pulse; and an AND gate that inhibits write data while the flip-flop is set; While the flip-flop is in a set state, addresses are specified sequentially from the first address, the output signal of the AND gate is written, and when the writing of the final address is completed, a carry signal is output, thereby resetting the flip-flop. Initializing circuit V of a random access memory characterized by comprising an address generation surface path
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15197082U JPS5958843U (en) | 1982-10-06 | 1982-10-06 | Random access memory initialization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15197082U JPS5958843U (en) | 1982-10-06 | 1982-10-06 | Random access memory initialization circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5958843U true JPS5958843U (en) | 1984-04-17 |
Family
ID=30336615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15197082U Pending JPS5958843U (en) | 1982-10-06 | 1982-10-06 | Random access memory initialization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5958843U (en) |
-
1982
- 1982-10-06 JP JP15197082U patent/JPS5958843U/en active Pending
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