JPS6044298U - memory write circuit - Google Patents
memory write circuitInfo
- Publication number
- JPS6044298U JPS6044298U JP13622383U JP13622383U JPS6044298U JP S6044298 U JPS6044298 U JP S6044298U JP 13622383 U JP13622383 U JP 13622383U JP 13622383 U JP13622383 U JP 13622383U JP S6044298 U JPS6044298 U JP S6044298U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- circuit
- write
- output
- latch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例に係るメモリ書込み回路のブ
ロック図、第２図はそのタイミングチャート、第３図は
第１図のブロック図に対応する詳細回路の例である。
１：メモリ、２ニアドレスラッチ回路、３：データラッ
チ回路、４：比較回路、５：読出し／書込み制御回路、
Ｓｌ：ラッチ信号、Ｓ２：外部信号、Ｓ′２：読出し／
書込み制御信号、Ｓ３：比較結果要求信号、Ｓ４：比較
結果一致信号、Ｓ５：比較結果不一致信号、Ｓ６：デー
タ書込み中表示信号。FIG. 1 is a block diagram of a memory write circuit according to an embodiment of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is an example of a detailed circuit corresponding to the block diagram of FIG. 1. 1: memory, 2 near address latch circuit, 3: data latch circuit, 4: comparison circuit, 5: read/write control circuit,
SL: Latch signal, S2: External signal, S'2: Read/
Write control signal, S3: Comparison result request signal, S4: Comparison result match signal, S5: Comparison result mismatch signal, S6: Data writing in progress display signal.
Claims (1)
レスラッチ回路と、メモリへの書込みデータをラッチす
るデータラッチ回路と、データラッチ回路の出力とメモ
リの読出し出力を比較する比較回路と、外部信号に応じ
てメモリの書込み、読出しを制御する制御信号を出力す
るとともに比較回路の比較結果を示す信号を入力してデ
ータラッチ回路の出力とメモリの読出し出力が一致する
までメモリへの書込みを行なう制御信号を出力する読出
し／書込み制御回路とを備えることを特徴とするメモリ
書込み回路。A memory, an address latch circuit that latches the write address to the memory, a data latch circuit that latches the write data to the memory, a comparison circuit that compares the output of the data latch circuit and the read output of the memory, and a outputs a control signal to control writing and reading of the memory, and inputs a signal indicating the comparison result of the comparator circuit, and outputs a control signal to write to the memory until the output of the data latch circuit and the read output of the memory match. A memory write circuit comprising: a read/write control circuit that outputs an output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13622383U JPS6044298U (en) | 1983-09-02 | 1983-09-02 | memory write circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13622383U JPS6044298U (en) | 1983-09-02 | 1983-09-02 | memory write circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6044298U true JPS6044298U (en) | 1985-03-28 |
Family
ID=30306362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13622383U Pending JPS6044298U (en) | 1983-09-02 | 1983-09-02 | memory write circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6044298U (en) |
-
1983
- 1983-09-02 JP JP13622383U patent/JPS6044298U/en active Pending
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