JPS6267919A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To realize a flip-flop without requiring an analog trigger pulse generator and inhibition input by using logic circuits only so as to constitute a flip-flop circuit. CONSTITUTION:The flip-flop circuit consists of a master flip-flop 1, slave flip- flops 22, 23, invertes 24, 25 and AND gates 26, 27 for input transfer. When a set signal S0 changes from L to H, the output of a AND gate 26 changes from L via H into L. Further, the output of the AND gate 27 goes from L via H into L in response to a reset signal R0 changed from L to H. Thus, since a pulse input is fed to input terminals R, S of the master flip-flop 1, no inhibition input exists in signals R0, S0. Further, it is known that the width of the input pulse at terminals R, S is the minimum time completing the circuit operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a flip-flop circuit driven by the edges of its input.

[Prior Art 1] Conventionally, in this type of flip-flop circuit, a trigger signal is formed at a rising edge or a falling edge of an input, and the trigger signal drives the set or reset of the flip-flop.

FIG. 3 shows an example of the circuit configuration. In the figure, l is an R-S flip-flop. 2 and 3 are respectively Sera I.
and a reset trigger signal generator, which generates l-trigger pulses S and R on the rising edge of the set and reset input signals R0 and So, respectively, as shown in FIG. These trigger pulses S and R are R-
By inputting S flip-flop 1, R, S
This flip-flop l can disable such simultaneous inputs without providing a circuit for disabling simultaneous inputs. That is, flip-flop l receives signals R,,S
Viewed from o, it operates on the Xrl-reset of each trigger pulse, and thus the signal S at the set and reset terminals at the same time. Even if , RO is input, the flip-flop output is uniquely determined as long as the edges of both signals do not match, and the flip-flop output is uniquely determined.

This type of trigger pulse generator 2, 3 uses a circuit that uses a capacitor and differentiates the input signal to generate a trigger pulse, or a circuit that uses a capacitor to generate a trigger pulse, or Japanese Patent Publication No. 58-8811 or Japanese Utility Model Publication No. 57-5
There are circuits such as those proposed in No. 0823.

FIG. 5 shows an example using the above-described capacitor, in which a human input signal So is supplied to a differential circuit composed of a capacitor 4 and a resistor 5, and a trigger pulse S is generated (-I).

FIG. 6 shows the circuit of Japanese Patent Publication No. 58-8 [i11], where 6 is an I2L injection PNP) transistor, and 7 to 12 are NPN) transistors.

Figure 7 shows the circuit of Jikko [\(57-50823),
Here, 13 to 15 are NPN transistors, 16 to 21
is resistance.

In this method of driving a flip-flop using a trigger pulse, the width of the pulse is designed to be wide, taking into account the S delay time of the flip-flop, but in this case, the pulse time must be secured, including variations. It is necessary to
As a result, the input signal S. The overall delay time until the flip-flop outputs Q and Q are obtained becomes longer than +RO. Further, the circuit configurations shown in FIGS. 5 to 7 are inappropriate for incorporating into various digital ICs for integral integration.

[Problem 1 to be Solved by the Invention Therefore, 1-1 of the present invention is to consider the rise or fall of the set or reset input as the true value without using the trigger pulse as described in 11 - To provide a low-cost flip-flop circuit suitably constructed only with logic circuits that do not require human power.

[Means for solving the problem 1] In order to achieve such a goal, the present invention uses only a logic circuit to control the rising or falling edge of a set or reset input without using a trigger pulse generator. An R-S flip-flop circuit driven by the edge of is constructed.

That is, the present invention includes a main flip-flop, a first slave flip-flop that stores a first output state of the main flip-flop and controls a set input of the main flip-flop, and a second output state of the main flip-flop. , and a second slave flip-flop that controls the reset input of the master flip-flop, and is supplied with a set signal for the master flip-flop and an output of the first slave flip-flop, and only if the set signal is valid for the master flip-flop. A first gate circuit supplies the set signal to the set input terminal of the main flip-flop, and is supplied with a reset signal for the main flip-flop and the output of the second slave flip-flop, so that the reset signal is effective for the main flip-flop. and a second gate circuit that supplies the reset signal to the reset input terminal of the main flip-flop only when the flip-flop is in use.

[Sakukawa 1] According to the present invention, the main flip-flops R and S are configured so that they do not inhibit each other. Moreover, since the flip-flop of the present invention operates in real time, the delay time, which was considered a drawback of the prior art, can be operated in real time.Furthermore, since it is composed entirely of logic circuits, it can be applied to a variety of logic integrated circuits.

According to the present invention, a flip-flop circuit is constructed only by a logic circuit, and an edge-trigger type flip-flop without inhibited IL input can be constructed without requiring an analog trigger pulse generator. Moreover, since it has a configuration consisting only of logic circuits, it can be inexpensively integrated into various digital IC forms such as 0MO3, I2L, and TTL.

[Example] The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the flip-flop circuit of the present invention. In FIG. 1, this flip-flop circuit is composed of a main flip-flop 1, slave flip-flops 22 and 23, inverters 24 and 25, and AND gates 26 and 27 for input transfer. Flip-flops l, 22 and 23 are all R-S flip-flops, and supply the Q and Q outputs of main flip-flop l to reset input terminals R1 and R2 of slave flip-flops 22 and 23, respectively. Set and reset signals SO and RO are supplied to set input terminals St and S2 of slave flip-flops 22 and 23 via inverters 24 and 25, respectively.

The set signal S0 and the Ql output of the secondary flip-flop 22 are supplied to an AND gate 26, and the AND output is supplied to the set input element S of the main flip-flop 1.

Reset signal R0 and 02 of slave flip-flop 23
The output is supplied to the AND gate 27, and the AND output is supplied to the reset input terminal H of the main flip-flop 1.

Here, the slave flip-flops 22 and 23 are connected to the signals So and R supplied to the input transfer gates 2B and 27.
8 to each corresponding input terminal S and H of the main flip-flop l.

Pretending the above configuration 1. Flop circuit number 6, A, set signal S. When is L, S, =H, Q, =H. Here, if the Q output is H, when the set signal So becomes H, S! As a result, Ql becomes L, the output of AND gate 2B remains L, and no H signal is generated at the set input terminal S. On the other hand, if the Q output is L, when the set signal So changes from L to H, Ql remains H, the output of the AND gate 26 changes from L to H, the main flip-flop l is set, and its output Q goes from L to H. As Q becomes H in this way, the output Q+ of the slave flip-flop 22 becomes L, and the AND gate 2B
The output of becomes L. That is, when the save signal So changes from L to H, the output of the AND gate 26 goes from H to H.
After that, it becomes L. The above operation similarly applies to the input on the reset signal R0 side, and in response to the reset signal R8 changing from ■ to H, the outputs J and I of the AND gate 27 change from L to L via II. Become. Therefore, since pulse-like inputs are supplied to the input terminals R and S of the 1: flip-flop l, the input terminals R and S of the flip-flop l are
Human power does not exist. Furthermore, it can be seen that the width of the human pulse at terminals R and S is the minimum time for the circuit operation to complete.

As described above, since the flip-flop circuit of the present invention can be constructed from logic circuits, it can be implemented in various configurations. FIG. 2 shows a concrete example thereof.

This example also has a main flip-flop l, slave flip-flops 22 and 23, and Nant gates 28 and 28 as input transfer gates, as in the case of FIG. Here, each of the flip-flops 1, 22 and 23 are all constructed of Nant gates, therefore, the inverters 24 and 25 in FIG. 1 are omitted, and the AND gate 2 in FIG.
Nant gates 28 and 28 are provided in place of 6 and 27. Here, the signals So and Ro and the Q and Q outputs of the main flip-flop l are supplied to the slave flip-flops 22 and 23, respectively.

[Effects of the Invention 1] According to the present invention, a flip-flop circuit is configured only with a logic circuit, and an edge-trigger type flip-flop can be configured without requiring an analog trigger pulse generator. . Moreover, since it has a configuration consisting only of logic circuits, it can be inexpensively integrated into various digital IC formats such as 0MO8, I2L, and TTL.

[Brief explanation of drawings]

Fig. 1 is a logic circuit diagram showing an embodiment of the flip-flop circuit of the present invention, Fig. 2 is a logic circuit diagram showing an embodiment of its specific circuit configuration, and Fig. 3 is an example of a conventional flip-flop circuit. 4 is a signal waveform diagram of each part thereof, and FIGS. 5 to 7 are circuit diagrams showing three examples of conventional pulse generators. 1... Main flip-flop 2-3... Trigger pulse generator, So, R,, S, R, Q, mouth... Shingin, 4... Capacitor, 5.16-21...・Resistance, 6.15...PNP) transistor, 7~14...
・NPN transistor, 22.23... Slave flip-flop, 24.25... Inverter, 28.27... AND gate for input transfer, 28.29
... Nantes gate for input transfer. Original I3 Tantenshi Ikuri's Theory f A Schematic Diagram Original Sun Moon Tsure 1 and ul + ↓ Life Extinction Circuit (to the sword ■ 0
Figure 4 Schematic diagram of the signal diagram of the row A. Figure 7.

Claims (1)

[Scope of Claims] A main flip-flop, a first slave flip-flop that stores a first output state of the main flip-flop and controls a set input of the main flip-flop, and a second output of the main flip-flop. remember the state,
and a second slave flip-flop that controls the reset input of the main flip-flop; and a set signal for the main flip-flop and the first slave flip-flop.
a first gate circuit that is supplied with the output of the secondary flip-flop and supplies the set signal to the set input terminal of the main flip-flop only when the set signal is valid for the main flip-flop; a reset signal for the primary flip-flop and the output of the second slave flip-flop, and supplies the reset signal to the reset input terminal of the primary flip-flop only when the reset signal is valid for the primary flip-flop; A flip-flop circuit characterized by comprising a two-gate circuit.