JPS52144253A - Flip-flop circuit - Google Patents
Flip-flop circuitInfo
- Publication number
- JPS52144253A JPS52144253A JP6205776A JP6205776A JPS52144253A JP S52144253 A JPS52144253 A JP S52144253A JP 6205776 A JP6205776 A JP 6205776A JP 6205776 A JP6205776 A JP 6205776A JP S52144253 A JPS52144253 A JP S52144253A
- Authority
- JP
- Japan
- Prior art keywords
- input
- flip
- flop circuit
- selection
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
Abstract
PURPOSE:To have an exclusive selection for the partner side input of the input read right before in order to eliminate the input waveform limitation and thus to obtain an FF free from the inhibition state, by providing both input memory circuit and input selection circuit to the two input circuits of R-SFF.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6205776A JPS52144253A (en) | 1976-05-27 | 1976-05-27 | Flip-flop circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6205776A JPS52144253A (en) | 1976-05-27 | 1976-05-27 | Flip-flop circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS52144253A true JPS52144253A (en) | 1977-12-01 |
JPS5737249B2 JPS5737249B2 (en) | 1982-08-09 |
Family
ID=13189121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6205776A Granted JPS52144253A (en) | 1976-05-27 | 1976-05-27 | Flip-flop circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS52144253A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6267919A (en) * | 1985-09-19 | 1987-03-27 | Fuji Electric Co Ltd | Flip-flop circuit |
JPS6281113A (en) * | 1985-10-03 | 1987-04-14 | Fujitsu Ltd | Latch circuit |
JP2018054628A (en) * | 2012-03-28 | 2018-04-05 | テラダイン・インコーポレーテッドTeradyne Incorporated | Edge-triggered calibration |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4891849U (en) * | 1972-02-04 | 1973-11-05 |
-
1976
- 1976-05-27 JP JP6205776A patent/JPS52144253A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4891849U (en) * | 1972-02-04 | 1973-11-05 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6267919A (en) * | 1985-09-19 | 1987-03-27 | Fuji Electric Co Ltd | Flip-flop circuit |
JPS6281113A (en) * | 1985-10-03 | 1987-04-14 | Fujitsu Ltd | Latch circuit |
JP2018054628A (en) * | 2012-03-28 | 2018-04-05 | テラダイン・インコーポレーテッドTeradyne Incorporated | Edge-triggered calibration |
Also Published As
Publication number | Publication date |
---|---|
JPS5737249B2 (en) | 1982-08-09 |
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