JPS62115752A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62115752A JPS62115752A JP60254801A JP25480185A JPS62115752A JP S62115752 A JPS62115752 A JP S62115752A JP 60254801 A JP60254801 A JP 60254801A JP 25480185 A JP25480185 A JP 25480185A JP S62115752 A JPS62115752 A JP S62115752A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- resin
- center
- dimples
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、％ｋ、レジンクラックの発
生や樹脂とリードフレームとの界面剥離を防止した樹脂
封止型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device that prevents occurrence of resin cracks and peeling at the interface between the resin and a lead frame.
一般に、リードフレームな利用した樹脂封止型半導体装
置は、その主要工程として、該フレームの半導体チップ
を搭載する部分であるタブ（ダイアタッチ部）上に当該
チップを固着させ、該チップと前記フレームのリードと
をコネクタワイヤにより結線し、樹脂モールドすること
により得られている。In general, the main process of a resin-sealed semiconductor device using a lead frame is to fix the chip on a tab (die attach part), which is the part of the frame on which the semiconductor chip is mounted, and then attach the chip to the frame. It is obtained by connecting the leads with connector wires and molding them with resin.
当該リードフレームは、一般に、金属より成っている。The lead frame is generally made of metal.
一方、かかる金属製リードフレーム（無機物）に対して
モールドされる樹脂は有機物であって、両者の本質的な
差異や熱膨張係数の差異などにより、これらリードフレ
ームとモールド樹脂（レジン）との界面に剥離を生じた
り、レジンにクランクを生じさせたりする。On the other hand, the resin molded onto such a metal lead frame (inorganic substance) is an organic substance, and due to the essential difference between the two and the difference in coefficient of thermal expansion, the interface between the lead frame and the mold resin (resin) This may cause peeling or cracking in the resin.
そこで、モールド樹脂のリードフレームに対する接着性
の向上などを目的として、タブに多数の凹孔（ディンプ
ル）Ｊ４Ｆ貫通孔を設けたりすることが行われている。Therefore, for the purpose of improving the adhesion of the mold resin to the lead frame, a large number of dimples (J4F through holes) are provided in the tab.
しかし、本発明者らの検討によれば、例えばディンプル
をタブの全面に設けた場合樹脂との接着性は向上するが
、高低温温度サイクル試験にかけると、かかる形態では
熱応力の逃げ場がなくタブの四隅（コーナー）！１１に
その応力が集中し、当該コーナ一部にレジンクラックが
生じることが判った。However, according to the studies of the present inventors, for example, if dimples are provided on the entire surface of the tab, the adhesion with the resin improves, but when subjected to high and low temperature temperature cycle tests, such a form has no place for thermal stress to escape. The four corners of the tab! It was found that the stress was concentrated at No. 11 and resin cracks were generated at a portion of the corner.
一方、タブの周辺部にのみ当該ディンプル加工Ｙ！した
ものについて同様に試験したところ、タブの当該周辺部
ではレジンとの間で強固な接着が行われているのに、中
心部のディンプル加工の行われていない部分ではタブが
７ラツトな面でレジンと接しており、このような場合に
は、タブ中心に向かって応力が集中するようになり、周
辺から次第に中心部へと界面剥離が生じることが判った
。On the other hand, the dimple processing is done only on the periphery of the tab! When a similar test was conducted on a tab with a dimpled surface, it was found that although there was strong adhesion between the resin and the surrounding area of the tab, the tab had a flat surface in the central area where the dimple processing was not performed. It was found that in such a case, stress would be concentrated toward the center of the tab, and interfacial peeling would occur gradually from the periphery to the center.
なお、タブ（ダイアタッチ部）に凹孔なとを設ける技術
について詳しく述べた特許の例として、特開昭５７−６
０８６０号、同５８−１４５５７号、同５６−１０４４
５８号、同５９−８６２５１号公報などがある。In addition, as an example of a patent that describes in detail the technology of providing a recessed hole in a tab (die attachment part), Japanese Patent Laid-Open No. 57-6
No. 0860, No. 58-14557, No. 56-1044
No. 58, No. 59-86251, etc.
本発明はレジンとリードフレームのタブとの接着面にお
ける界面剥ｆｉを防し、レジンクラックの発生を阻止す
る技術を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for preventing interfacial peeling at the adhesive surface between a resin and a tab of a lead frame, and preventing resin cracks from occurring.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきもかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will be clear from the description herein and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明では、全面に多数のディンプル加工を
施すのではなく、また、周辺部にのみ多数のディンプル
加工を施すのではなく、周辺部にディンプル加工を施す
ことにその内部空間に適切なディンプル加工を施したこ
とにある。That is, in the present invention, instead of applying a large number of dimples to the entire surface or applying a large number of dimples only to the peripheral area, the present invention does not apply a large number of dimples to the entire surface. This is because it has been processed.
すなわち、全面にディンプル加工を施す場合にはタブの
各コーナ一部に応力が集中し応力のバランスを欠くし、
また、周辺部のみにディンプル加工を施す場合にはタブ
中心に向かって応力が集中し、応力のバランスを欠くの
で、本発明ではかかる欠点を解消すべく応力のバランス
のとれたディンプル加工ヲ施すようにした。これにより
レジンとリードフレームのタブとの間の界面剥離やレジ
ンクラックを生じない樹脂封止型半導体装置を得ること
に成功した。In other words, when dimples are applied to the entire surface of the tab, stress is concentrated on a portion of each corner of the tab, resulting in an imbalance of stress.
Furthermore, if dimples are applied only to the periphery, stress will concentrate toward the center of the tab and the stress will be unbalanced.In order to eliminate this drawback, the present invention attempts to perform dimples with well-balanced stress. I made it. As a result, we succeeded in obtaining a resin-sealed semiconductor device that does not cause interfacial peeling or resin cracks between the resin and the tab of the lead frame.
し実施例〕 次に、本発明の実施例を、図面に基づいて説明する。Example] Next, embodiments of the present invention will be described based on the drawings.
第３図はリードフレームの一例平面図で、当該リードフ
レーム１は、その略中夫に半導体素子を搭載する部分で
あるタブ２と該タブ２の外周に配さ才したり−ド３と該
タブを支持しているタブ吊りリード４と樹脂封止の際の
樹脂の流れを止めるなどの目的で設けられているダム５
と枠６とを備えて成っている。FIG. 3 is a plan view of an example of a lead frame, in which the lead frame 1 has a tab 2, which is a portion on which a semiconductor element is mounted approximately in the middle, and a board 3 arranged around the outer periphery of the tab 2. A tab suspension lead 4 supporting the tab and a dam 5 provided for the purpose of stopping the flow of resin during resin sealing.
and a frame 6.
第４図は当該タブ２の拡大図で、同図にて、４は上記の
ごとくタブ吊りリードである。FIG. 4 is an enlarged view of the tab 2, and in the same figure, 4 is the tab suspension lead as described above.
タブ２は長方形などの方形に形成され、ここでは長方形
状のタブを例示しである。The tab 2 is formed into a rectangular shape, such as a rectangle, and a rectangular tab is shown here as an example.
タブ２の中心を含む適宜の太ぎさのエリア７内はこの第
４図では空間とし曵おり、その周辺部８には多数のディ
ンプル９を設けている。An area 7 of an appropriate thickness including the center of the tab 2 is drawn as a space in FIG. 4, and a large number of dimples 9 are provided around the area 8.
本発明ではかかる周辺部８に多数のディンプル９を設け
て成るタブ２において、当該エリア７内に、前記のごと
く応力のバランスをとるために、適切にディンプル加工
を施す。In the present invention, in the tab 2 having a large number of dimples 9 in the peripheral portion 8, dimples are appropriately processed in the area 7 in order to balance stress as described above.
次に、これを、第５図〜第１３図に図示した例に従い説
明する。Next, this will be explained according to the examples illustrated in FIGS. 5 to 13.
第５図に示すように、タブの横方向中心！！１１０と同
縦方向中心線１１と対角線１２．１３と？想定する。As shown in Figure 5, the horizontal center of the tab! ! 110 and the same vertical center line 11 and diagonal line 12.13? Suppose.
これら線の交わる叉点１４はタブの中心をなす。The intersection point 14 of these lines forms the center of the tab.
第−例として、第６図および第７図に示すように、叉点
１４にディンプル９を設けるとともに・備中心線１０上
に等間隔にディンプル９を設け、かつ、縦中心ｉｌｌ上
にも等間隔にディンプル９を設ける。As an example, as shown in FIGS. 6 and 7, dimples 9 are provided at the fork points 14, and dimples 9 are provided at equal intervals on the center line 10, and also on the vertical center ill. Dimples 9 are provided at intervals.
第二例は、第８図および第９図に示すように、対角線１
２及び１３上に上記と同様にしてディンプル９を設ける
。In the second example, as shown in FIGS. 8 and 9, the diagonal 1
Dimples 9 are provided on 2 and 13 in the same manner as above.
第三例は、第１０図および第１１図に示すように、横縁
中心１ｉＡ１０．１１のみならず、対角線１２．１３上
にも同様にディンプル９を設けた例を示す。The third example shows an example in which dimples 9 are provided not only at the center of the lateral edge 1iA10.11 but also on the diagonal line 12.13, as shown in FIGS. 10 and 11.
第四例は、第１２図に示すように、叉点１４にディンプ
ル９を設けるとともに、横縦中心線１０゜１１及び対角
線１２．１３上にもディンプル９を設け、これら線１０
．１１，１２．１３上のディンプル９を仮に結ぶと円を
構成するようになっている。In the fourth example, as shown in FIG.
．． If the dimples 9 on 11, 12, and 13 are tied together, they will form a circle.
第五例は、第１３図に示すよ５に、上記に加えてさらに
円を構成するディンプル９を第四例に示すディンプル９
の外部に配設したものである。In the fifth example, as shown in FIG.
It is placed outside the .
第六例は第１４図に示すようにディンプル９の平面サイ
ズを檜々変えて設けた例を示したもので第１５図は同上
のディ／グルの断面を示したものである。The sixth example shows an example in which the dimples 9 are provided with different planar sizes as shown in FIG. 14, and FIG. 15 shows a cross section of the same dimple.
このように、本発明では叉点１４にディンプル９を形成
するとともに、当該中心線１０．１１および／または対
角Ｍ１２，１３上にディンプル９を形成する。As described above, in the present invention, the dimple 9 is formed at the fork point 14, and the dimple 9 is formed on the center line 10.11 and/or the diagonals M12, 13.
第１図は上記第１例による本発明のタブの拡大平面′図
であり、タブ２０周辺部８にディンプル９が設けられて
いるとともに、当該周辺部８内部のエリア７にはタブの
縦横中央線上にディンプル９が設けられている。第２図
はタブの対角線上で切断した断面図である。FIG. 1 is an enlarged plan view of the tab of the present invention according to the first example, in which a dimple 9 is provided in the peripheral part 8 of the tab 20, and an area 7 inside the peripheral part 8 is located at the vertical and horizontal center of the tab. A dimple 9 is provided on the line. FIG. 2 is a cross-sectional view taken along the diagonal line of the tab.
本発明による応力集中について第１６図〜第１８図に基
づいて説明するに、第１７図に示すようにディンプルを
全面に施した場合は各コーナ一部に応力が集中する。ま
た、第１８図に示すようにディンプルを周辺部のみに設
けたときは中心に向かって応力が集中する。Stress concentration according to the present invention will be explained based on FIGS. 16 to 18. When dimples are applied to the entire surface as shown in FIG. 17, stress is concentrated at a portion of each corner. Furthermore, when dimples are provided only on the periphery as shown in FIG. 18, stress concentrates toward the center.
これに対し、本発明では第１６図に示すように、各コー
ナ一部のみに応力が集中したり、あるいは中心に向かっ
てのみ応力が集中したすせず応力のバランスをとること
ができる。On the other hand, in the present invention, as shown in FIG. 16, it is possible to balance stress that is concentrated only at a portion of each corner or concentrated only toward the center.
第１９図は本発明に係る樹脂封止型半導体装置の一例断
面図であり、同図にて、１５は半纏体テップ、１６はコ
ネクタワイヤ、１７は接合材料を示す。FIG. 19 is a cross-sectional view of an example of the resin-sealed semiconductor device according to the present invention. In the figure, 15 indicates a half-wrapped tip, 16 indicates a connector wire, and 17 indicates a bonding material.
本発明によれば上述のごとく応力のバランスがとれた半
導体装置が得られるので、レジンとリードフレームとの
界面剥離の発生を阻止し、また、レジンクラックを防止
でざる。According to the present invention, a semiconductor device with well-balanced stress as described above can be obtained, thereby preventing the occurrence of interfacial peeling between the resin and the lead frame, and also preventing resin cracks.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で櫛々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, it is to be understood that the present invention is not limited to the above-mentioned examples, and can be modified without departing from the gist thereof. Not even.
例えば、前記実施例ではディンプル（凹孔ンをタブの片
面にのみ設ける例を示したが両面でもよい。For example, in the embodiment described above, dimples (recessed holes) are provided only on one side of the tab, but they may be provided on both sides.
また、ディンプル加工の例を示したが、貫通孔でもよい
。Further, although an example of dimple processing is shown, a through hole may also be used.
また、これら孔の太ささ、形状は円形でも、細条角形な
ど任意である。Further, the thickness and shape of these holes may be arbitrary, such as circular or striped rectangular.
本発明は樹脂で刺止するタイプの樹脂封止型半導体装置
全般に適用できるが、半田付などによる実装の際に、装
置に熱がかかる面付は実装タイプの樹脂封止型半導体装
置に特に有効である。Although the present invention can be applied to all types of resin-sealed semiconductor devices that are pierced with resin, it is particularly applicable to surface-mounted resin-sealed semiconductor devices that expose the device to heat during mounting by soldering or the like. It is valid.
第１図は本発明の実施例を示す要部平面図、第２図は同
断面図、
第３図は本発明に使用されるリードフレームの一例平面
図、
第４図はタブの説明図、
第５図は本発明におけるディンプルの配置説明図、
第６図は同配置の一例説明図、
第７図同具体例を示す説明図、
第８図は同配−の他の一例説明図、
第９図は同具体例を示す説明図、
１１ｇ１Ｏ図は同配置のさらに他の一例説明図、第１１
図は同具体列を示す説明図、
第１２図は同配置のさらに他の一例説明図、第１３図は
同配置のさらに他の一例説明図、第１４図は具体例を示
す説明図、
第１５図は同断面図、
第１６図は本発明の作用効果を示す説明図、第１７図は
従来例による作用効果を示す説明図、第１８図は従来例
による作用効果を示す説明図、第１９図は樹脂封止型半
導体装置の一例断面図である。
１・・・リードフレーム、２・・・タブ、３・・・す・
−ド、４・・・タブ吊りリード、５・・・ダム、６・・
・枠、７・・・空間（エリア）、８・・・周辺部、９・
・・ディンプル、ｌＯ・・・タブ横方向中心線、１１・
・・タブ横縦方向中心線、１２・・・対角線、１３・・
・対角線、１４・・・交点、１５・・・半導体チップ、
１６・・・コネクタワイヤ、１７・・・接合材料。
第 １ 図
ダ
第 ２ 図
′ 第 ３ 図
瞥
第 ４ 図
第 ５ 図
第 １４ 図
第 １５ 図
第１６図Fig. 1 is a plan view of a main part showing an embodiment of the present invention, Fig. 2 is a sectional view thereof, Fig. 3 is a plan view of an example of a lead frame used in the present invention, Fig. 4 is an explanatory diagram of a tab, FIG. 5 is an explanatory diagram of the arrangement of dimples in the present invention; FIG. 6 is an explanatory diagram of an example of the same arrangement; FIG. 7 is an explanatory diagram showing a specific example of the same arrangement; FIG. 8 is an explanatory diagram of another example of the same arrangement; Figure 9 is an explanatory diagram showing the same specific example, Figure 11g1O is an explanatory diagram of yet another example of the same arrangement, No. 11
12 is an explanatory diagram showing yet another example of the same arrangement; FIG. 13 is an explanatory diagram showing still another example of the same arrangement; FIG. 14 is an explanatory diagram showing a concrete example; 15 is a sectional view of the same, FIG. 16 is an explanatory diagram showing the effects of the present invention, FIG. 17 is an explanatory diagram showing the effects of the conventional example, FIG. 18 is an explanatory diagram showing the effects of the conventional example, FIG. 19 is a sectional view of an example of a resin-sealed semiconductor device. 1...Lead frame, 2...Tab, 3...S...
- lead, 4... tab suspension lead, 5... dam, 6...
・Frame, 7...Space (area), 8...Periphery, 9.
... Dimple, lO ... Tab horizontal center line, 11.
...Tab horizontal and vertical center line, 12...Diagonal line, 13...
・Diagonal line, 14...intersection, 15...semiconductor chip,
16...Connector wire, 17...Joining material. Figure 1 Figure 2' Figure 3 Figure 4 Figure 5 Figure 14 Figure 15 Figure 16
Claims (1)
該チップの各電極と前記リードフレームのリードとを結
線し、樹脂封止して成る半導体装置において、前記タブ
の中心を含む適宜エリアを空間とし、該エリア周辺部に
多数の凹孔および／または透孔を設け、かつ、前記エリ
アには、タブの縦横中心線及び対角線を想定したときに
、これら中心線及び対角線の交点に前記凹孔または透孔
を設けるとともに、これら中心線および／または対角線
上に適宜個数の当該凹孔および／または透孔を設けて成
ることを特徴とする樹脂封止型半導体装置。 ２、タブの中心に凹孔および／または透孔を設けるとと
もに、タブの縦横中央線上に一定間隔で凹孔および／ま
たは透孔を設けて成る特許請求の範囲第１項記載の樹脂
封止型半導体装置。[Claims] 1. A semiconductor chip is mounted on a tab of a lead frame,
In a semiconductor device in which each electrode of the chip is connected to a lead of the lead frame and sealed with resin, an appropriate area including the center of the tab is a space, and a large number of recesses and/or holes are formed around the area. A through hole is provided in the area, and the recessed hole or through hole is provided in the area at the intersection of the vertical and horizontal center lines and diagonal lines of the tab, and these center lines and/or diagonal lines are provided. 1. A resin-sealed semiconductor device comprising an appropriate number of recesses and/or through holes provided thereon. 2. The resin-sealed mold according to claim 1, wherein a recessed hole and/or a through hole are provided in the center of the tab, and recessed holes and/or through holes are provided at regular intervals on the vertical and horizontal center lines of the tab. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60254801A JPS62115752A (en) | 1985-11-15 | 1985-11-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60254801A JPS62115752A (en) | 1985-11-15 | 1985-11-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62115752A true JPS62115752A (en) | 1987-05-27 |
Family
ID=17270079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60254801A Pending JPS62115752A (en) | 1985-11-15 | 1985-11-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62115752A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4910577A (en) * | 1987-08-10 | 1990-03-20 | Kabushiki Kaisha Toshiba | Lead frame |
| KR100499606B1 (en) * | 2000-06-13 | 2005-07-07 | 앰코 테크놀로지 코리아 주식회사 | Substrate for manufacturing semiconductor package |
| JP2008159742A (en) * | 2006-12-22 | 2008-07-10 | Fujitsu Component Ltd | Mounting structure of semiconductor element |
| DE102011016566A1 (en) * | 2011-03-07 | 2012-09-13 | Osram Opto Semiconductors Gmbh | Lead frame for optoelectronic components and method for producing optoelectronic components |
-
1985
- 1985-11-15 JP JP60254801A patent/JPS62115752A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4910577A (en) * | 1987-08-10 | 1990-03-20 | Kabushiki Kaisha Toshiba | Lead frame |
| KR100499606B1 (en) * | 2000-06-13 | 2005-07-07 | 앰코 테크놀로지 코리아 주식회사 | Substrate for manufacturing semiconductor package |
| JP2008159742A (en) * | 2006-12-22 | 2008-07-10 | Fujitsu Component Ltd | Mounting structure of semiconductor element |
| DE102011016566A1 (en) * | 2011-03-07 | 2012-09-13 | Osram Opto Semiconductors Gmbh | Lead frame for optoelectronic components and method for producing optoelectronic components |
| US9130136B2 (en) | 2011-03-07 | 2015-09-08 | Osram Opto Semiconductors Gmbh | Leadframe for optoelectronic components and method for producing optoelectronic components |
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