JPH02174149A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02174149A JPH02174149A JP33176088A JP33176088A JPH02174149A JP H02174149 A JPH02174149 A JP H02174149A JP 33176088 A JP33176088 A JP 33176088A JP 33176088 A JP33176088 A JP 33176088A JP H02174149 A JPH02174149 A JP H02174149A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- frame
- die frame
- die
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000011347 resin Substances 0.000 abstract description 20
- 229920005989 resin Polymers 0.000 abstract description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 6
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000005452 bending Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置のフレームの形状に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of a frame of a semiconductor device.
第３図は従来の半導体装置の断面図で、図において、（
１）は金線、（２）は樹脂、（８）はリードフレーム、
（４）はチップ、（５）はチップ（４）を載置するダイ
フレームである。FIG. 3 is a cross-sectional view of a conventional semiconductor device, and in the figure (
1) is gold wire, (2) is resin, (8) is lead frame,
(4) is a chip, and (5) is a die frame on which the chip (4) is placed.
次に動作について説明する。半導体装置はリードフレー
ム（８）、樹脂（２）、チップ（４）等、熱伝導率が違
う材質で作られており、熱の加わる速度が違っている。Next, the operation will be explained. A semiconductor device is made of materials such as a lead frame (8), resin (2), and chip (4) that have different thermal conductivities, and heat is applied at different rates.
１０全体金熱するりフロー半田等ではダイフレーム（５
）が最初に熱せられ１次にその周辺の樹脂（２）の温度
が上がって行き、ダイフレーム（６）と樹脂（２）の密
着性が弱い箇所（ダイフレーム（δ）の内の外部リード
（８）と接続されていない側面）でクラックはく離が発
生していた。10 The entire die frame (5
) is heated first, and then the temperature of the resin (2) around it increases, and the adhesiveness between the die frame (6) and the resin (2) is weak (external leads in the die frame (δ)). Cracks and peeling occurred on the side surface (not connected to (8)).
従来の半導体装置は以上の様に構成されていたので、ダ
イフレームと樹脂の密着性が悪く、又熱の放出の点でも
伝導性が悪く、また半田リフロー等の熱をＩＣ全体に加
えた場合、ダイフレームの側面の箇所で樹脂クラックが
起こるなどの問題点があった。Conventional semiconductor devices were constructed as described above, so the adhesion between the die frame and the resin was poor, and the conductivity was also poor in terms of heat release, and when heat was applied to the entire IC during solder reflow etc. However, there were problems such as resin cracks occurring on the side surfaces of the die frame.
この発明は上記のような問題点を解消するためになされ
たもので、熱放散を良くし熱の一部集中を避けると共に
、樹脂との密着性を良くした半導体装置を得る事を目的
とする。This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor device that improves heat dissipation, avoids partial concentration of heat, and improves adhesion to resin. .
この発明に係る半導体装置はダイフレームの周辺の形状
を下側に折り曲げ、又外部リードフレームとの接続本数
を増加させたものである。In the semiconductor device according to the present invention, the shape of the periphery of the die frame is bent downward, and the number of connections to an external lead frame is increased.
この発明におけるリードフレームおよびグイフレームの
形状は熱放散性を良くし、熱の一部集中を避け、又樹脂
との密着性を増大させる事ができる。The shape of the lead frame and goo frame in this invention improves heat dissipation, avoids partial concentration of heat, and increases adhesion to the resin.
以下、この発明の一実施例を図について説明する。第１
図において、（１）は金線、（２）は樹脂、（８）はリ
ードフレーム、（４）はチップ、（６）はチップ（４）
を載置するダイフレームで、ダイフレーム（５）はその
周辺を図示の如く下側に折り曲げられており、ダイフレ
ーム（５）とリードフレーム（８）の接続本数を４本に
増やしである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is gold wire, (2) is resin, (8) is lead frame, (4) is chip, (6) is chip (4)
The periphery of the die frame (5) is bent downward as shown in the figure, and the number of connections between the die frame (5) and the lead frame (8) is increased to four.
次に動作について説明する。リードフレーム（８）の内
、合計４本は内部グイフレーム（５）と接続されており
、熱の放散性を良くし、熱の一部集中を避ける事ができ
る。又、樹脂（２）に接する各フレームの表面積が増え
る為、樹脂（２）との密着性が良くなる。一方、ダイフ
レーム（５）の形状を下側に折シ曲げる事により、樹脂
（２）との密着性を良くする事ができる。Next, the operation will be explained. A total of four of the lead frames (8) are connected to the internal goo frame (5), which improves heat dissipation and prevents partial concentration of heat. Furthermore, since the surface area of each frame in contact with the resin (2) increases, the adhesion with the resin (2) improves. On the other hand, by bending the shape of the die frame (5) downward, it is possible to improve the adhesion with the resin (2).
以上により、リフロー半田等ＩＣ全体を熱す゛る場合に
も熱のダイフレーム（５）への集中を避ける事ができる
。As described above, even when the entire IC is heated by reflow soldering, etc., it is possible to avoid concentration of heat on the die frame (5).
なお、上記実施例ではリードフレーム（８）の内４本を
内部グイフレーム（５）と接続させた場合を示したが、
さらにその本数を増やす事も可能である。In addition, in the above embodiment, four of the lead frames (8) were connected to the internal Gui frame (5), but
It is also possible to further increase the number.
また、ダイフレーム（６）の周辺を下側に折り曲げる事
により、樹脂（２）との間でクラックが起こっても、下
側（熱集中が起こり易い方向にしかクラックが入らず、
チップ（４）、金線（１）を保護する事ができる。In addition, by bending the periphery of the die frame (6) downward, even if a crack occurs between the die frame (6) and the resin (2), the crack will only occur on the lower side (in the direction where heat concentration is likely to occur).
Chip (4) and gold wire (1) can be protected.
以上のようにこの発明によれば、リードフレームを複数
本グイフレームと増加接続させ、又ダイフレームの周辺
を下側に折シ曲げる事により、熱集中を避ける事ができ
、樹脂とのクラックが防止できる効果がある。As described above, according to the present invention, by increasing the number of lead frames connected to a plurality of lead frames and bending the periphery of the die frame downward, heat concentration can be avoided and cracks with the resin can be avoided. It has a preventive effect.
第１図はこの発明の一実施例による半導体装置を示す断
面図、第２図は第１図のフレームのみの上面図、第３図
は従来の半導体装置を示す断面図である。
図において、（１）は金線、（２）は樹脂、（８）はリ
ードフレーム、（４）はチップ、（６）はダイフレーム
を示す。
なお、図中、同一符号は同一 または相当部分を示す。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a top view of only the frame shown in FIG. 1, and FIG. 3 is a sectional view showing a conventional semiconductor device. In the figure, (1) is a gold wire, (2) is a resin, (8) is a lead frame, (4) is a chip, and (6) is a die frame. In addition, the same symbols in the figures indicate the same or equivalent parts.
Claims (1)
フレームとの接続本数を増やした事を特徴とする半導体
装置。A semiconductor device characterized in that the end of the die frame of the semiconductor device is bent to increase the number of connections to an external lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33176088A JPH02174149A (en) | 1988-12-26 | 1988-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33176088A JPH02174149A (en) | 1988-12-26 | 1988-12-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02174149A true JPH02174149A (en) | 1990-07-05 |
Family
ID=18247313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33176088A Pending JPH02174149A (en) | 1988-12-26 | 1988-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02174149A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019116457A1 (en) * | 2017-12-13 | 2019-06-20 | 三菱電機株式会社 | Semiconductor device and power conversion device |
-
1988
- 1988-12-26 JP JP33176088A patent/JPH02174149A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019116457A1 (en) * | 2017-12-13 | 2019-06-20 | 三菱電機株式会社 | Semiconductor device and power conversion device |
| JPWO2019116457A1 (en) * | 2017-12-13 | 2020-05-28 | 三菱電機株式会社 | Semiconductor device and power converter |
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