JPS5827352A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5827352A JPS5827352A JP56125196A JP12519681A JPS5827352A JP S5827352 A JPS5827352 A JP S5827352A JP 56125196 A JP56125196 A JP 56125196A JP 12519681 A JP12519681 A JP 12519681A JP S5827352 A JPS5827352 A JP S5827352A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- tab
- resin
- coining
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はレジン封止をの半導体装置に関し１時に内部へ
の水の浸透を防止した耐水性の優れた半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device sealed with a resin, and more particularly to a semiconductor device with excellent water resistance that prevents water from penetrating inside.
レジン封止渥の半導体装置は、＃１Ｈに示すように、金
属板材を打抜等により形成したリードフレーム１のタブ
２上に半導体素子ペレット３を固着し、複数本のリード
４とベレッ）３のパッドとの間をワイヤ５にて接続した
上でこれらをレジン６にて一体にモールドしてパッケー
ジを形成したものである。ところが、この種の半導体装
置ではり−ド７レーム１の材質に４２アロイ等を使用し
ているため、その熱膨張係数（６ＸｌＯ−’／Ｕ）がレ
ジン６の熱膨張係数（２４Ｘ１０”−＠／ｃ）ｔ！＝大
幅に相違し、この結果、レジンモールド時或いはモール
ド後における熱変化によりレジンとリードフレームとの
間に熱膨張の差に基づく剪断応力が発生する。このため
、リードフレームとレジンとの界面に接着剥離が生じ、
この剥１部分を通して外部の水分がタブリード７→タブ
２→ベレット３或いはリード４→ワイヤ５→ペレツト３
に沿うて浸入し、ＡＪ材からなるパッドを腐蝕させて断
線不良を起し半導体装置の信頼性を低下させている。As shown in #1H, a resin-sealed semiconductor device is made by fixing a semiconductor element pellet 3 onto a tab 2 of a lead frame 1 formed by punching a metal plate material, and attaching a plurality of leads 4 and a pellet 3 to a lead frame 1. A package is formed by connecting these pads with wires 5 and molding them together with resin 6. However, in this type of semiconductor device, since 42 alloy is used as the material for the resin 6, its thermal expansion coefficient (6XlO-'/U) is the same as that of the resin 6 (24X10''-@ /c) t! = significantly different, and as a result, shear stress is generated between the resin and the lead frame due to thermal changes during or after resin molding due to the difference in thermal expansion. Adhesive peeling occurs at the interface with the resin,
External moisture flows through this peeled portion 1 to tab lead 7 → tab 2 → pellet 3 or lead 4 → wire 5 → pellet 3.
It penetrates along the AJ material and corrodes the pads made of AJ material, causing disconnection defects and reducing the reliability of semiconductor devices.
したが９て本発明の目的は、リードフレームのリードの
レジンモールドされる部分の一部表面にコイニング等の
芯凸を形成し、レジンとり−・ドｔの接着面積の増大を
図るとともにレジンとリードとの剪断方向の引掛りを図
り、これにより熱変化に伴なうリードフレームとレジン
との接着剥離を防止し、水の浸入およびパッド、ワイヤ
の腐蝕を防止して装置の信頼性を高めることができる半
導体装置を提供することにある。However, an object of the present invention is to form a core convexity such as coining on a part of the surface of the resin-molded part of the lead of a lead frame, to increase the adhesive area of the resin handle and dot t, and to It aims to hook the lead in the shear direction, thereby preventing the adhesive from peeling off between the lead frame and resin due to thermal changes, preventing water intrusion and corrosion of the pad and wire, and increasing the reliability of the device. The object of the present invention is to provide a semiconductor device that can perform the following steps.
以下、本発明を図示め実施例により説明する。Hereinafter, the present invention will be explained with reference to illustrated embodiments.
第２図は本発明の一実施例を示し、１０は４２アロイ等
の金属板を打抜き等により形成したリードフレームであ
り、その中央に形成した方形のタブ１１と、タブ１１の
周囲にインナ一部分を配置した複数本のり一部１２と、
前記タブ１１を図外のフレームを介してリード１２と連
絡するタブリード１３とを有している。前記タブ・１１
上には半導体素子ペレット１４をろう材或いはシリコン
共晶等を利用して固着しており、そのパッド１５には前
記リード１２との間１にワイヤ１６を接続している。そ
して、この構体はリードのインナ一部。FIG. 2 shows an embodiment of the present invention, and 10 is a lead frame formed by punching or the like from a metal plate such as 42 alloy, with a rectangular tab 11 formed in the center and an inner part around the tab 11. A plurality of glue parts 12 arranged with
It has a tab lead 13 that connects the tab 11 with a lead 12 via a frame (not shown). Said tab 11
A semiconductor element pellet 14 is fixed thereon using a brazing material or silicon eutectic, and a wire 16 is connected between the pad 15 and the lead 12. And this structure is part of the inner part of the lead.
タブ１１．ペレット１４．ワイヤ１６等を封止するよう
にレジン１７にて一体にモールドされている。Tab 11. Pellets 14. It is integrally molded with resin 17 so as to seal the wire 16 and the like.
一方、前記リード１２．タブリード１３のインナ一部分
、更に言えば前記レジン１７によりモールドされてレジ
ンに接着する部分の一部表面には、第３図に合せて示す
ように、コイニング１８を施してその表面に凹凸を形成
している。このコイニング１８はローラ又はプレスにて
形成しており、特にプレスの場合にはリードフレームの
打抜きと同時にこれを行なうことができる。On the other hand, the lead 12. As shown in FIG. 3, coining 18 is applied to a part of the inner part of the tab lead 13, more specifically, to a part of the surface of the part molded with the resin 17 and bonded to the resin, to form irregularities on the surface. ing. This coining 18 is formed by a roller or a press, and in particular, in the case of a press, this can be done at the same time as punching the lead frame.
以上の構成によれば、半導体装置に熱変化が生じてリー
ドフレーム１０とレジン１７との間に熱膨張の差が生じ
、リードフレームとレジンとの界面に剪断応力が発生し
ても、両者はコイニングの部位において接触（接着）面
積が増大されかつ剪断方向に互に引掛かるように構成さ
れているため。According to the above configuration, even if a thermal change occurs in the semiconductor device and a difference in thermal expansion occurs between the lead frame 10 and the resin 17, and shear stress is generated at the interface between the lead frame and the resin, both This is because the contact (adhesion) area is increased at the coining site and they are configured to catch each other in the shear direction.
両者はコイニング１８部位において剥離されることはな
い。したがって、他の部位において剥離が生じても、第
４Ｐ３に示すようにコイニング１８部位においてはレジ
ン１７とリード１２、タブリード１３とは密着状態を保
持し、リード１２やタブリード１３を通してワイヤ１６
やタブ１１に移動しようとする水の浸入を防止する。こ
れにより、パッド１５やワイヤ１６への水の付着および
これらの腐蝕を防止することができるのであり、装置の
信頼性を高めることができる。Both are not separated at the coining 18 portion. Therefore, even if peeling occurs in other parts, the resin 17, lead 12, and tab lead 13 maintain close contact with each other in the coining 18 part, as shown in P3, and the wire 16 is passed through the lead 12 and tab lead 13.
This prevents water from entering the tub 11. This makes it possible to prevent water from adhering to the pads 15 and wires 16 and from corroding them, thereby increasing the reliability of the device.
ここで、リード等に形成する凹凸は前述のコイニングに
限らず第５図に示すようにリードの延設方向と直角な方
向に形成した縞状の凹凸１８Ａであってもよく、いずれ
にしても単に凹凸を形成するのみではなくレジンとリー
ドフレームとが剪断方向に引掛りをもつように形成する
ことが好ましい。更に、凹凸はリードの片面に限らず表
、裏の両面に形成することが好ましい。Here, the unevenness formed on the lead etc. is not limited to the above-mentioned coining, but may be a striped unevenness 18A formed in a direction perpendicular to the extending direction of the lead as shown in FIG. It is preferable not only to form irregularities but also to form so that the resin and the lead frame are hooked in the shearing direction. Furthermore, it is preferable that the unevenness be formed not only on one side of the lead but also on both the front and back sides.
以上のように本発明の半導体装置によれば、リードのレ
ジンとの接着面の一部にレジンとリードとの接着面積を
増大しかつ両者を剪断方向に引掛は得るコイニング等の
凹凸を形成しているので、熱変化に伴なってリードとレ
ジンとの間に熱膨張の差が生じてもコイニング部におけ
るレジンとリードとの接着剥離を防止し、これによりリ
ードやタブリードを通してペレットにまで移動しようと
する水の浸入を防止してパッドやワイヤの腐蝕を防止し
、装置の信頼性を高めることができるという効果を奏す
る。As described above, according to the semiconductor device of the present invention, unevenness such as coining is formed on a part of the adhesive surface of the lead with the resin, which increases the adhesive area between the resin and the lead and hooks both in the shearing direction. Therefore, even if a difference in thermal expansion occurs between the lead and the resin due to thermal changes, the adhesive between the resin and the lead at the coining part is prevented from peeling off, and this allows the resin to move through the lead and tab lead to the pellet. This has the effect of preventing water from entering, preventing corrosion of the pads and wires, and improving the reliability of the device.
第１図は従来の半導体装置の断面図、第２図は本発明の
半導体装置の破断斜視図、第３図は要部の平面図、第４
図は断面図、第５図は他の実施例の要部斜視図である。
１０・・・リードフレーム、１１・・・タブ、１２・・
・リード、１３・・・タブリード、１４・・・ペレット
、１６・・・ワイヤ、１７・・・レジン、１８，１８Ａ
・・・凹凸（コイニング）。FIG. 1 is a sectional view of a conventional semiconductor device, FIG. 2 is a cutaway perspective view of a semiconductor device of the present invention, FIG. 3 is a plan view of main parts, and FIG.
The figure is a sectional view, and FIG. 5 is a perspective view of a main part of another embodiment. 10...Lead frame, 11...Tab, 12...
・Lead, 13... Tab lead, 14... Pellet, 16... Wire, 17... Resin, 18, 18A
...Irregularities (coining).
Claims (1)
固着するとともに、このタブの肩囲に配置したリードや
タブリードを前記ペレットと共にレジンにてモールドし
てなる半導体装置において、前記リードやタブリードの
レジン接着面の一部にはレジンとリードフレームとの接
着面積を増大しかつ両者を剪断方向に引掛は得るコイニ
ング等の凹凸を形成したことをｆｌ！＃黴とする半導体
装置。1. In a semiconductor device in which a semiconductor element pellet is fixed on a tab of a lead frame, and a lead or tab lead placed around the shoulder of the tab is molded with resin together with the pellet, the resin bonding surface of the lead or tab lead is Fl! is formed with unevenness such as coining on a part of the lead frame to increase the bonding area between the resin and lead frame and to hook them in the shearing direction. # Semiconductor devices that become moldy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56125196A JPS5827352A (en) | 1981-08-12 | 1981-08-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56125196A JPS5827352A (en) | 1981-08-12 | 1981-08-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5827352A true JPS5827352A (en) | 1983-02-18 |
Family
ID=14904291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56125196A Pending JPS5827352A (en) | 1981-08-12 | 1981-08-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5827352A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59177952A (en) * | 1983-03-28 | 1984-10-08 | Matsushita Electric Ind Co Ltd | Resin sealed electronic part |
| JPS61263142A (en) * | 1985-05-15 | 1986-11-21 | Mitsui Haitetsuku:Kk | Lead frame |
| JPS6219754U (en) * | 1985-07-22 | 1987-02-05 | ||
| JPS62104448U (en) * | 1985-12-23 | 1987-07-03 | ||
| JPS6467949A (en) * | 1987-09-08 | 1989-03-14 | Mitsui High Tec | Lead frame and manufacture thereof |
| US4862586A (en) * | 1985-02-28 | 1989-09-05 | Michio Osada | Lead frame for enclosing semiconductor chips with resin |
| US4876587A (en) * | 1987-05-05 | 1989-10-24 | National Semiconductor Corporation | One-piece interconnection package and process |
| JP2007258205A (en) * | 2006-03-20 | 2007-10-04 | Denso Corp | Electronic device and its manufacturing method |
-
1981
- 1981-08-12 JP JP56125196A patent/JPS5827352A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59177952A (en) * | 1983-03-28 | 1984-10-08 | Matsushita Electric Ind Co Ltd | Resin sealed electronic part |
| US4862586A (en) * | 1985-02-28 | 1989-09-05 | Michio Osada | Lead frame for enclosing semiconductor chips with resin |
| JPS61263142A (en) * | 1985-05-15 | 1986-11-21 | Mitsui Haitetsuku:Kk | Lead frame |
| JPS6219754U (en) * | 1985-07-22 | 1987-02-05 | ||
| JPS62104448U (en) * | 1985-12-23 | 1987-07-03 | ||
| US4876587A (en) * | 1987-05-05 | 1989-10-24 | National Semiconductor Corporation | One-piece interconnection package and process |
| JPS6467949A (en) * | 1987-09-08 | 1989-03-14 | Mitsui High Tec | Lead frame and manufacture thereof |
| JP2007258205A (en) * | 2006-03-20 | 2007-10-04 | Denso Corp | Electronic device and its manufacturing method |
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