JPS61186024A - Timing signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain plural timing signals by frequency-dividing variably a reference frequency, applying fixed frequency division further to the result and changing the frequency division of a variable frequency division circuit so as to output the timing signal applying n/m frequency-division to the reference frequency from the variable frequency division circuit. CONSTITUTION:A phase locked circuit is constituted of a loop circuit comprising a phase comparator 1, a low pass filter 2, a voltage controlled oscillator 3 and a 1/6 frequency division circuit 10, and a reference frequency f0 being 6 times the signal of an input signal f1 inputted to a phase comparator 1 is outputted from the voltage controlled oscillator 3 synchronously with the frequency f1. The reference frequency f0 is selected to a frequency being twice the frequency 2,304kHz being a least common multiple of, e.g., 14.4kHz and 768kHz. The output of the voltage controlled oscillator 3 is subject to 1/2 frequency division by a 1/2 frequency division circuit 6, the output is subject to frequency division by a 1/160 frequency-division circuit 9 and a timing signal f3 in 14.4kHz is obtained. Further, an output A of the voltage controlled oscillator 3 is subjected to 1/19 frequency division by the variable frequency division circuit 4, then a fixed frequency division circuit 5 applies 1/5 frequency division, and its output C controls the frequency division ratio of the variable frequency division circuit 4 to be 1/20 and a timing signal f1 in 240kHz is obtained.

Description

Detailed Description of the Invention Field of the Invention The present invention relates to a timing signal generation circuit used in a time division multiplexing device or the like to generate timing signals of multiple types of frequencies in synchronization with an input signal. Regarding.

Summary of the Invention The present invention provides a timing signal generation circuit that synchronizes with the frequency of an input signal and oscillates a frequency that is an integer multiple of the frequency of the input signal using a loop circuit including a phase comparator, a low-frequency single wave generator, a voltage controlled oscillator, and a frequency divider. The output of the phase synchronized circuit is divided by a variable frequency divider circuit, the output of the variable frequency divider circuit is further divided by a fixed frequency divider circuit, and the frequency division ratio of the variable frequency divider circuit is determined by the output of the fixed frequency divider circuit. By controlling the output of the voltage controlled oscillator from the variable frequency divider circuit to n/m (n, m are integers)
The frequency-divided timing signal is output, and the reference frequency for obtaining timing signals of multiple types of frequencies can be lower than the least common multiple of the multiple types of frequencies.

Prior Art Conventionally, timing signals of a plurality of types of frequencies are created by dividing a reference signal of a frequency that is the least common multiple of the plurality of types of frequencies. FIG. 3 is a block diagram showing an example of a conventional timing signal generation circuit. That is, a phase synchronization circuit is configured by a loop circuit including a phase comparator 11, a low frequency single wave generator 12, a voltage controlled oscillator 13, and a frequency dividing circuit 17 with a frequency division ratio of 1/N. In synchronization with the signal fi, a reference frequency f that is N times that
, ' are output from the voltage controlled oscillator 13, and are frequency-divided into I/, f/L, and I/M by the frequency dividing circuits 14 to 6, respectively, to obtain timing signals of frequencies fl, f2, and f3.

In recent years, with the digitization of equipment, time division multiplexing equipment has been used that converts various signals such as data terminals, facsimiles, audio and images into digital signals, time division multiplexes them, and transmits them over a single communication line. . Such time division multiplexing equipment must handle data signals of various transmission speeds, from low-speed data to high-speed image signals, and the timing signals required for this purpose range from low to high frequencies. For example, 14.4 Kb/s data terminal, 58 Kb/s facsimile, 240 Kb/s
Considering a multiplexing device that time-division multiplexes various signals such as inter-computer communications at 7HKb/s and transmits them at 7HKb/s. 4Kb/s, 58Kb/
It is necessary to create various timing signals of 240 Kb/s.

When trying to generate these various timing signals using the conventional timing signal generation circuit described above, the reference frequency *fo' oscillated by the voltage controlled oscillator 13 is 14.4 Kb/s.
, 5GKb/s, 240Kb/s and 788K
It is necessary to set the frequency to the lowest common multiple of b, that is, an extremely high frequency of 80.84 MHz. For this reason, the synchronization pull-in characteristic of the phase synchronized circuit deteriorates, and the frequency dividing circuits 14 to 1
There is a drawback that the number of frequency division stages of 7 increases.

If separate oscillators are prepared according to the type of frequency, it is possible to prevent an increase in the number of stages in the frequency divider circuit and deterioration of the pull-in characteristics of the phase-locked circuit. Since it is necessary to prepare a plurality of 4Bs, it becomes difficult to downsize and lower the cost of the device.

Problems to be Solved by the Invention The present invention uses a frequency lower than the least common multiple of various timing signals as a reference, and divides this frequency by n/m to obtain arbitrary various timing signals. This is intended to reduce the number of frequency division stages.

Structure of the Invention The timing signal generation circuit of the present invention is a phase synchronized circuit that synchronizes with an input signal and oscillates a frequency that is an integral multiple of the input signal using a loop circuit including a phase comparator, a low-frequency single wave generator, a voltage controlled oscillator, and a frequency dividing circuit. and a variable frequency divider circuit that frequency divides the output of the voltage controlled oscillator.

and a fixed frequency divider circuit that divides the output of the variable frequency divider circuit.

The frequency division ratio of the variable frequency divider circuit is controlled by the frequency division output of the fixed frequency divider circuit, so that the output of the voltage controlled oscillator is n/
It is characterized in that it generates a round signal by dividing the frequency by m (where n and m are integers).

Embodiments of the Invention Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention,
Based on 4808KHz, 14.4Kb/s.

58 Kb/s, 240 Kb/s and 788 Kb timing signals are available. That is, a phase synchronization circuit is constituted by a loop circuit of a phase comparator 1, a low frequency waveform generator 2, a voltage controlled oscillator 3, and a 178 frequency divider 10,
In synchronization with the input signal fi input to the phase comparator l, the voltage controlled oscillator 3 outputs a reference frequency f that is six times that input signal fi. The reference frequency f is, for example, 24.4 KHz and 788
KHz (1) 2 of 2304KH2 which is the least common multiple
Select twice the frequency (4608KHz). The output of the voltage controlled oscillator 3 is divided by 1/2 by the 1/2 frequency divider circuit 6, and 17
The output of the frequency divider 6 by 2 is further divided by 1/1130 by a 1/1ffO frequency divider 9 to obtain a timing signal f3 of 14.4 KHz.

The 240 KHz timing signal fl is obtained by dividing the output A of the voltage controlled oscillator 3 by l/19 by a variable frequency divider circuit 4, and further by dividing the output of the variable frequency divider circuit 4 by a fixed frequency divider circuit 5! This can be obtained by dividing the frequency by 15 and controlling the frequency dividing ratio of the variable frequency dividing circuit 4 to 1/20 using the output C of the fixed frequency dividing circuit 5. FIG. 2(A) shows the input clock signal A (signal with reference frequency f output from the voltage controlled oscillator 3) of the variable frequency divider circuit 4. The variable frequency divider circuit 4 receives the input clock signal A by a fixed number Each time it counts, it outputs a divided output B as shown in (B) in the same figure (C).
shows the column of output B of the variable frequency divider circuit 4.

As shown in the figure (D), the fixed frequency divider circuit 5 outputs the frequency divided output C every time the frequency divided output B is counted 5 times, so during this time, the variable frequency divider circuit 4 receives the input clock. Divide the frequency of signal A by 1/20. Therefore, the variable frequency divider circuit 4 outputs five pulses during the (19X 4 + 20) period of the input clock signal A (see (C) in the same figure).
). That is, the timing signal f is a timing signal obtained by dividing the reference frequency f by 5/9θ. By changing the frequency division ratio, this timing signal f1 has
Although approximately 4.2% jitter is generated, this value is smaller than the jitter that occurs in a normal data communication line, and does not adversely affect terminal devices and the like.

The 58 KHz timing signal f2 is obtained by dividing the output of the 172 frequency dividing circuit 6 by 1/41 by the variable frequency dividing circuit 7, dividing the frequency by 1/7 by using the fixed frequency dividing circuit 8, and by dividing the output of the variable frequency dividing circuit 7 by 1/7. Only when the fixed frequency dividing circuit 8 outputs a frequency, the frequency division ratio of the variable frequency dividing circuit 7 is controlled to be 1/42. From the variable frequency divider circuit 7, the output of the voltage 81m oscillator 3 is 7157
A timing signal f2 of 58 Kb/s obtained by dividing the frequency by 6 is obtained. The jitter in this case is about 2%, and its effect can be completely ignored.

For any frequency combination other than the above, similarly to the above, the reference signal lower than the least common multiple of each frequency is n / m
By dividing the frequency, it is possible to easily obtain a plurality of timing signals of various frequencies. Also, when obtaining only one timing signal, one can be obtained in the same way as above.
Of course, it can be created by dividing the reference frequency, which is not exactly an integral multiple, by n/m.

Effects of the Invention As described above, in the present invention, the reference frequency is divided by a variable frequency divider circuit, the output of the variable frequency divider circuit is further divided by a fixed frequency divider circuit, and the frequency is divided by the fixed frequency divider circuit. By changing the frequency division ratio of the variable frequency divider circuit when outputting the frequency, the variable frequency divider circuit outputs a timing signal obtained by dividing the reference frequency by n/m.
It is possible to create a plurality of timing signals based on a frequency lower than the least common multiple of each frequency.

Therefore, the oscillation frequency of the voltage controlled oscillator of the phase locked circuit can be lowered, the synchronization pull-in characteristic can be improved, and the number of frequency division stages can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing various signals of the above embodiment, and FIG. 3 is a block diagram showing an example of a conventional timing signal generation circuit. In the figure, 2 is a phase comparator, 2 is a low-frequency single wave filter, 3 is a voltage-controlled oscillator, 4 is a variable frequency divider circuit, 5 is a fixed frequency divider circuit, and 6 is a phase comparator.
: 1/2 frequency divider circuit, 7: Variable frequency divider circuit, 8: Fixed frequency divider circuit, 9: 1/1130 frequency divider circuit, lO: L/8
Frequency divider circuit, 11: Phase comparator, 12: Low frequency single wave generator, 13
: Voltage controlled oscillator, 14 to 17: Frequency dividing circuit.

Claims (1)

[Claims] A phase synchronized circuit that synchronizes with an input signal and oscillates a frequency that is an integer multiple of the input signal using a loop circuit including a phase comparator, a low-frequency single wave generator, a voltage controlled oscillator, and a frequency dividing circuit; A variable frequency divider circuit that frequency divides the output of the controlled oscillator, and a fixed frequency divider circuit that frequency divides the output of the variable frequency divider circuit, the variable frequency divider according to the frequency divided output of the fixed frequency divider circuit. By controlling the frequency division ratio of the circuit, the output of the voltage controlled oscillator is n/m (
A timing signal generation circuit characterized in that it generates a timing signal of an arbitrary frequency in synchronization with an input signal by dividing the frequency (n and m are integers).