JPH05199498A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To produce a 2nd clock signal synchronous with the prescribed timing of a 1st clock signal with high stability and high accuracy by controlling the oscillation of the 2nd clock signal in accordance with the phase difference caused between the delayed division outputs of both clock signals. CONSTITUTION:A dividing circuit 11 divides a 1st clock signal S10 to be inputted by an integer multiple (N) of the 1st prescribed cycle number (322) and outputs the 1st division output S11, i.e., the dividing result. A 2nd dividing circuit 14 divides a 2nd clock signal S12 inputted from a VCO 13 by an integer multiple (N) of the 2nd prescribed cycle number (423) and outputs 2nd division output S13. A variable delay circuit 15 sends the delayed division output S14 obtained by delaying the output S13 as necessary to a phase detecting circuit 12. The circuit 12 compares the phases of both outputs S11 and S14 with each other. Then the circuit 12 controls the VCO 13 based on the result of comparison and outputs the clock signal S12.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problem to be Solved by the Invention (FIG. 5) Means for Solving the Problem (FIG. 1) Action (FIG. 1) Example (FIGS. 1 to 4) Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and can be applied to, for example, a circuit which generates a clock signal when converting a sampling rate of a digital video signal.

[0003]

2. Description of the Related Art Conventionally, as a rate converter for a digital video signal, for example, D-1.625 in SMPTE.
/ 50 format component digital video signal (hereinafter simply referred to as D-1 digital video signal) is referred to as D-2.
There is a PAL type composite digital video signal (hereinafter, simply referred to as D-2 digital video signal).

Here, the sampling frequency of the D-1 digital video signal is 13.5 [MHz], while the sampling frequency of the D-2 digital video signal is 17.734475 [MHz] which is four times the carrier frequency f _SC. Therefore, the rate conversion device is realized by a high-order oversampling filter configuration having a least common multiple of the sampling frequency, for example.

[0005]

In such a rate converter, clock signals having frequencies 13.5 [MHz] and 17.734475 [MHz] depending on the sampling frequency must be synchronized with each other at a predetermined timing. For this reason, a clock generation circuit having a phase locked loop (PLL) structure is used.

In the above-mentioned digital video signals of D-1 and D-2, it is the period of one frame that the mutual clock signals have the smallest integer relationship with respect to 540,000 cycles of the clock signal of D-1. Then, with the clock signal of D-2
It is 709,379 cycles. Therefore, in the clock generation circuit, the PLL is synchronized with each frame cycle.

That is, as shown in FIG. 5, in the clock generation circuit 1, the input D-1 frame signal S1 is supplied to the phase detection circuit 2. Further, the D-2 clock signal S2 output from the voltage controlled oscillator (VCO) 3 is divided by the 1 / 709,379 frequency divider circuit 4, and the resultant D-2 frame signal S3 is obtained by the phase detection circuit 2.
Has been entered in.

The phase detection circuit 2 compares the phases of the frame signals S1 and S3 of the input D-1 and D-2 and generates a control signal S4 for making the phases coincide with each other. In S4, the oscillation frequency of the voltage controlled oscillator circuit 3 is controlled. As a result, the clock signal S2 of the digital video signal of D-2 that matches the cycle of the frame signal S1 of the digital video signal of D-1 is generated.

However, in the clock generation circuit 1 having such a configuration, the PLL is used in a frame cycle having a frequency of 25 [Hz].
However, the rate conversion device requires a stability of about 1/10 cycle, and in practice, the clock signal interlocks with each other. Considering the stability of, it was still insufficient for practical use.

The present invention has been made in consideration of the above points. With respect to the first and second clock signals which cannot be expressed by a simple relation of integer ratios, the predetermined timing of the first clock signal is stable and highly accurate. A clock generation circuit for generating a second clock signal synchronized with the clock signal is proposed.

[0011]

In order to solve such a problem, in the present invention, the first and second clock signals S10 and S12, which cannot be represented by a simple integer ratio relationship, and the first clock signal S10 First predetermined cycle (322)
The first and second clock signals S1 whose eyes are close to the second predetermined cycle (423) of the second clock signal S12
0 and S12 are input to the clock generation circuit 10 that generates the second clock signal S12 synchronized with the predetermined timing of the first clock signal S10.
Clock signal S10 of the first predetermined number of cycles (322
), An integer multiple (N) of the
First clock frequency dividing means 1 for transmitting the frequency division output S11 of
1 and the clock signal oscillating means 13 that oscillates and outputs the second clock signal S12, and the second clock signal S12 input from the clock signal oscillating means 13
The second frequency division output S13 is obtained by dividing the frequency by an integer multiple (N) of the predetermined number of cycles (423) of
Clock dividing means 14, a delay means 15 for transmitting a delay frequency dividing output S14 obtained by delaying the second frequency dividing output S13 as necessary, a first frequency dividing output S11 and a delay frequency dividing output. The phase of S14 is compared, and the phase detecting means 12 for controlling the clock signal oscillating means 13 is provided based on the detection result, and the second clock signal S12 oscillated by the clock signal oscillating means 13 is output. ..

[0012]

The frequency division output S11 is an integral multiple (N) of the first predetermined number of cycles (322) of the first clock signal S10, and the second
Second predetermined number of cycles of clock signal S12 (423)
The second clock signal S12 according to the phase difference between the second frequency-divided output S13 and the delayed frequency-divided output S14 that is an integral multiple (N) of
By controlling the clock signal oscillating means 13 for oscillating the clock signal, the clock signal oscillating means 13 is synchronized with the predetermined timing of the first clock signal S10 with much more stable and higher accuracy as compared with the case where the synchronization is taken at every predetermined timing. A second clock signal S12 may be generated.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, reference numeral 10 generally indicates a clock generation circuit according to the present invention, in which a D-1 clock signal S10 input at a frequency of 13.5 [MHz] is divided by a 1/322 × N frequency divider circuit 11. The first frequency-divided signal S11 obtained as a result is input to the phase detection circuit 12.

Further, the clock signal S12 of D-2 having a frequency of 17.734475 [MHz] oscillated by the voltage controlled oscillator (VCO) 13 is divided by the 1/423 × N divider circuit 14, and the result is obtained. The second frequency-divided signal S13 is delayed by the variable delay circuit 15 as necessary, and the delayed frequency-divided signal S13 is delayed.
14 is input to the phase detection circuit 12.

As a result, the phase detection circuit 12 compares the phases of the first frequency-divided signal S11 and the delayed frequency-divided signal S14, and controls the oscillation frequency of the VCO 13 according to the comparison result. The clock signal S12 of D-2 whose phase is synchronized with the clock signal S10 at a predetermined timing is transmitted as an output.

In the case of this clock generation circuit 10, D-1
Clock signal S10 and D-2 clock signal S12
, The phase is exactly synchronized with each other in one frame period, but pay attention to the cycle in which the timings of the clock signals S10 and S12 are very close to each other, and stabilize the PLL in a period significantly shorter than one frame period. It is designed to let you.

Practically, D-1 having a frequency of 13.5 [MHz]
The time of the 322 × Nth cycle (in this embodiment, 644th cycle with N = 2) of the clock signal S10 of

[Equation 1] It is represented by.

On the other hand, the time of the 423.times.N cycle of the clock signal S12 of D-2 having the frequency of 17.734475 [MHz] (which is the 846th cycle of N = 2 as in the case of D-1) is as follows. formula

[Equation 2] The difference is 7.936 × 10 ^-12 [Sec]. Thus, it can be seen that the 644th cycle of the D-1 clock signal S10 and the 846th cycle of the D-2 clock signal S12 are substantially equal to each other, and thus it is sufficient to apply the PLL.

Therefore, in the case of this clock generation circuit 10,
First, the counters of the 1/322 × N frequency dividing circuit 11 and the 1/423 × N frequency dividing circuit 14 each having a loop counter configuration are reset at a frame period to generate a clock signal S10 of D-1 and a clock signal S12 of D-2. Is synchronized with the frame cycle.

Actually, in the case of the 644th cycle of the D-1 clock signal S10 and the 846th cycle of the D-2 clock signal S12 per one cycle, as described above, 7.936
An error of × 10 ^-12 [Sec] occurs, and in one frame,

[Equation 3] As shown in, an error of about 6.7 [ns] occurs.

Since the time of this error takes a fixed time per cycle, the variable delay circuit 15 delays the delay by the delay time as necessary in practice and corrects it. P between D-2 clock signals
The error of LL is controlled to a small value, and the clock signal S1 of D-2 synchronized with the clock signal S10 of D-1 with high accuracy.
It is designed to generate 2.

Now, the clock generation circuit 1 of this embodiment
0 has a detailed configuration as shown in FIG. 2 in which the same parts as those in FIG.
And 1/423 × N frequency dividing circuit 14 are respectively a 644 counter circuit 11A and a 846 counter circuit 14A having a loop counter configuration, and a flip-flop (FF) 11B and 14B.
It is configured by combining and.

First, the 644 counter circuit 11A counts the input D-1 clock signal S10. As a result, the carrier signal S16 (FIG. 3C) appearing at every 644th cycle of the clock signal S10 is D-1. Clock signal S
The phase is controlled by a predetermined amount by the phase control circuit 11C through the flip-flop 11B which operates at the timing of 10 and is input to the phase detection circuit 12 as the 1/644 frequency division signal S11 (FIG. 3D).

On the other hand, the 846 counter circuit 14A counts the input D-2 clock signal S12, and as a result, the carrier signal S17 (FIG. 3 (E)) that appears every 846th cycle of the clock signal S12 is D-2. Clock signal S
Through the flip-flop 14B which operates at the timing of 12, the variable delay circuit 15 is generated as the 1/846 frequency-divided signal S13.
Input to A.

In addition to this, 846 counter circuit 14A
The carrier signal S17 sent from is input to the delay amount control circuit 15B. The delay amount control circuit 15B counts the carrier signal S13 and sends an address signal S18 that determines the delay time according to the count result to the variable delay circuit 15A.

As a result, the variable delay circuit 15A delays the falling edge of the input 1/846 frequency-divided signal S13 with a delay time of, for example, 0 [ns] to a maximum of 10 [ns] according to the address signal S18. This is the delayed frequency-divided signal S14 (see FIG.
(F)) is input to the phase detection circuit 12.

As described above, the 644 counter circuit 11
The A and 846 counter circuits 14A are reset at the frame cycle, and in reality, the frame signal S20 (see FIG.
(A) is a clock signal S of D-1 and D-2, respectively.
10 and the latch circuit 20 operating at the timing of S12
A and 21A, and edge detection circuits 20B and 21B.

The latch circuits 20A and 21A and the edge detection circuits 20B and 21B are connected to the clock signal S, respectively.
The frame switching is detected at the timings of 10 and S12, and the frame cycle signals S21, S obtained as a result are detected.
22 (FIG. 3 (B)), the 644 counter circuit 11A and the 846 counter circuit 14A are reset.

In this way, in the clock generation circuit 10 of this embodiment, the clock signal S12 of D-2 is output.
Delayed frequency-divided signal S14 obtained by delaying 1/846 frequency-divided signal S13
And the 1/644 frequency division signal S1 of the clock signal S10 of D-1
The VCO 13 is controlled so as to correct the phase difference with respect to 1, and as a result, as shown in FIG. 4, the clock signal of D-2 synchronized with the clock signal S10 of D-1 (FIG. 4A) with high accuracy. S12 (FIG. 4 (B)) can be generated.

According to the above-mentioned configuration, the VCO 13 has a phase difference between the 1/644 frequency-divided signal S11 of the D-1 clock signal S10 and the 1/846 frequency-divided signal S13 of the D-2 clock signal S12. Is controlled so that the PLL is locked, the clock signal S10 of D-1 is synchronized with the clock signal S10 of D-1 with much higher accuracy and stability as compared with the conventional clock generation circuit 1 that locks the PLL at the frame cycle. It is possible to realize the clock generation circuit 10 that can generate the clock signal S12 of D-2.

In the above embodiment, N is set to 2 and the 1/644 frequency dividing circuit and the 1/846 frequency dividing circuit are used, but the frequency dividing number is not limited to this, and for example N Even if the frequency is divided by 1/322 and 1/423 with = 1, the same effect as that of the above-described embodiment can be realized.

Further, in the above-described embodiment, the present invention has been described with reference to the case where the clock signal of the digital video signal of D-2 is generated in synchronization with the clock signal of the digital video signal of D-1. It can also be applied to the case of obtaining the clock signal of the D-1 digital video signal in which the clock signal of the digital video signal of 2 is synchronized.

Furthermore, in the above-mentioned embodiment, the case where the present invention is applied to the clock generation circuit in the rate conversion device of the digital video signal has been described, but the present invention is not limited to this, and the relations of simple integer ratios are mutually. It is suitable for wide application in the case of generating a clock signal which is synchronized with a predetermined timing of one clock signal among the clock signals which are not present.

[0035]

As described above, according to the present invention, the frequency division output is an integral multiple of the first predetermined number of cycles of the first clock signal and the second predetermined number of cycles of the second clock signal is an integer. The oscillation of the second clock signal is controlled according to the phase difference between the second frequency-divided output and the frequency-divided frequency-divided output. It is possible to realize a clock generation circuit capable of generating the second clock signal synchronized with the predetermined timing of the first clock signal with stable and high accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a clock generation circuit according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration of the clock generation circuit in FIG.

FIG. 3 is a timing chart for explaining the operation of the clock generation circuit of FIG.

FIG. 4 is a timing chart for explaining operation timing of the clock generation circuit of FIG. 2 after one frame.

FIG. 5 is a block diagram showing a configuration of a conventional clock generation circuit.

[Explanation of symbols]

1, 10 ... Clock generation circuit, 2, 12 ... Phase detection circuit, 3, 13 ... Voltage-controlled oscillation circuit, 4, 11, 1
4 ... Dividing circuit, 15 ... Variable delay circuit.

Claims (1)

[Claims] 1. A first predetermined clock signal and a second clock signal which cannot be expressed by a simple integer ratio relationship, and a first predetermined cycle of the first clock signal is a second predetermined clock signal of the second clock signal. In the clock generation circuit for generating the second clock signal in synchronization with the predetermined timing of the first clock signal for the first and second clock signals close to the cycle, the first clock signal is input. The signal is frequency-divided by an integer multiple of the first predetermined cycle number, and the first frequency obtained by the frequency division is obtained.
The first clock frequency dividing means for transmitting the frequency division output, the clock signal oscillating means for oscillating and outputting the second clock signal, and the second clock signal input from the clock signal oscillating means. , A second clock frequency dividing means for frequency-dividing by the integer multiple of the second predetermined number of cycles, and transmitting a second frequency-divided output resulting from the frequency-division result, and the second frequency-divided output. Delay means for delaying and outputting the delayed frequency-divided output, and the phases of the first frequency-divided output and the delayed frequency-divided output are compared, and based on the detection result, the clock signal oscillating means And a phase detection means for controlling the output of the clock signal oscillating means to output the second clock signal oscillated by the clock signal oscillating means.