[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS6419459A - Common bus arbiter - Google Patents

Common bus arbiter

Info

Publication number
JPS6419459A
JPS6419459A JP17497287A JP17497287A JPS6419459A JP S6419459 A JPS6419459 A JP S6419459A JP 17497287 A JP17497287 A JP 17497287A JP 17497287 A JP17497287 A JP 17497287A JP S6419459 A JPS6419459 A JP S6419459A
Authority
JP
Japan
Prior art keywords
priority level
low
speed device
degrading
common bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17497287A
Other languages
Japanese (ja)
Inventor
Satoshi Sugano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17497287A priority Critical patent/JPS6419459A/en
Publication of JPS6419459A publication Critical patent/JPS6419459A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To stabilize the operation and to improve the efficiency of the whole of a computer system by securing the normal operation of a low-speed device generally having a low priority level without degrading the performance of a high-speed device generally having a high priority level. CONSTITUTION:All of common bus request signals (a) outputted from plural devices connected to a common bus are latched in a bus use request accepting circuit 11 once synchronously with a system clock (b). Fundamentally, the right of bus use is given to a device in a group having a high priority level; but this principle is not absolute, and the right of bus use is given to a device in a group having a low priority level when the value of a low level request detection signal (d) inputted to an arbitrating information switching circuit 13 synchronously with the system clock (b) continues for a certain time. Consequently, the normal operation of the low-speed device having a low priority level is secured without degrading the performance of the high-speed device having a high priority level. Thus, the stable operation is performed without degrading the efficiency of the whole of the computer system.
JP17497287A 1987-07-15 1987-07-15 Common bus arbiter Pending JPS6419459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17497287A JPS6419459A (en) 1987-07-15 1987-07-15 Common bus arbiter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17497287A JPS6419459A (en) 1987-07-15 1987-07-15 Common bus arbiter

Publications (1)

Publication Number Publication Date
JPS6419459A true JPS6419459A (en) 1989-01-23

Family

ID=15987958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17497287A Pending JPS6419459A (en) 1987-07-15 1987-07-15 Common bus arbiter

Country Status (1)

Country Link
JP (1) JPS6419459A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013094A (en) * 1988-08-25 1991-05-07 Aisin Seiki Kabushiki Kaisha Hydraulic braking system
US5171073A (en) * 1989-11-07 1992-12-15 Honda Giken Kogyo Kabushiki Kaisha Hydraulic pressure control system with three port spool valve

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013094A (en) * 1988-08-25 1991-05-07 Aisin Seiki Kabushiki Kaisha Hydraulic braking system
US5171073A (en) * 1989-11-07 1992-12-15 Honda Giken Kogyo Kabushiki Kaisha Hydraulic pressure control system with three port spool valve

Similar Documents

Publication Publication Date Title
EP0378427A3 (en) High speed data transfer on a computer system bus
JPS57117027A (en) Signal sending and receiving circuit
JPS6419459A (en) Common bus arbiter
SU955071A1 (en) Priority control device
JPS6476486A (en) Memory ic
JPS5672753A (en) Selective processor for occupation of common bus line
JPS6467665A (en) Information processor
EP0264740A3 (en) Time partitioned bus arrangement
JPS6476254A (en) Device for arbitrating bus
JPS6431252A (en) Data bus width transformer
SU1679625A1 (en) Counting unit
JPS6426967A (en) Multi-firmware system
JPS5638643A (en) Interruption priority processing system
JPS6421488A (en) Crt controller
JPS5614329A (en) Data processing system
JPS57137938A (en) Data processor
JPS54122944A (en) Logic circuit
JPS54109733A (en) Synchronous control system for interface device
JPS55159265A (en) Information processor
JPS5523582A (en) Request selection system
JPS5478635A (en) Data transfer control circuit
JPS6441951A (en) Dma controller
JPS6310246A (en) Address output system for microprocessor
JPS56116155A (en) Error detection system of parity check system
JPS5478636A (en) Input/output interface circuit