JPS6476254A - Device for arbitrating bus - Google Patents

Abstract

PURPOSE:To attain effective bus arbitration with simple circuit constitution by generating the bus access request of the bus master of high priority at the rising of a processing clock signal and generating the access request of the bus master of low priority at the falling of the signal. CONSTITUTION:The bus access request of a bus master 1 of the high priority is outputted from a first bus request generating means 3 as a requesting signal at the rising of a processing clock (Cm) of this bus master. The bus access request of a bus master 2 of the low priority is synchronized to the clock (Cm) by a synchronizing means 4 and outputted from a second bus request generating means 5 as the requesting signal at the falling of the clock (Cm). The using allowance of a bus is given from a bus using allowing means 6 to the requesting signals from the means 3 and 5. Accordingly, a bus arbitrating device, in which the bus master of the high priority can acquire the bus with a short waiting time, can be obtained with the simple circuit constitution.