JPS58118599U - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPS58118599U JPS58118599U JP1143082U JP1143082U JPS58118599U JP S58118599 U JPS58118599 U JP S58118599U JP 1143082 U JP1143082 U JP 1143082U JP 1143082 U JP1143082 U JP 1143082U JP S58118599 U JPS58118599 U JP S58118599U
- Authority
- JP
- Japan
- Prior art keywords
- register
- address register
- error
- read
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例のブロック図、第２図は、第
１図中のエラーアドレスレジスタ部、エラーデータレジ
スタ部、表示回路およびエラー表示フリツプフｂツブ部
の詳細図である。
′１・・・中央処理装置、２・・・記憶装置、３・・・
起動信号線、４・・・アドレス信号線、５・・・データ
信号線、２５・・・記憶部、２６・・・表示回路。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a detailed diagram of an error address register section, an error data register section, a display circuit, and an error display flip-flop section in FIG. '1...Central processing unit, 2...Storage device, 3...
Activation signal line, 4: Address signal line, 5: Data signal line, 25: Storage section, 26: Display circuit.
Claims (1)
ジスタと、記憶素子からの読出し情報を保持する読取り
レジスタと制御タイミング発生回路とを有する記憶装置
において、該アドレスレジスタと同一ビット構成のエラ
ーアドレスレジスタと該読取りレジスタと同一ビット構
成のエラーデータレジスタとをそれぞれアドレスレジス
タ、読取りレジスタと併置し、該出力を表示回路に接続
し、かつ読取りレジスタ出力にパリティチェック回路を
接続し、該パリティチェック回路のチェック結果を保持
するレジスタを設け、該出力を該エラーアドレスレジス
タ及びエラーデータレジスタのセット及びリセットゲー
トに接続し、制御タイミング発生回路のタイミングを制
御することを特徴とする記憶装置。In a storage device that has an address register that holds address information from a central processing unit, a read register that holds information read from a storage element, and a control timing generation circuit, an error address register that has the same bit configuration as the address register and an error address register that has the same bit configuration as the address register, A read register and an error data register having the same bit configuration are placed in parallel with an address register and a read register, respectively, the outputs are connected to a display circuit, and a parity check circuit is connected to the read register output, and the check result of the parity check circuit is 1. A storage device comprising: a register for holding the error address register; the output thereof is connected to the set and reset gate of the error address register and the error data register; and the timing of the control timing generation circuit is controlled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1143082U JPS58118599U (en) | 1982-02-01 | 1982-02-01 | Storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1143082U JPS58118599U (en) | 1982-02-01 | 1982-02-01 | Storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58118599U true JPS58118599U (en) | 1983-08-12 |
Family
ID=30024038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1143082U Pending JPS58118599U (en) | 1982-02-01 | 1982-02-01 | Storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58118599U (en) |
-
1982
- 1982-02-01 JP JP1143082U patent/JPS58118599U/en active Pending
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