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JPS5710924A - Selective diffusion process for impurity into semiconductor crystal - Google Patents

Selective diffusion process for impurity into semiconductor crystal

Info

Publication number
JPS5710924A
JPS5710924A JP8573480A JP8573480A JPS5710924A JP S5710924 A JPS5710924 A JP S5710924A JP 8573480 A JP8573480 A JP 8573480A JP 8573480 A JP8573480 A JP 8573480A JP S5710924 A JPS5710924 A JP S5710924A
Authority
JP
Japan
Prior art keywords
diffusion
crystal
semiconductor crystal
mask
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8573480A
Other languages
Japanese (ja)
Inventor
Toyohiro Takimoto
Kenji Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8573480A priority Critical patent/JPS5710924A/en
Publication of JPS5710924A publication Critical patent/JPS5710924A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent an abnormal diffusion and to provide a diffusion region under a good control by a method wherein openings are formed in different kinds of crystals and diffusion mask layer placed on a substrate crystal, and impurities are diffused into the substrate plate. CONSTITUTION:Semiconductor crystal 22 having a different chemical characteristic is grown on the semiconductor substrate plate 21, the diffusion mask 3 arranged on the semiconductor crystal is applied as an etching mask, while an opening is formed in the semiconductor crystal 22, a diffusion is performed in the impurity gas so as to form a diffusion area 6, then the mask 3 and the crystal 22 are removed by a selective etching operation. Thereby, a normal diffusion is performed for the lower crystal 21 when no stress is applied thereto, while a normal diffusion shape may be provided, and thus it is possible to provide a sufficient reduction of crystal defects which may be caused by a stress therein.
JP8573480A 1980-06-24 1980-06-24 Selective diffusion process for impurity into semiconductor crystal Pending JPS5710924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8573480A JPS5710924A (en) 1980-06-24 1980-06-24 Selective diffusion process for impurity into semiconductor crystal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8573480A JPS5710924A (en) 1980-06-24 1980-06-24 Selective diffusion process for impurity into semiconductor crystal

Publications (1)

Publication Number Publication Date
JPS5710924A true JPS5710924A (en) 1982-01-20

Family

ID=13867062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8573480A Pending JPS5710924A (en) 1980-06-24 1980-06-24 Selective diffusion process for impurity into semiconductor crystal

Country Status (1)

Country Link
JP (1) JPS5710924A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4832469A (en) * 1971-08-31 1973-04-28
JPS4847770A (en) * 1971-10-18 1973-07-06
JPS50120258A (en) * 1974-03-05 1975-09-20

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4832469A (en) * 1971-08-31 1973-04-28
JPS4847770A (en) * 1971-10-18 1973-07-06
JPS50120258A (en) * 1974-03-05 1975-09-20

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