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JPS6459858A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6459858A
JPS6459858A JP21665387A JP21665387A JPS6459858A JP S6459858 A JPS6459858 A JP S6459858A JP 21665387 A JP21665387 A JP 21665387A JP 21665387 A JP21665387 A JP 21665387A JP S6459858 A JPS6459858 A JP S6459858A
Authority
JP
Japan
Prior art keywords
polysilicon
region
impurity region
semiconductor substrate
insulating oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21665387A
Other languages
Japanese (ja)
Inventor
Koji Suzukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP21665387A priority Critical patent/JPS6459858A/en
Publication of JPS6459858A publication Critical patent/JPS6459858A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To prevent a leakage current from being increased, by employing a specific process in which a polysilicon is deposited and heat-treated at the temperature suitable for the high depositing rate or the like of the polysilicon prior to an impurity diffusion during an impurity region being formed in the surface region of a semiconductor substrate. CONSTITUTION:A base impurity region 22 is selectively formed in the surface region of a semiconductor substrate 21. An insulating oxide film 23 is then formed over the whole surface of the semiconductor substrate 21. Subsequently, this insulating oxide film 23 is selectively patterned to form an opening 24 for an emitter diffusion on the base impurity region 22. Next, a non-doped polysilicon is deposited over the region including the base impurity region 22 corresponding to both a part of the insulating oxide film 23 thereon and the opening 24 at the temperature of 625+ or -10 deg.c in order to form a polysilicon film 25. This polysilicon film 25 is thereafter heat-treated in N2 gas at the temperature of 1100 deg.C, for example, for 2 minutes. Subsequently, the polysilicon film 25 is selectively patterned to form an emitter electrode. Next, impurity of P or the like is diffused into the polysilicon film 25 to form an emitter impurity region 26.
JP21665387A 1987-08-31 1987-08-31 Manufacture of semiconductor device Pending JPS6459858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21665387A JPS6459858A (en) 1987-08-31 1987-08-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21665387A JPS6459858A (en) 1987-08-31 1987-08-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6459858A true JPS6459858A (en) 1989-03-07

Family

ID=16691823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21665387A Pending JPS6459858A (en) 1987-08-31 1987-08-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6459858A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5340752A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method for forming a bipolar transistor using doped SOG
KR19980054454A (en) * 1996-12-27 1998-09-25 김영환 Polysilicon Cone Formation Method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5340752A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method for forming a bipolar transistor using doped SOG
KR19980054454A (en) * 1996-12-27 1998-09-25 김영환 Polysilicon Cone Formation Method

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