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JPS5633826A - Manufacture of target - Google Patents

Manufacture of target

Info

Publication number
JPS5633826A
JPS5633826A JP10914179A JP10914179A JPS5633826A JP S5633826 A JPS5633826 A JP S5633826A JP 10914179 A JP10914179 A JP 10914179A JP 10914179 A JP10914179 A JP 10914179A JP S5633826 A JPS5633826 A JP S5633826A
Authority
JP
Japan
Prior art keywords
target
photo resist
resist film
etching
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10914179A
Other languages
Japanese (ja)
Inventor
Kaoru Niino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10914179A priority Critical patent/JPS5633826A/en
Publication of JPS5633826A publication Critical patent/JPS5633826A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To prevent damage to a substrate by additionally covering the parts except the target forming region with a separate photo resist film wherein the above process is done when etching formation is made to the target pattern on a semiconductor substrate by consisting a photo resist as a mask. CONSTITUTION:When the target is made by utilizing photo etching process for isolation diffusion, an oxide film 8 is formed on the silicon substrate 7 and the oxide film 8 is furthermore covered with the first photo resist film 9. Next, a desired pattern is formed by partially exposing the photo resist film 9 and a window 10 for isolation and windows 11 for target are formed by consisting the photo resist film 9 as a mask and by etching the oxide film 8. After that, the surface of the first photo resist film 9 except the region which becomes a target is covered with the second photo resist film 12 and a target pattern 13 is formed on the silicon substrate 7 by etching treatment. In this way, damage to the isolation region 10 will be prevented.
JP10914179A 1979-08-29 1979-08-29 Manufacture of target Pending JPS5633826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10914179A JPS5633826A (en) 1979-08-29 1979-08-29 Manufacture of target

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10914179A JPS5633826A (en) 1979-08-29 1979-08-29 Manufacture of target

Publications (1)

Publication Number Publication Date
JPS5633826A true JPS5633826A (en) 1981-04-04

Family

ID=14502632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10914179A Pending JPS5633826A (en) 1979-08-29 1979-08-29 Manufacture of target

Country Status (1)

Country Link
JP (1) JPS5633826A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856333A (en) * 1981-09-29 1983-04-04 Fujitsu Ltd Formation of key pattern for mask alignment
JPH03105876A (en) * 1989-09-19 1991-05-02 Ngk Insulators Ltd Sodium-sulfur battery

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147179A (en) * 1975-06-12 1976-12-17 Fujitsu Ltd Method of munufacturing of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147179A (en) * 1975-06-12 1976-12-17 Fujitsu Ltd Method of munufacturing of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856333A (en) * 1981-09-29 1983-04-04 Fujitsu Ltd Formation of key pattern for mask alignment
JPH03105876A (en) * 1989-09-19 1991-05-02 Ngk Insulators Ltd Sodium-sulfur battery

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