JPH10107235A - Method for constituting gate array lsi and circuit device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the operation of circuit devices by providing construction of a gate array LSI with low parasitic self inductance from circuits and a power terminal to a bypass capacitor, where the bypass capacitor is packaged without increasing the chip size. SOLUTION: Among devices prepared for constructing logic circuits on the gate array LSI, devices not used for ordinary logic circuits (207 and 208) are used to form bypass capacitors 300. This provides the bypass capacitors very near the circuits and the power terminal without increasing the LSI area and reducing the packaging density of the circuit devices, thus stabilizes the operations of the circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit device which operates at high speed, and more particularly, to a gate array LSI having a built-in bypass capacitor which can be used to prevent electrical noise typified by power supply voltage fluctuation of the gate array LSI. The present invention relates to a method and a circuit device using the same.

[0002]

2. Description of the Related Art A semiconductor integrated circuit is used by being incorporated in a very large number of devices such as a computer, a personal computer, and a mobile phone. In particular, in a device for processing a signal at high speed typified by an electronic computer, a semiconductor integrated circuit having an extremely high operation speed and a large number of circuits is used in combination with the enhancement of the function. In such a semiconductor integrated circuit, when the circuit performs a switching operation, electrical noise caused by the switching current, that is, power supply voltage fluctuation occurs. This power supply voltage fluctuation increases as the circuit operation speed increases and the number of circuits that switch simultaneously increases. Fluctuations in the power supply voltage of the circuit cause problems such as deterioration of the operation speed of the circuit and malfunction. For this reason, a contrivance has been employed so that the fluctuation of the power supply voltage does not increase. The most typical countermeasure is to connect a bypass capacitor between the power supply terminals of the circuit.

The conventional example shown in FIG. 3 shows a state in which a bypass capacitor 103 is connected between the positive and negative power supply terminals VDD and GND of the integrated circuit 1. Power supply terminal VD
D and GND are connected to the substrate 100 first, and the through holes and the power supply layer wirings 101 and 102 arranged in the substrate 100 are connected.
To the bypass capacitor.

FIG. 4 shows still another conventional example for connecting a bypass capacitor. This technology is disclosed in, for example, IEE Journal of Solid State Circuits, Volume 25, Number 5, Oktober 1990 (IEEE JOURNAL OF
SOLID-STATE CIRCUITS, VO
L. 25, NO. 5, OCTOBER 1990), pages 1166 to 1177 (especially FIG. 15). A logic circuit group 114 formed on the chip is connected between the power supply lines 112 and 113 in the chip laid out on the integrated circuit 1. In this figure, 112
Corresponds to the positive power supply VDD, and 113 corresponds to the negative power supply GND. In this conventional example, a p-channel MOS transistor 110 formed on a chip and connected between power supply lines in the chip, and an n-channel MOS transistor 1
The parasitic capacitance 11 between the gate and the source and between the gate and the drain has the function of a bypass capacitor. Although only two transistors for a bypass capacitor are shown in the figure, a design is generally made so that the capacitance of the bypass capacitor is increased by forming a plurality of transistors for a bypass capacitor on a chip.

[0005]

In FIG. 3 described above, the power supply terminal of the integrated circuit and the wiring from the logic circuit which is actually switched to the bypass capacitor are long, and especially when the circuit operates at high speed. The problem is that the bypass capacitor does not function effectively due to the influence of parasitic self-inductance generated in the wiring. For example, when the length of the wiring is about 5 mm, the parasitic self-inductance becomes about 4 nH when the diameter of the through hole is 100 μm. Further, in FIG. 3, since the area for mounting the bypass capacitor is required separately from the area occupied by the integrated circuit, there is another problem that the connection density of the entire device is reduced by connecting the bypass capacitor.

In FIG. 4, since the bypass capacitor is formed in the integrated circuit, there is no problem of parasitic self-inductance as shown in FIG. However, since a transistor for a bypass capacitor is arranged in a chip, it is necessary to secure a transistor area for forming a bypass capacitor separately from a circuit for realizing a logic operation on an integrated circuit. There is another problem of increasing. This further leads to a problem that the mounting density of the entire device is reduced.

According to the present invention, there is provided a gate capable of realizing a bypass capacitor without reducing the parasitic self-inductance from a power supply terminal and a switching logic circuit to a bypass capacitor, further increasing the chip area of the LSI, and without deteriorating the packaging density. An object of the present invention is to provide a method of configuring an array LSI.

[0008]

According to the present invention, there is provided an element prepared in advance on a gate array LSI in order to form a logic circuit. However, the element is not used as a logic circuit but is arranged and wired. A bypass capacitor circuit is formed by using the elements that are left unused later.

An element for forming a bypass capacitor is located in a part of a region prepared in advance for forming a logic circuit, and is located closer to a circuit than a power supply pad of an LSI. Since the length of the wiring from the bypass capacitor to the circuit performing the switching operation can be as long as several hundreds μm, generally about several tens μm, the influence of the parasitic self-inductance becomes very small.

According to the present invention, the elements constituting the capacitance of the bypass capacitor circuit are elements that have been formed in advance on the LSI and have not been used as a logic circuit in the logic circuit formation region. . Therefore, there is no deterioration in the mounting density as seen in the conventional example of FIG.

Further, unlike the conventional example shown in FIG. 4, it is not necessary to form another transistor for the logic circuit in the LSI in order to form a bypass capacitor. Therefore, the area of the LSI does not increase.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A gate array LSI will be described as an example.
The method of forming the circuit and wiring of the S gate array LSI will be briefly described.

FIG. 5 shows a general CMOS gate array LS.
It is the figure which expanded and displayed a part of surface pattern of I. In this figure, the grid positions (204, 205) where the transistors (206) whose terminals are not connected anywhere, the power supply wirings (VDD, GND), and the signal wirings can be arranged are shown.
(Solid line in) is shown. In-circuit wiring and inter-circuit wiring for connecting the terminals of the transistors to realize a desired logic operation have not been formed yet. In a CMOS gate array LSI, only a transistor and a power supply line are prepared as common components, and an LS including necessary logic is added by appropriately adding a line connecting the terminals of the transistor.
Develop I varieties. Although not shown in the figure, VDD
Each of the wiring and the GND wiring extends long in the X direction (horizontal direction in the drawing) and is connected to a power supply pad for receiving power from outside the LSI. In addition, the power supply wiring is generally prepared not only in the X direction but also in the Y direction (vertical direction in the figure). In this case, the same type of power supply wiring (for example, VDD) running in each of the X direction and the Y direction is connected to each other,
It is common practice to lower the impedance of the power supply system.

In FIG. 1, reference numeral 200 denotes a pattern to be a gate electrode of a p-channel MOS transistor (hereinafter abbreviated as pMOS). Reference numeral 202 denotes a p-type semiconductor region for forming source and drain electrodes of the pMOS. Similarly 2
03 is an n-channel MOS transistor (hereinafter referred to as nM
A gate electrode 201 (abbreviated as OS) is an n-type semiconductor region serving as source and drain electrodes of the nMOS. pM
A transistor pair 206 including one OS and one nMOS
Are regularly arranged in the LSI. pMOS source,
The wiring VDD of the positive power supply passes over the drain. V
The voltage of DD is generally set to 5V or 3.3V. Similarly, a wiring GND of a negative power supply passes over the source and drain of the nMOS. GND is generally set to 0V.

A group of solid lines 204 represents the grid positions of signal wirings running in the X direction on the paper. Similarly, a solid line group 205 represents a grid position of a signal wiring running in the Y direction on the paper surface. In a gate array LSI, a desired logic is realized by appropriately connecting signal terminals of a circuit. At this time, a wiring connecting the signal terminals is not arranged at an arbitrary position on the LSI. Generally, a virtual grid is formed in each of the X direction and the Y direction, and the wiring generally passes only on the grid. In the example of FIG. 5, since the metal of the same layer as the power supply wiring is used for the signal wiring in the X direction, no grid is formed at the position of the power supply pattern, thereby preventing the signal and the power supply from being short-circuited. I have.

FIG. 6 is a circuit diagram equivalent to the CMOS gate array LSI shown in FIG. PMOS consisting of terminals 200 and 202 and nMO consisting of terminals 201 and 203
The transistor pairs 206 composed of S are regularly arranged, and the power supply lines VDD and GND run there.

FIG. 7A is a sectional view of a pMOS. 2
Reference numeral 00 denotes a gate electrode, 202 denotes a source or drain electrode, which is also shown in FIG. 230 is an n-type semiconductor region, and 231 is an insulator for electrically isolating the transistors. M1
Denotes a first-layer metal wiring. M2 is a second-layer metal wiring. M1 and M are signal wirings connecting power supply wiring and circuits.
Metal wiring such as 2 is used. In FIG. 5, VDD,
The M1 layer is used for the wiring forming GND, the M1 layer is also used for the X-direction signal wiring 204 showing only the grid position, and the M2 layer is used for the Y-direction signal wiring 205 showing only the grid position. Reference numeral 232 denotes an interlayer insulating film for electrically separating the M1 wiring layer from the gate electrode, the source, and the drain electrode. 233 is an interlayer insulating film for separating the M1 layer and the M2 layer. CONT is a hole formed in 232 for electrically connecting the p-type semiconductor region 202 and M1, and a metal filled in the hole. Even if M1 and 202 overlap on the XY coordinates, they do not have electrical continuity if there is no CONT there. Although not shown in FIG. 7A, CO is also used to connect the gate electrode 200 and M1.
NT is used. TH is a hole formed in the hole 233 and metal filled in the hole, and is used for electrically connecting M1 and M2. X between M1 and M2 is the same as before.
If there is no TH at the intersection on the Y coordinate, conduction does not occur.

FIG. 7B is a sectional view of the nMOS. 2
01 is an n-type semiconductor region for forming a source electrode and a drain electrode. 203 is a gate electrode. 234 is p
Type semiconductor region. Other components are the same as those shown in FIG.

FIG. 8 is a diagram showing a state in which wiring, CONT, and TH are added to the base pattern shown in FIG. 5 to form two CMOS inverter circuits 207 and 208.
In the figure, the crosses indicate CO described in FIGS. 7A and 7B.
NT indicates a certain position. Similarly, the black diamond is T
H represents the position. In the inverter circuit 207, 209 is an M1 wiring for an input terminal, and 211 is an M1 wiring for an output terminal. The source electrodes of the pMOS and nMOS are connected to VDD and GND by CONT, respectively. The gate electrodes of both transistors are CON
They are connected via T and M1. The drain electrodes of both transistors are also connected via CONT and M1, and M1 is an output terminal 211. Similarly, in the inverter circuit 208, 216 is CONT, M1
This is the output terminal formed by. Input terminal is M1 wiring 21
4 and an M2 wiring 215 connected to it via TH. FIG. 8 shows an M1 signal wiring 220 for connecting between circuits outside the illustrated range, in addition to the inverter circuit. The other M1 wirings 221 and M2 wirings 222 and the TH connecting them are signal wirings for connecting circuits outside the illustrated range, similarly to 220.

FIG. 9 shows the gate array LSI shown in FIG.
It is a circuit diagram equivalent to FIG. Input terminal 209 and output terminal 21
1 and an inverter circuit 208 having an input terminal 215 and an output terminal 216 are formed. Other transistor pairs 206 remain unused. Signal wirings 220 and 221 connecting logic circuits outside the illustrated range are also shown.

As shown in the examples of FIGS. 8 and 9, a gate array LSI generally uses only a part of the transistors arranged to form a logic circuit, and it is difficult to use all of the transistors. It is rare. The present invention stabilizes the circuit operation by forming a bypass capacitor using an unused logic circuit forming transistor.

An embodiment of the present invention will now be described with reference to FIGS.
Description will be made from 0 to FIG.

FIG. 10A shows a set of pMOS and nMO
FIG. 5 is a diagram showing an example of a layout when a bypass capacitor is made using S. In the figure, the hatching on the upper right indicates the M1 wiring added to form the bypass capacitor circuit, and the hatching on the lower right indicates the M2 wiring added for forming the bypass capacitor circuit. Both the source electrode and the drain electrode of the pMOS are connected to GND. pMO
The gate electrode of S is connected to VDD. The source and drain electrodes of the nMOS are connected to VDD. nMOS
Are connected to GND.

FIG. 10B is a circuit diagram equivalent to the layout shown in FIG. pMOS gate-source capacitance, gate-drain capacitance (CP1, CP
2) Reverse-biased parasitic diodes (DP1, DP2) generated between the source electrode and the drain electrode and VDD.
Depletion layer acts as a bypass capacitor. Similarly, the capacitance between the gate and source of the nMOS, the capacitance between the gate and drain (CN1, CN2), and the depletion layer capacitance of the parasitic diodes (DN1, DN2) between the source electrode, the drain electrode and GND also function as bypass capacitors.

FIG. 2 shows a gate array LSI using the present invention.
FIG. In FIG. 8, the transistor pair 206 which is not used and not used for forming the logic circuit is used.
Is replaced by a bypass capacitor circuit 300. In the plurality of bypass capacitor circuits 300 shown in FIG.
The layout patterns of the wirings M1 and M2 added for the bypass capacitor are different from each other. Since the layout method is not the essence of the present invention, the existing signal wiring (220, 221 in the figure) and the wiring in the circuit (209, 211, 21) are used.
4, 215, 216).

FIG. 1 is a circuit diagram equivalent to the layout shown in FIG. The transistor pair 206 that has not been used and left unused to form the logic circuit in FIG.
The configuration is changed to the bypass capacitor circuit 300 shown in FIG.

As is apparent from FIGS. 1 and 2, when the present invention is used, even if a bypass capacitor is formed on an LSI, there is no increase in the area of the LSI caused by that. In addition, since the bypass capacitor can be arranged very close to the switching circuit, the circuit operation is less likely to be affected by the parasitic inductance and the circuit operation can be effectively stabilized.

FIGS. 1 and 2 show a state in which all of the unused transistor pairs 206 in FIGS. 8 and 9 are replaced with the bypass capacitor circuit 300, but it is not always necessary to replace all of them. Generally, the larger the bypass capacitor capacitance, the more stable the circuit operation. However, even if unused elements remain on the LSI, the essence of the present invention is not impaired.

FIG. 11 is a diagram showing a second transistor connection method for forming a bypass capacitor circuit. FIG. 11A is a layout when only the pMOS is used as the bypass capacitor. FIG. 11B shows the nMO
This is a layout when only S is used as a bypass capacitor. The bypass capacitor circuit need not be a pair of the pMOS and the nMOS, but may be only one of them.

FIG. 12 is a diagram showing a third transistor connection method for forming a bypass capacitor circuit. FIG. 12A shows an example of the layout, and FIG.
Fig. 2 shows a circuit diagram represented by the layout. FIG.
(A) and (b) show C in which the input is fixed to a logic low level.
It is a MOS inverter circuit. pMOS gate-drain capacitance CP1, gate-source capacitance CP
2. A gate-to-substrate capacitance CP3, a drain-to-substrate parasitic diode DP1, an nMOS gate-to-drain capacitance CN1, and a drain-to-substrate parasitic diode DN1 are connected between the VDD power supply and the GND power supply, and are bypass capacitors. Act as

FIG. 13 is a diagram showing a fourth transistor connection method for forming a bypass capacitor circuit. FIG. 13 is also a CMOS inverter circuit like FIG. 12, but the input is fixed at a logical high level. When the input is fixed at a logical high level, the gate-source capacitance and the gate-substrate capacitance of the pMOS do not function as a bypass capacitor, as shown in FIG. In this configuration, the gate-source capacitance CN1 and the gate-substrate capacitance CN3 of the nMOS have the function of a bypass capacitor.

In FIG. 13A, a line (LINE) is connected to the output terminal of the inverter circuit. FIG.
As shown in (b), the wiring capacitance (C
LP, CLN), which can also be used as a bypass capacitor. The longer the wiring (LINE), the larger the wiring capacitance (CLP, CLN), and the more effective the bypass capacitor. However, it is not always necessary to connect a wiring to the output terminal. It only needs to be performed when wiring can be added.

Not only an inverter circuit but also a normal logic circuit such as a NOR circuit or a NAND circuit can be used as a bypass capacitor. In this case, the input terminal is fixed to a logic high level or a logic low level so that the bypass capacitor circuit is not switched unnecessarily.

Connecting a wiring to the output terminal and using the inverter circuit as a bypass capacitor are independent. Wiring may be connected to the output terminal of a normal logic circuit.

FIG. 14 shows a fifth transistor connection method for forming a bypass capacitor. FIG.
(A) shows a case where the source electrode and the drain electrode are connected to the positive power supply VDD, and the gate electrode is connected to the negative power supply GND.
I am making bypass capacitors with MOS. In this connection, the gate-source capacitance, the gate-drain capacitance (CP1, CP2), the gate-substrate capacitance (C
P3) becomes a bypass capacitor. FIG. 14B shows that the source electrode and the drain electrode are connected to the negative power supply GND,
A bypass capacitor is formed by an nMOS whose gate electrode is connected to the positive power supply VDD. In this connection, nMO
The gate-source capacitance, gate-drain capacitance (CN1, CN2), and gate-substrate capacitance (CN3) of S constitute a bypass capacitor.

The bypass capacitor circuit shown in FIG.
0, p in the bypass capacitor circuit shown in FIG.
In this circuit, the source and drain electrodes and the gate electrode of each of the MOS and nMOS are connected such that the positive side and the negative side are reversed. If an element is connected so that a capacitance is added between power supplies for which power supply fluctuation is to be suppressed, a bypass capacitor circuit is formed. Therefore, transistors may be connected in this way.

In the embodiments shown in FIGS. 1 and 2, all the bypass capacitor circuits 300 use the circuit shown in FIG. 10, but another bypass capacitor circuit shown in FIGS. 11 to 14 may be used. Absent. Further, a plurality of types of bypass capacitor circuits may be mixed in one LSI.

FIG. 15 shows a sixth transistor connection method for forming a bypass capacitor. FIG.
(A) shows a case where a bypass capacitor is formed using an npn-type bipolar transistor. The collector terminal and the emitter terminal are connected to the positive side of the power supply between which power supply fluctuation is to be suppressed, and the base terminal is connected to the negative side power supply. With this connection, the base-collector capacitance Cbc1 and the base-emitter capacitance Cbe1 of the transistor enter between the power supplies in parallel, thereby suppressing the fluctuation of the power supplies. FIG. 14B similarly shows an example in which a bypass capacitor is formed using a pnp bipolar transistor. In a pnp type bipolar transistor, a collector terminal and an emitter terminal are connected to a negative power supply, and a base terminal is connected to a positive power supply. Also in this case, the base-emitter capacitance Cb of the transistor
e2 and the base-collector capacitance Cbc2 act as a bypass capacitor. In the case of a gate array LSI using bipolar transistors, among the elements prepared for forming a logic circuit, the remaining transistors may be connected as shown in FIG.

[0039]

According to the present invention, a bypass capacitor can be arranged very close to a circuit and a power supply terminal without deteriorating the mounting density of a circuit device, and the circuit operation can be stabilized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an LSI layout pattern according to the embodiment of the present invention.

FIG. 3 is a diagram showing a first conventional example showing a mounting method of a bypass capacitor.

FIG. 4 is a diagram showing a second conventional example of a mounting method of a bypass capacitor.

FIG. 5 shows a circuit of a general CMOS gate array LSI,
The figure which shows a part of power supply wiring pattern.

6 is a circuit diagram equivalent to the layout pattern shown in FIG.

FIG. 7 is a cross-sectional view of a p-channel MOS transistor and an n-channel MOS transistor.

FIG. 8 is a diagram in which two inverters and two kinds of signal wirings are formed on the LSI shown in FIG. 5;

FIG. 9 is a circuit diagram equivalent to the layout pattern shown in FIG.

FIG. 10 is a diagram showing a first connection method of a transistor and a circuit configuration thereof for forming a bypass capacitor.

FIG. 11 is a diagram showing a first method of connecting transistors to form a bypass capacitor.

FIG. 12 is a diagram showing a third method of connecting transistors for forming a bypass capacitor and a circuit configuration thereof;

FIG. 13 is a diagram showing a fourth connection method of a transistor and a circuit configuration thereof for forming a bypass capacitor.

FIG. 14 is a circuit diagram showing a fifth connection method of a transistor for forming a bypass capacitor.

FIG. 15 is a circuit diagram showing a sixth connection method of a transistor for forming a bypass capacitor.

[Explanation of symbols]

VDD, GND: power supply, 207, 208: inverter circuit, 300: bypass capacitor.

Claims (11)

[Claims] An element for forming a logic circuit and a power supply line for supplying power to the logic circuit are prepared in advance on a chip, and a part of the element and a part of the power supply line are provided. A logic circuit is created by using a logic circuit, and a desired logic function is realized by connecting the logic circuits. Among the elements prepared in advance, those elements that were not used to configure the logic circuit A method of forming a gate array LSI, comprising forming a bypass capacitor between power supply wirings on an integrated circuit by using at least a part thereof. 2. The p-channel MOS transistor according to claim 1, wherein at least a part of said bypass capacitor is a p-channel MOS transistor having a gate electrode connected to a positive power supply and a source electrode and a drain electrode connected to a negative power supply. The gate array LSI. 3. An n-channel MOS transistor in which at least a part of the bypass capacitor is an n-channel MOS transistor having a gate electrode connected to a negative power supply and a source electrode and a drain electrode connected to a positive power supply. The gate array LSI. 4. A p-channel MOS transistor having a gate electrode connected to a negative power supply and a source electrode and a drain electrode connected to a positive power supply, at least a part of said bypass capacitor. The gate array LSI. 5. The at least part of the bypass capacitor is an n-channel MOS transistor having a gate electrode connected to a positive power supply and a source electrode and a drain electrode connected to a negative power supply. The gate array LSI. 6. The gate according to claim 1, wherein at least a part of said bypass capacitor is an npn-type bipolar transistor having a base electrode connected to a negative power supply and a collector electrode and an emitter electrode connected to a positive power supply. How to configure an array LSI. 7. The gate according to claim 1, wherein at least a part of said bypass capacitor is a pnp bipolar transistor having a base electrode connected to a positive power supply and a collector electrode and an emitter electrode connected to a negative power supply. How to configure an array LSI. 8. At least a part of said bypass capacitor is at least one element connected to form a logic circuit, said element being a p-channel MOS transistor, an n-channel MOS transistor, or an n-channel MOS transistor.
at least one of either a pn bipolar transistor or a pnp bipolar transistor or a resistor;
2. A method for configuring a gate array LSI according to claim 1, comprising: 9. A method according to claim 8, wherein one of a logic high level and a logic low level is applied to an input terminal of said logic circuit. 10. A method according to claim 8, wherein a signal wiring having a finite wiring length is connected to an output terminal of said logic circuit. 11. A circuit device comprising a gate array LSI constituted by at least one method according to any one of claims 1 to 10.