CN1294642C - Analysis method and reduction method of power supply noise - Google Patents

Abstract

A method for analyzing power noise and a method for reducing power noise are applied in the design process of an integrated circuit. Firstly, computer aided design software is used to analyze the related data of the integrated circuit design to obtain the power network model of the integrated circuit design, then, the power network model is defined as being composed of multiple unit blocks connected with each other, and on the other hand, after analyzing the related data of the integrated circuit design, the number and type parameters of the elements electrically connected to each unit block can be known as the reference data of the elements of the power network model unit block, and the voltage drop caused by the operation of each unit block can be estimated by using the equivalent circuit formed by the elements electrically connected to the unit blocks, so as to know the voltage distribution and voltage consumption consumed by each area in the power network model, and accordingly, the decoupling capacitor is configured at the proper position of the power network model, to properly compensate the voltage drop caused by the operation of the devices in the integrated circuit, thereby reducing the power noise in the integrated circuit.

Description

Analysis method and reduction method of power supply noise

technical field

The present invention relates to integrated circuit technology, and relates to an analysis method and reduction method of power noise (Power Noise). Capacitors are arranged in the integrated circuit to reduce power noise in the integrated circuit.

Background technique

With the development of semiconductor manufacturing technology and integrated circuit design, various integrated circuits with different functions are widely used in many electronic products. At the same time, the line size of semiconductor components has entered sub-micron (Sub-Micro) or even deep sub-micron (Deep Sub-Micro) field, and the integration of integrated circuits is also increasing rapidly. Since the surface of the semiconductor structure cannot provide enough area to make the interconnection (Interconnection) required by the semiconductor element, the technology of multilevel interconnection (Multilevel Interconnection) has been developed, using several layers of metal layers and dielectric layers for semiconductor The wiring and isolation work between components, and the metal wiring that supplies power to semiconductor components constitutes the power supply network of integrated circuits.

In integrated circuits in the deep sub-micron field, signal processing and transmission are often disturbed by many noises, such as leakage current noise, crosstalk noise (Crosstalk Noise), reflection noise (Reflection Noise) and power supply noise ( Power Supply Noise), etc., when the operating frequency of integrated circuits is getting higher and higher, the interference of power supply noise will become more serious, so it is necessary to analyze the power supply network.

When analyzing the efficiency of the power network, the main things to pay attention to are Electromigration and Voltage Drop. When the current density flowing through the conductive metal wire is too high, the atoms in the metal wire will migrate, causing the metal wire in the wafer to age rapidly and become invalid.

In order to allow the semiconductor elements at various positions in the chip to obtain sufficient voltage to operate, it is necessary to avoid excessive voltage drop in the chip. In other words, if some semiconductor elements in the chip generate a very large voltage drop during operation, other semiconductor elements in the chip (especially the semiconductor elements located in the center of the chip) will not be able to obtain sufficient voltage to operate, and the performance of the integrated circuit will be reduced. drop, or even malfunction.

As the operating frequency of integrated circuits is greatly increased, the switching speed of semiconductor elements in the chip is also increased at the same time. Due to the instantaneous electrical changes when semiconductor elements switch states, voltage surges will be caused, and this fluctuation will cause instantaneous voltage drop, and create noise between power and ground. With the increase of the operating frequency, transmission speed and density of electronic circuits, the noise is also greatly increased, which seriously affects the normal operation of the system and causes malfunctions.

In view of the above-mentioned background of the invention, with the progress of semiconductor manufacturing technology and integrated circuit design, the operating frequency of integrated circuits is getting higher and higher, and the area of chips is also getting larger and larger at the same time. The resulting voltage drop is getting bigger and bigger. At the same time, the high operating frequency of semiconductor components also causes serious power noise, which interferes and pollutes normal circuit operation signals and power supply, and affects the operating performance of integrated circuits and the accuracy of signal processing.

Contents of the invention

The main purpose of the present invention is to provide a power supply noise analysis method and its reduction method. During the integrated circuit design process, by defining the power supply network of the integrated circuit layout (Layout) to be composed of many unit blocks, and according to Components electrically connected to each unit block, such as logic elements, logic circuits (such as D-type flip-flops; D-Flip-Flop) and clock buffers used to construct a clock tree (Clock Tree) and clock transmission After estimating the voltage drop and power supply noise caused by each unit block during operation, a capacitor used to compensate for the voltage drop can be configured at an appropriate position in the integrated circuit layout to reduce Voltage disturbances and power supply noise.

In order to achieve the above-mentioned purpose, the present invention provides a power supply noise analysis method and its reduction method. First, use Computer Aided Design (Computer Aided Design) software to analyze the chip power supply of the relevant design data of the integrated circuit, so as to obtain After the power network model of the integrated circuit design, the power network model is defined as being composed of many unit blocks connected to each other. After analyzing the relevant information of the integrated circuit design, the number and number of components electrically connected to each unit block can be known. Type and other parameters, as the component reference data of the unit block, and then according to the component reference data of each unit block, use the equivalent circuit composed of the components electrically connected to the unit block, and use the circuit simulation software to estimate the unit block in the According to the voltage drop caused by the operation, the distribution of the voltage consumed by each area in the power network model and the voltage consumption can be known. Based on this, decoupling capacitors are arranged at appropriate positions in the power network model to properly compensate the voltage in the integrated circuit. The voltage drop caused by the device during operation, thereby reducing the power supply noise in the integrated circuit.

More specifically, the present invention provides a method for analyzing power supply noise, which is applied in integrated circuit design. The analysis method for power supply noise at least includes:

providing a power network model of the integrated circuit design;

defining the power network model to be composed of a plurality of unit blocks according to a predetermined method;

Obtaining a plurality of data of a plurality of components electrically connected to each unit block according to a position and a covered area of each unit block in the power network model, and using these data as a reference material for each unit block; as well as

According to the reference materials of the unit blocks, an AC analysis step is performed to obtain an AC analysis result of the power network model.

In the method for analyzing power supply noise, the above-mentioned AC analysis results at least include the power consumed and the voltage drop caused by each unit block during operation.

The power supply noise analysis method further includes performing a power supply network analysis step on the integrated circuit design, so as to obtain the power supply network model of the integrated circuit design.

In the method for analyzing power supply noise, the above-mentioned power supply network model includes a DC power supply network model data and an AC power supply network model data of the integrated circuit design.

The method for analyzing power supply noise, wherein the above predetermined method is to define the unit blocks of the power supply network model as a plurality of rectangles by means of a plurality of metal wires constituting the power supply network model, wherein the rectangles are formed by the metal wires line composition.

In the method for analyzing power supply noise, the elements at least include a plurality of logic elements, a plurality of timing buffers, and a plurality of parasitic elements.

In the method for analyzing power supply noise, the parasitic elements at least include a plurality of parasitic decoupling capacitors.

The method for analyzing power supply noise, after obtaining the AC analysis result of the power network model, further includes disposing a plurality of decoupling capacitors in a plurality of positions of the integrated circuit design according to the AC analysis result.

The present invention provides a method for reducing power supply noise, which is applied in the design of an integrated circuit. The method for reducing power supply noise at least includes:

providing a power network model of the integrated circuit design;

defining the power supply network model to be composed of a plurality of unit blocks according to a predetermined method;

Obtaining a plurality of data of a plurality of components electrically connected to each unit block according to a position and a covered area of each unit block in the power network model, and using these data as a reference material for each unit block;

According to the reference materials of the unit blocks, an AC analysis step is performed to obtain an AC analysis result of the power network model; and

According to the AC analysis result, a plurality of decoupling capacitors are arranged in a plurality of positions in the integrated circuit design.

In the method for reducing power supply noise, the above-mentioned AC analysis results at least include the power consumed by each unit block and the voltage drop caused during operation.

The method for reducing power supply noise further includes performing a power network analysis step on the integrated circuit design, so as to obtain the power network model of the integrated circuit design.

In the method for reducing power supply noise, the above-mentioned power supply network model includes a DC power supply network model data and an AC power supply network model data of the integrated circuit design.

The method for reducing power supply noise, wherein the above predetermined method is to define the unit blocks of the power supply network model as a plurality of rectangles by means of a plurality of metal lines constituting the power supply network model, wherein these rectangles are formed by these metal lines .

In the method for reducing power supply noise, the elements at least include a plurality of logic elements, a plurality of timing buffers and a plurality of parasitic elements.

In the method for reducing power supply noise, the parasitic elements at least include a plurality of parasitic decoupling capacitors.

Description of drawings

Fig. 1 is a schematic diagram of the processing flow of one embodiment of the present invention;

FIG. 2 is a schematic top view of a defined power network model during the integrated circuit design process according to FIG. 1 ;

FIG. 3 is a schematic diagram of the connection relationship of components in the unit block in the power network model of FIG. 2 .

Detailed ways

Please refer to FIG. 1 , which is a schematic diagram of a processing flow according to an embodiment of the present invention. As shown in Figure 1, in order to obtain the power network model of the integrated circuit design first, in the power network analysis 30 of the processing flow 10, first input the relevant design reference materials 20 of the integrated circuit design, and use computer-aided design software to perform chip Power analysis (Chip Power Analysis), in order to obtain the power network model of the integrated circuit design, according to the power network model of the integrated circuit design, can obtain the characteristic parameters and data of the DC power network model and the AC power network model of the integrated circuit design Among them, the reference materials about integrated circuit design generally include: standard component database, power network impedance, operating frequency, operating temperature range, temperature coefficient, voltage drop range, and the length of each metal line in the power network metal layer Relevant parameters and data such as width, resistance per unit area of metal wires and distance between metal wires.

Please refer to FIG. 2 , which shows a schematic top view of the power network model defined during the integrated circuit design process according to FIG. 1 , wherein the power network model 100 is composed of metal layers 120 and 130, and the metal The layer 120 and the metal layer 130 respectively include a plurality of metal wires 140 and metal wires 150 , and each unit block 110 is connected to each other in the form of an equivalent circuit. In order to facilitate the simulation and estimation of the normal and transient conditions of the huge power network model 100 during operation, after obtaining the power network model 100 for integrated circuit design, the definition unit block and component analysis 40 of the processing flow 10 are performed, according to the power supply The area of the network model 100 and the metal wires in each metal layer that constitute the power network model 100 define the power network model 100 to be composed of many unit blocks 110 connected to each other, wherein the components contained in each unit block 110 The type and quantity are determined according to the design and layout of the integrated circuit, as well as the location and coverage of each unit block 110 in the power network model 100 . Therefore, through the steps of defining the unit block, the analysis of the power network model of the integrated circuit design can be made faster and more accurate.

For example, as shown in FIG. 2 , if the power network model 100 is composed of a metal layer 120 and a metal layer 130, then the power network model 100 can be defined to use two metal wires at the metal layer 120 for each unit block 110 140 and two metal wires 150 on the metal layer 130 to form a rectangular block.

Please refer to FIG. 3 , which is a schematic diagram of the connection relationship of the components in the unit block in the power network model of FIG. 2 . The unit block 110 shown in FIG. 3 includes many logic elements, logic circuits for constructing a clock tree and clock transfer, and a clock buffer. For example, two logic elements-D-type flip-flops ( D-Flip Flop) (D-type flip-flop 160 and D-type flip-flop 170), two timing buffers (timing buffer 180 and timing buffer 190), and other parasitic elements 200, such as on-chip parasitic Decoupling capacitor (On-chip Parasitic Decoupling Capacitance), etc., but the number and types of components in the unit block 110 are not limited to those shown in FIG. 3 , but depend on the design.

Next, in order to conduct AC analysis on the power network model 100 defined as being composed of many unit blocks 110, so as to know the voltage drop generated by each unit block 110 corresponding to the circuit at each position in the chip, it is necessary to perform transient analysis on the components (Transient Analysis) or AC analysis, using the information about various components in the reference component database to analyze each unit block 110 in the power network model 100 of FIG. type, quantity, operational parameters, geometric parameters and other relevant data.

For example, according to the information about various components in the reference component database, component analysis is performed on the unit block 110 in FIG. flip-flop), two timing buffers, and other parasitic elements, wherein the D-type flip-flop 160 is a first-type D-type flip-flop, and the D-type flip-flop 170 is a second-type D-type flip-flop , and the timing buffer 180 is a timing buffer belonging to the A type, and the timing buffer 190 is a timing buffer belonging to the B type, and other parasitic elements 200 include parasitic capacitances in the chip, etc., these elements are in the unit block 110 In the equivalent circuit, they are all connected between the metal wire 210 (the metal wire for supplying the operating power) and the metal wire 220 (the metal wire for the ground or virtual ground). In addition, the resistance 240 and the resistance 250 of the metal line 210 and the metal line 220, and the connection of the input/output terminals of the elements electrically connected to the unit block 110, such as the timing input of the logic element and the output of the logic element, need to be considered. In order to obtain the complete reference material of each component electrically connected to the unit block 110 , and use it as the component reference material of the unit block 110 , it is necessary to obtain relevant information such as the input and the output of the timing buffer.

Then, according to the component reference materials containing each unit block 110, the AC analysis 50 can be performed on the power network model 100 of the integrated circuit by using circuit simulation and analysis software such as Hspice, so as to estimate the components electrically connected to each unit block 110 The power consumed and the voltage drop caused during transient operation can be used to know the power consumed and the voltage drop caused by each unit block 110 in the power network model 100, and finally, the power supply to the integrated circuit on the chip can be obtained. Distribution of power attenuation at each location.

However, due to the increasingly powerful functions of today's integrated circuits, many elements or semiconductor elements need to be used to form them. Therefore, the number of elements electrically connected to each unit block 110 is very large. If all elements electrically connected to each unit block 110 If all the relevant data are put into the AC analysis 50 of the power network model 100, the time and system resources will be very considerable, which will greatly increase the design cost of the integrated circuit and increase the cost of the product. Before the communication analysis of the model 100, the screening process 70 of the process flow 10 in FIG. 1 can be performed first.

The so-called screening process 70 is to evaluate the power consumption and the voltage drop caused by each component to the unit block 110 according to the type, quantity, operating parameters, geometric parameters and other relevant data of each component in the component reference data of the unit block 110. Influence, the components that have little influence on the power consumption and the voltage drop caused are eliminated, so as to reduce the data involved in the AC analysis of the power network model 100, reduce the time and system resources required for analysis, and at the same time the AC analysis of the power network model 100 The accuracy of the results will not be seriously affected.

For example, in the screening process 70 of the processing flow 10 in FIG. 1 , the analysis and reduction method of power supply noise of the present invention provides two preset screening steps (screening step 80 and screening step 90), in order to explain the relevant settings and operation, but this is for illustration only, and does not limit the implementation method of the screening process 70 or the number of screening steps.

The screening ranges of these two preset screening steps are not the same, and can be adjusted or modified according to different IC designs and components used to reduce the time and system resources required for analysis without seriously The purpose of affecting the accuracy of the AC analysis results of the power network model 100 .

For example, the unit block 110 of FIG. 3 includes a first type D-type flip-flop 160 and a second type D-type flip-flop 170. When analyzing and comparing the D-type flip-flop 160 and the D-type flip-flop After the 170 consumes power and causes voltage drop during operation, it is known that the power consumption and voltage drop caused by the first type D-type flip-flop 160 in operation are far greater than those of the second type D-type flip-flop 170 Power consumption and the resulting voltage drop, so when estimating the power consumption and the voltage drop caused by the unit block 110 in operation, the component data of the D-type flip-flop 170 of the second type need not be involved in the calculation, so as to reduce Estimate the time spent. Moreover, according to the design of the integrated circuit, the relevant data of the components used, and the scheduled time-consuming of the AC analysis, the screening step 80 can be set to only select the D-type front and back of the first type in the component reference materials of the unit block 110. The relevant data of the device 160 is used to participate in the AC analysis 50 of the power network model 100, while the relevant data of other components in the component reference data of the unit block 110 are eliminated. Similarly, in other preset screening steps, it can also be set according to different design conditions and various related reference data, thereby reducing the data involved in the AC analysis of the power network model 100, so as to reduce the analysis requirements. At the same time, the accuracy of the AC analysis results of the power network model 100 will not be greatly reduced.

On the other hand, in the above example, only the unit block 110 contains a first type D-type flip-flop 160, a second type D-type flip-flop 170, an A-type timing buffer 180 and a The B-type timing buffer 190 is taken as an example. If a unit block includes a plurality of D-type flip-flops 160 of the first type, a plurality of D-type flip-flops 170 of the second type, and other different elements, It is necessary to conduct a detailed analysis of the power consumed and the voltage drop caused by these D-type flip-flops 160, D-type flip-flops 170 and other components during operation before deciding which components to use to participate in the power network model 100 communication analysis. Otherwise, the accuracy of the AC analysis result of the estimated power network model 100 will be greatly reduced. In addition, since the type and quantity of components included in each unit block depends on the design and layout of the integrated circuit, it is necessary to analyze the components in each unit block in detail before setting the screening step 80 or screening step 90. The type, quantity, data data during normal operation and data data during transient operation, etc., can accurately set the appropriate screening steps, so as to improve the execution speed of the AC analysis 50 while maintaining the consistency of the results of the AC analysis 50 high accuracy.

On the other hand, if it is desired to obtain high-accuracy AC analysis results of the power supply network model 100, the screening process 70 can be omitted, and the integrated circuit can be analyzed directly based on the component reference data containing each unit block, using circuit simulation and analysis software such as Hspice The power network model 100 is subjected to AC analysis 50 .

After the AC analysis 50 is performed on the power network model 100 of the integrated circuit, the AC analysis results of the power network model 100 can be obtained, and the designer can know from the AC analysis results that each unit block 110 in the power network model 100 is operated. The power consumed and the voltage drop caused can be optimized and adjusted accordingly for the integrated circuit design.

In addition, the voltage drop caused by the state switching of the components in the integrated circuit, especially the voltage drop caused by the state switching of high-frequency operation, will pollute the power supply and form power noise, which will interfere with signal processing. Therefore, based on the AC analysis results of the power network model 100, according to the design rules of the integrated circuit, the Loop-up Table and the data of the component database, the configuration of the decoupling capacitor 60 in the processing flow 10 of FIG. 1 is performed. A certain number of decoupling capacitors are arranged at appropriate positions in the design of integrated circuits to reduce voltage disturbances, compensate for voltage drops caused by components during state switching, and reduce noise generated when components change states, so as to maintain stable power supply standards. bit. For example, an appropriate decoupling capacitor 230 can be added and electrically connected to the unit block 110 in FIG. 3 to reduce voltage disturbance.

Moreover, after disposing decoupling capacitors at appropriate positions in the integrated circuit design, the AC analysis 50 of the integrated circuit design can be performed again by using circuit simulation and analysis software, so as to know that the power supply network model 100 of the integrated circuit design is equipped with decoupling capacitors Power consumption and distribution.

The advantage of the present invention is to provide a power supply noise analysis method and its reduction method, by defining the power supply network model of integrated circuit design as being composed of many unit blocks, and then according to the type of components electrically connected to each unit block , quantity, operating parameters, geometric parameters and other relevant data, use circuit simulation and analysis software to conduct AC analysis on the power network model of integrated circuit design, in order to obtain the power consumption and voltage drop caused by each unit block, and then it can be used in A certain number of decoupling capacitors are arranged at appropriate positions in the integrated circuit design to reduce the voltage drop and power noise caused by the state switching of components, and maintain a stable power level.

Claims (9)

1. the analytical method of a methd of power supply random signal is to be applied in the integrated circuit (IC) design, it is characterized in that the analytical method of this methd of power supply random signal comprises at least:

One electric power network model of this integrated circuit (IC) design is provided;

Define this electric power network model for to form according to a preordering method by a plurality of unit square;

Contain area according to each unit square in a position and of this electric power network model, acquisition is electrically connected to the plurality of data of a plurality of elements of each unit square, and with the reference of these data as each unit square;

This reference to each this unit square is carried out a Screening Treatment, participates in a screening data of each this unit square of a transactional analysis step with acquisition; Wherein this Screening Treatment will be rejected the little element of the influence of consumed power and the pressure drop that causes in each this unit square, participate in the data of this transactional analysis step of this electric power network model with minimizing, thereby reduce and carry out required time of this transactional analysis step and system resource; And

According to this reference of this unit square, carry out this transactional analysis step, to obtain a transactional analysis result of this electric power network model.

2. the analytical method of methd of power supply random signal as claimed in claim 1 is characterized in that, described transactional analysis result comprises power that each unit square is consumed and the voltage drop that causes at least when operation.

3. the analytical method of methd of power supply random signal as claimed in claim 1 is characterized in that, wherein more comprises this integrated circuit (IC) design is carried out an electric power network analytical procedure, so as to obtaining this electric power network model of this integrated circuit (IC) design.

4. the analytical method of methd of power supply random signal as claimed in claim 1 is characterized in that, described electric power network model includes a direct current electric power network model data and AC power network model data of this integrated circuit (IC) design.

5. the analytical method of methd of power supply random signal as claimed in claim 1, it is characterized in that, described preordering method is for being a plurality of rectangles by a plurality of metal wires that constitute this electric power network model with the unit square that defines this electric power network model, and wherein those rectangles are made of those metal wires.

6. the analytical method of methd of power supply random signal as claimed in claim 1 is characterized in that, wherein these a plurality of elements include a plurality of logic elements, a plurality of sequential buffer and a plurality of parasitic antenna at least.

7. the analytical method of methd of power supply random signal as claimed in claim 6 is characterized in that, wherein these a plurality of parasitic antennas comprise a plurality of parasitic decoupling capacitances at least.

8. the analytical method of methd of power supply random signal as claimed in claim 1, it is characterized in that, wherein behind the transactional analysis result who obtains this electric power network model, more comprise according to the transactional analysis result, in a plurality of decoupling capacitances of a plurality of position configuration of integrated circuit (IC) design.

9. the analytical method of methd of power supply random signal as claimed in claim 1 is characterized in that, described Screening Treatment is at least one screening conditions that type, quantity, operating parameters and the geometric parameter according to this element defines this Screening Treatment.

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