JP2002110798A - Semiconductor device and method for layout thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for a layout thereof, where a resistant value between a power line at a power potential connecting a function element with a capacitor and a ground line at a ground potential can be set as a desired value and a capacitor layout can be realized, without the need for investigating individually by the layout of a macro cell in the semiconductor. SOLUTION: The semiconductor device comprises a macro cell, including a function cell which is the function element with the capacitor and a macro cell including a function cell which is the function element without the capacitor. The function cell, which is the function element with the capacitor included in the macro cell, is defined as the driver cell of a minimum cell unit, comprises a function element 1 comprising an inverter, a function element 2 comprising a clocked inverter, a capacitor 3 or the like and is configured, by adding the capacitor between the power potential (VCCL) of the function elements 1, 2 in the function cell which is a minimum cell unit and the ground potential (VSSL).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of logic function circuit blocks are integrated, and more particularly, to electromagnetic interference (Electro-magnetic interference) generated by the semiconductor device around the semiconductor device.
MagneticInterference: EMI)
The present invention relates to a technology effective when applied to a layout method of a semiconductor device suitable as a noise suppression technology.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventors, a conventional semiconductor device is disclosed in Japanese Patent Laid-Open No. 10-135.
As described in Japanese Patent Publication No. 336, a main power supply line to which a power supply potential is supplied from outside the semiconductor chip, a local power supply line connected to a circuit constituting a macro cell, and one electrode connected to the local power supply line; There is a technology having a capacitor having the other electrode connected to a ground line to which a ground potential is supplied. Then, the capacity of the capacitor is set to a range in which the amount of electric charge consumed in one cycle of consuming the current by the macrocell can be accumulated, and the capacitance between the electrode pad of the main power supply line and the connection point of the capacitor of the local power supply line is set. The time constant between the resistance value and the capacitance of the capacitor is set so that the amount of charge discharged from the capacitor can be recovered during one cycle of the cycle. .

[0003]

The inventors of the present invention have studied the technique disclosed in Japanese Patent Laid-Open No. Hei 10-135336, and as a result, the following has been found. For example, the technique disclosed in the above publication has a configuration in which a capacitor is connected between a local power supply line connected to a circuit forming a macro cell and a ground line to which a ground potential is supplied. When focusing on elements, it is conceivable that a desired resistance value may not be realized depending on the position of the functional element in the macro cell even if a capacitor is connected in macro cell units.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which a resistance value of a power supply line connecting a functional element and a capacitor and a ground line of a ground potential can be set to desired values. is there.

In the method of arranging capacitors in a semiconductor device as described above, it is conceivable that it is necessary to individually examine the arrangement of capacitors according to the result of arranging macrocells in the semiconductor device.

Accordingly, another object of the present invention is to provide a layout method of a semiconductor device which can realize the arrangement of capacitors without individually considering the arrangement of macrocells inside the semiconductor device.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the present invention, in a semiconductor device having a plurality of circuit blocks each including a plurality of logic function elements, a power supply potential and a ground potential of one or a plurality of logic function elements are provided for each function cell constituting a macro cell of the semiconductor device. The capacitor is added to the logic function element so as to be adjacent to the logic function element. This is used as one logic function element with a capacitor, and the semiconductor device is configured using the capacitor. And the inductance between them is made small and always constant.

That is, the semiconductor device according to the present invention is applied to a semiconductor device having a plurality of circuit blocks each including a plurality of logic function elements. The circuit block includes one or a plurality of logic function elements and one or a plurality of the logic function elements. It has a logic function element with a capacitor comprising a capacitor connected between the power supply potential and the ground potential of the logic function element.

In this semiconductor device, the capacitor is
This is provided for each functional cell in the minimum cell unit of the logic functional element with a capacitor.

In addition, a layout method of a semiconductor device according to the present invention includes a method of controlling one or more logic function elements and a capacitor connected between a power supply potential and a ground potential of the one or more logic function elements. A function cell of a logic function element with a capacitor is created, and the function cell of the logic function element with a capacitor is arranged on a semiconductor substrate.

In the method of laying out a semiconductor device, a function cell of a non-capacitor logic function element comprising one or more logic function elements is further created, and a function cell of a logic function element with a capacitor and a function cell of a logic function element without a capacitor are formed. The power supply potential and the ground potential of the function cell are unified to the same width, and the function cell of the logic function element with the capacitor and the function cell of the logic function element without the capacitor are mixed and arranged on the semiconductor substrate. It was done.

Further, in this semiconductor device layout method, a macro cell having a plurality of function cells of a logic function element with a capacitor and a macro cell having a plurality of function cells of a logic function element without a capacitor are mixed and arranged on a semiconductor substrate. It is like that.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a functional cell of a functional element with a capacitor in a semiconductor device according to an embodiment of the present invention, FIG. 2 is a layout diagram showing a functional cell of a functional element with a capacitor, and FIG. FIG. 4 is a schematic layout diagram illustrating a macro cell including a functional cell, and FIG. 4 is a schematic layout diagram illustrating a semiconductor device in which a macro cell including a functional cell of a functional element with a capacitor is arranged.

First, referring to FIG. 1, the configuration of an example of a functional cell of a functional element with a capacitor in the semiconductor device of the present embodiment will be described. The functional cell of the functional element with a capacitor according to the present embodiment is, for example, a driver cell in a minimum cell unit, and includes a functional element 1 composed of an inverter, a functional element 2 composed of a clocked inverter, a capacitor 3, and the like. A capacitor 3 is added between the power supply potential and the ground potential of the functional elements 1 and 2 in the unit functional cell.

In the functional cell of the functional element with a capacitor, the power supply terminals 1a and 2a of the functional elements 1 and 2 comprising an inverter and a clocked inverter are connected to a power supply potential (VC).
CL), the ground terminals 1b, 2b are connected to the local ground line 5 of the ground potential (VSSL), respectively, and the power terminals 1a, 2a of the functional elements 1, 2 are connected to one capacitor plate of the capacitor 3. 3a, ground terminal 1
b and 2b are connected to the other capacitor plate 3b of the capacitor 3, respectively. Further, an input signal is input to the input terminal of the functional element 1, and the input signal and the output signal from the output terminal serve as a control signal for the functional element 2. Further, an input signal is input to the input terminal of the functional element 2 and output as an output signal from the output terminal.

Next, with reference to FIG. 2, an example of a layout of a functional cell of a functional element with a capacitor will be described. The capacitor 3 includes one capacitor plate 3a connected to the power supply terminals 1a and 2a of the functional elements 1 and 2 including the inverter and the clocked inverter in the functional cell, and the ground terminals 1b and 2
b and the other capacitor plate 3b connected thereto. In this example, the capacitor 3 is constituted by the capacitance between the two layers of polysilicon.
It is also possible to use a capacitance between gates. With such a circuit configuration and a layout structure, the power terminals 1a and 2a and the ground terminals 1b and 2b of the functional elements 1 and 2 are formed.
The impedance between the capacitor and the capacitor 3 is reduced.

The functional element 1 composed of an inverter has a CMOS structure of a PMOS transistor and an NMOS transistor constituting the inverter. The functional element 2 composed of a clocked inverter includes two PMOS transistors and two NMOS transistors forming the clocked inverter. Each transistor is composed of a diffusion layer connected to source and drain electrodes, and a gate layer connected to a gate electrode. Local power supply line 4 of power supply potential (VCCL) and local ground line 5 of ground potential (VSSL) are formed of conductive layers, and predetermined conductive layers, diffusion layers and gate layers are electrically connected through interlayer connection contacts. Have been.

Next, an example of a layout of a macro cell including a functional cell of a functional element with a capacitor will be described with reference to FIG. The macro cell is, for example, a plurality of (here, four examples) functional cells 6 of the above-described functional element with a capacitor.
And a plurality of (here, five examples) functional cells 7 of capacitorless functional elements, and a local power supply line 4 of a power supply potential (VCCL) and a ground potential (V
SSL) and a local ground line 5.

For example, a functional cell 6 of a functional element with a capacitor and a functional cell 7 of a functional element without a capacitor in the first stage
The upper side is connected to the local power supply line 4 and the lower side is connected to the local ground line 5, respectively. Conversely, the functional cell 6 of the functional element with a capacitor in the second stage and the functional cell 7 of the functional element without a capacitor have a local ground line 5 (shared with the first stage) on the upper side and a local power supply line 4 (third stage on the lower side). And shared). Hereinafter, they are alternately arranged between the local power supply line 4 and the local ground line 5. The width between the local power supply line 4 and the local ground line 5 is unified to the same width. As a result, the functional cell 6 of the functional element with a capacitor and the functional cell 7 of the functional element without a capacitor are also formed in the same width, and the functional cell 6 of the functional element with a capacitor is formed.
And the function cell 7 of the capacitor-less function element can be mixed.

Next, an example of a layout of a semiconductor device in which macro cells including functional cells of functional elements with capacitors are arranged will be described with reference to FIG. The semiconductor device includes, for example, a 1-cell including a functional cell 6 of a functional element with a capacitor as described above.
One or more (here three examples) macrocells 8;
It consists of zero or one or a plurality (here, one example) of macro cells 9 which do not include a function cell of a functional element with a capacitor, and a local power supply line 4 of a power supply potential (VCCL) and ground around these macro cells 8, 9 Potential (VSS
L), a peripheral wiring of a local ground line 5, a main power supply line 10 of a power supply potential (VCC), and a main ground line 11 of a ground potential (VSS) are arranged, and further, external connection pads 12 are arranged on the outer periphery. Have been. The metal wirings of the local power supply line 4 and the local grounding line 5 are replaced with main power supply lines 10 and main grounding lines 11 of different metal wiring layers.
It is connected to the.

In the layout of this semiconductor device,
First, a functional cell 6 of a functional element with a capacitor comprising one or more functional elements 1 and 2 and a capacitor 3 connected between the power supply potential and the ground potential of the one or more functional elements 1 and 2 Create In addition, a function cell 7 of a capacitor-free function element including one or a plurality of function elements 1 and 2 is created. At this time, the functional cell 6 of the functional element with a capacitor and the functional cell 7 of the functional element without a capacitor are used.
And the same width between the power supply potential and the ground potential.

Further, a macro cell 8 having a plurality of functional cells 6 of a functional element with a capacitor and a macro cell 9 having a plurality of functional cells 7 of a functional element without a capacitor are prepared. Then, a macro cell 8 having a plurality of functional cells 6 of a functional element with a capacitor and a macro cell 9 having a plurality of functional cells 7 of a functional element without a capacitor are arranged on a semiconductor substrate in a mixed manner. Thereby, the layout design of the semiconductor device in which the macro cells 8 including the functional cells 6 of the functional elements with capacitors are arranged is completed.

Therefore, according to the semiconductor device of the present embodiment, the capacitor 3 is added between the power supply potential and the ground potential of the functional elements 1 and 2 for each of the functional cells in the smallest cell unit. Functional elements 1 and 2 by charging and discharging of electric charge
Since a current loop is formed by the power supply potential, the ground potential, and the capacitor 3, transient changes in the power supply voltage at the power supply terminal and the ground terminal of the semiconductor device are reduced.

At this time, the capacitor 3 is connected to the functional elements 1 and 2
, The capacitor 3, the functional elements 1, 2
The effects of the resistance component and the inductance parasitically present on the power supply line and the ground line between them are always constant. Therefore, the power supply potential, the ground potential, and the current loop of the capacitor 3 are reduced, and the effect of reducing the transient power supply voltage change of the power supply terminal and the ground terminal of the semiconductor device is improved.
Noise can be reduced.

That is, since the parasitic resistance component between the functional elements 1 and 2 and the power supply potential and the ground potential is always small and constant, the effect of the bypass capacitor by the added capacitor 3 is large and uniform. EM
Does not emit I noise.

Further, since the capacitor 3 is always adjacent to the functional elements 1 and 2 for each functional cell in the minimum cell unit, it is not necessary to individually consider the positions of the capacitors when arranging the functional cells and the macro cells.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, the functional cell of the functional element with the capacitor including the functional element of the inverter and the clocked inverter and the capacitor has been described as an example. The present invention can be widely applied to all functional cells in a minimum cell unit of a functional element with a capacitor in which a capacitor is added to one or a plurality of functional elements such as an element.

Further, the example in which one capacitor is provided for each functional cell of the functional element with a capacitor has been described. However, the present invention is also applicable to a case where a plurality of capacitors are provided for each minimum cell, such as two for each functional cell. is there. In particular, the functional cell of the functional element with a capacitor is effective for a functional cell that generates a large amount of noise, such as a driver cell.

Although the layout design of the semiconductor device in which the macro cell including the functional cell of the functional element with the capacitor is arranged has been described, the present invention is also applied to the case where the functional cell of the functional element with the capacitor is simply arranged on the semiconductor substrate. It goes without saying that it is possible.

[0033]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By having a logic function element with a capacitor in which a capacitor is connected between the power supply potential and the ground potential of the logic function element, the power supply line between the capacitor and the logic function element and the ground line are parasitically connected. Since the effects of the existing resistance component and inductance are always constant, EMI noise can be reduced by improving the effect of reducing transient power supply voltage changes at the power supply terminal and the ground terminal of the semiconductor device.

(2) Since a capacitor is always adjacent to a logic function element by adding a capacitor next to the logic function element to form a functional cell in a minimum cell unit, the layout position is individually considered in the layout design. It is possible to arrange the capacitors without having to do so.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a functional cell of a functional element with a capacitor.

FIG. 2 shows a semiconductor device according to an embodiment of the present invention;
FIG. 4 is a layout diagram showing a functional cell of a functional element with a capacitor.

FIG. 3 illustrates a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic layout diagram showing a macro cell including a functional cell of a functional element with a capacitor.

FIG. 4 illustrates a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a schematic layout diagram showing a semiconductor device in which macro cells including functional cells of functional elements with capacitors are arranged.

[Explanation of symbols]

Reference Signs List 1 functional element (inverter) 2 functional element (clocked inverter) 1a, 2a power supply terminal 1b, 2b ground terminal 3 capacitor 3a, 3b capacitor plate 4 local power supply line 5 local ground line 6 function cell (functional element with capacitor) 7 function Cell (functional element without capacitor) 8 Macro cell (including functional cell of functional element with capacitor) 9 Macro cell (not including functional cell of functional element with capacitor) 10 Main power supply line 11 Main ground line 12 Pad for external connection

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 H (72) Inventor Masaru Iwabuchi 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Stock 5B046 AA08 BA05 5F038 AC04 AC05 AC17 BH02 BH03 BH13 CA02 CA03 CA07 CA17 CD02 CD12 CD13 DF14 EZ09 EZ20 5F064 AA04 CC12 CC23 DD02 DD03 DD05 DD07 DD13 DD14 EE44 EE52 HHH

Claims (5)

[Claims] 1. A semiconductor device having a plurality of circuit blocks each including a plurality of logic function elements, wherein the circuit block includes one or a plurality of logic function elements and a power supply potential of the one or a plurality of logic function elements. A logic function element with a capacitor comprising a capacitor connected between the capacitor and a ground potential. 2. The semiconductor device according to claim 1, wherein the capacitor is provided for each functional cell of a minimum cell unit of the logic function element with a capacitor. 3. A function cell of a logic function element with a capacitor comprising one or more logic function elements and a capacitor connected between a power supply potential and a ground potential of the one or more logic function elements. And arranging a functional cell of the logic function element with a capacitor on a semiconductor substrate. 4. The method for laying out a semiconductor device according to claim 3, wherein a function cell of a logic function element without a capacitor comprising one or a plurality of logic function elements is created, and the function cell of the logic function element with a capacitor is formed. And the same width between the power supply potential and the ground potential of the function cell of the logic function element without a capacitor, and the function cell of the logic function element with a capacitor and the function cell of the logic function element without a capacitor. A layout method of a semiconductor device, wherein the semiconductor device is arranged on a semiconductor substrate in a mixed manner. 5. The layout method for a semiconductor device according to claim 4, wherein a macro cell having a plurality of function cells of the logic function element with a capacitor and a macro cell having a plurality of function cells of the logic function element without a capacitor are mixed. And arranging it on a semiconductor substrate.