JP2003203984A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be made smaller in circuit area than normally and improved in degree of integration. <P>SOLUTION: An electrostatic discharge protection circuit is formed of a p-type MOS transistor Qp, an n-type MOS transistor Qn, and a protection resistance R. When electrostatic discharge is produced, the p-type MOS transistor Qp or n-type MOS transistor Qn is turned on and a surge current flows to a power source Vdd or reference potential Vss to limit voltage variation of a pad 1, so that an internal circuit 2 is prevented from being broken owing to the electrostatic discharge. A portion (n-type MOS transistor Qn) of an electrostatic protection circuit is formed below an electrode 41 forming the pad 1, so that the circuit area can be made smaller than normal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an electrostatic discharge protection circuit for preventing an internal circuit from being destroyed by electrostatic discharge, and a semiconductor device having a plurality of different power supply systems. .

[0002]

2. Description of the Related Art FIG. 5 is a schematic block diagram showing an example of a conventional semiconductor device having an electrostatic discharge protection circuit. 5, reference numeral 1 indicates a pad, reference numeral Qn indicates an n-type MOS transistor, reference numeral Qp indicates a p-type MOS transistor, reference numeral R indicates a protection resistor, and reference numeral 2 indicates an internal circuit.

The signal wiring of the internal circuit 2 is connected to the pad 1 via the protection resistor R. By electrically connecting the pad 1 to the pin exposed outside the package,
The signal wiring of the internal circuit 2 is drawn out of the device. The connection line between the pad 1 and the protection resistor R is connected to the reference potential Vss via the drain-source terminal of the n-type MOS transistor Qn, and is connected to the power supply Vdd via the drain-source terminal of the p-type MOS transistor Qp. Connected.

According to the semiconductor device shown in FIG. 5, the potential of the pad 1 is changed from the power source Vdd to the p-type MOS by electrostatic discharge.
When the threshold voltage of the transistor Qp increases, the p-type MOS transistor Qp becomes conductive, so that the potential increase of the pad 1 is suppressed. Further, when the potential of the pad 1 becomes lower than the reference potential Vss by the threshold voltage of the n-type MOS transistor Qn due to electrostatic discharge, this n
Since the type MOS transistor Qn becomes conductive, the potential drop of the pad 1 is suppressed. Pad 1 in this way
Since the voltage fluctuation range is limited, the internal circuit 2 is prevented from being damaged by electrostatic discharge.

FIG. 6 is a diagram showing an example of a conventional layout of the semiconductor device shown in FIG. In FIG. 6, reference numeral 1
Reference numeral 1 is a semiconductor substrate, reference numeral 12 is a p-type impurity region, reference numeral 13 is an n-type impurity region, reference numeral 14 is an n-type or p-type impurity region, reference numeral 15 is a polycrystalline silicon film, reference numeral 2
Reference numeral 1 is a second layer wiring, reference numeral 31 is a third layer wiring, reference numeral 41.
Indicate the fourth layer wirings, respectively. Further, FIG. 7 is a cross-sectional view of the cross section of the semiconductor device taken along the dotted line AA ′ in FIG. 6 viewed from the direction of arrow a. The same reference numerals in FIGS. 7 and 6 indicate the same components. 7, reference numeral 16 indicates a gate electrode, reference numeral 17 indicates an n-type impurity region, reference numeral 18 indicates a p-type impurity region, reference numeral 50 indicates an interlayer insulating film, and reference numeral 60 indicates a via.

As shown in FIGS. 6 and 7, the pad 1 is provided in the area A1 and the n-type MOS transistor Q is provided in the area A2.
n, a p-type MOS transistor Qp is formed in the region A3, a resistor R is formed in the region A4, and an internal circuit 2 is formed in the region A5.

In the area A1, the second wiring layer and the fourth wiring layer are formed.
A rectangular electrode 41 is formed on the wiring layer, and the area A
3 and the third layer wiring 31 extending from the region A2 and these electrodes 41 are connected by the via 60.

In the area A2, a fourth layer wiring 42, which is a wiring of the reference potential Vss, is formed extending in a direction perpendicular to the third layer wiring 31. On the semiconductor substrate 11 facing the fourth layer wiring 42, the p-type impurity region 12 extending in the same direction as the fourth layer wiring 42 is formed.

A gate electrode 16 is formed on the p-type impurity region 12 via a gate insulating film, and an n-type MOS is sandwiched by a channel forming region facing the gate electrode 16.
An n-type impurity region 17 to be the source or drain of the transistor Qn is formed. The n-type impurity region 17 serving as a source is connected to the second layer wiring 21 via the via 60, and the second layer wiring 21 is further connected to the third layer wiring 31 via the via 60. The n-type impurity region 17 to be the drain and the gate electrode 16 are connected to the same second layer wiring 21 via the via 60, and the second layer wiring 21 is further connected.
Is connected to the fourth layer wiring 42, which is the wiring of the reference potential Vss, via the third layer wiring (not shown) and the via 60. In the example of FIG. 7, the p-type impurity region 18 formed in the p-type impurity region 12 and the second common gate electrode 16
It is connected to the layer wiring 21. As a result, the potential of the p-type impurity region 12 is fixed to the reference potential Vss.

In the area A3, a fourth layer wiring 43, which is a wiring for the power supply Vdd, is formed extending in a direction parallel to the fourth layer wiring 42. On the semiconductor substrate 11 facing the fourth layer wiring 43, the n-type impurity region 13 extending in the same direction as the fourth layer wiring 43 is formed.

A gate electrode 16 is formed on the n-type impurity region 13 via a gate insulating film, and a p-type MOS is sandwiched by a channel forming region facing the gate electrode 16.
A p-type impurity region 18 serving as the source or drain of the transistor Qp is formed. The p-type impurity region 18 serving as the source is connected to the second layer wiring 21 via the via 60, and the second layer wiring 21 is further connected to the third layer wiring 31 via the via 60.

The p-type impurity region 18 serving as a drain and the gate electrode 16 are connected to the same second layer wiring 21 via a via 60, and the second layer wiring 21 further includes a third layer wiring and a via (not shown). Via 60, it is connected to the fourth layer wiring 43 which is the wiring of the power supply Vdd. In the example of FIG. 7, the n-type impurity region 1 formed in the n-type impurity region 13 is
7 and the gate electrode 16 are connected to a common second layer wiring 21. As a result, the potential of the n-type impurity region 13 becomes V
It is fixed at dd.

In the region A4, one end of the resistor R formed of the polycrystalline silicon film 15 formed on the semiconductor substrate 11 and the third layer wiring 31 are connected via the via 60 and the second layer wiring 21. The other end of the polycrystalline silicon film 15 is
It is connected to a wiring extending from the internal circuit 2 in the area A5.

Next, a conventional semiconductor device having a plurality of different power supply systems will be described. FIG. 8 is a diagram showing an example of a layout near a pad in a conventional semiconductor device having two power supply systems. The same reference numerals in FIGS. 8 and 5 indicate the same components. In addition, in FIG. 8, reference numeral 24 is the second layer wiring of the reference potential Vss1, reference numeral 26 is the second layer wiring of the reference potential Vss2, and reference numeral 27 is the power supply Vd.
The second layer wirings of d2 are respectively shown, and these wirings are directly connected to the internal circuit. Reference numeral 44 is the reference potential Vs.
s1 is the fourth layer wiring, reference numeral 45 is the fourth layer wiring of the power source Vdd1, reference numeral 46 is the fourth layer wiring of the reference potential Vss2,
Reference numeral 47 represents the fourth layer wiring of the power supply Vdd2,
Pads are formed by these wirings.

In the layout example of FIG. 8, power supply Vdd1 system pads are formed in the regions A6 and A10, and power supply Vdd2 system pads are formed in the region A8 between the regions A6 and A10.

Further, the reference potential Vss1 in the area A6
And the pad of the reference potential Vss2 in the area A8 are adjacent to each other across the area A7, and the two pads are connected to each other by a bidirectional parallel diode formed in the area A7.

Similarly, the reference potential Vs in the area A10 is
The pad of s1 and the pad of the power supply Vdd2 in the area A8 are adjacent to each other across the area A9, and the two pads are connected to each other by the diode formed in the area A9. In the example of FIG. 8, the reference potential Vss1 is connected to the anode side of the diode and the power supply Vdd2 is connected to the cathode side.

FIG. 9 is a sectional view of the semiconductor device taken along the dotted line BB 'in FIG. The same reference numerals in FIG. 9 and FIGS. 7 and 8 indicate the same components. In addition, in FIG.
Reference numeral 34 indicates a third layer wiring of the reference potential Vss1, and reference numeral 36.
Is the third layer wiring of the reference potential Vss2, and 37 is the power source V
The third layer wiring of dd2 is shown.

As shown in FIG. 9, the electrodes of the respective pads formed on the fourth wiring layer have the second electrodes connected to the internal circuit.
It is connected to the layer wiring or the third layer wiring via the via 60. Further, between pads of different power supply systems, a region A7 or a region A where a diode connecting these pads is formed.
Therefore, there is an empty area in which no circuit is formed.

In general, a sensitive signal processing circuit whose operation is defective due to the mixing of noise generated in a main logic circuit or the like which operates with a high-speed clock signal has a common power supply supplied to the main circuit of the noise source. May use different independent power supplies. In this case, such a small independent power supply system has a smaller capacitance component between the power supply and the reference potential than a large-scale common power supply system, and the number of electrostatic discharge protection circuits is smaller than that of the common power supply system. When the voltage occurs, the voltage of the circuit tends to be higher than that of the common power supply system. That is, the small independent power supply circuit is
Compared to a large-scale common power supply system circuit, it has low electrostatic resistance and is easily destroyed.

In order to solve such a problem, for example, as in the semiconductor device shown in FIGS. 8 and 9, bidirectional parallel diodes are inserted between reference potentials or power supply potentials of different power supply systems, or A diode may be inserted between the reference potential of one power supply system and the power supply potential of the other power supply system.

If the voltage of the noise component is smaller than the forward voltage of this diode, the diode has a high impedance with respect to the noise component, so that noise mixing between different power supply systems is prevented.

On the other hand, when electrostatic discharge occurs, the diode becomes conductive due to the large voltage, so that the reference potential or the power supply potential connected by the bidirectional parallel diode is electrically connected to each other. As a result, since the electrostatic discharge protection circuits of both power supply systems are shared, the electrostatic withstand capability of the independent power supply system and the common power supply system can be made approximately the same. Also, due to the diode connected between the reference potential of one power supply system and the power supply potential of the other power supply system, part of the surge current of electrostatic discharge that flows from the pad of the independent power supply system also flows to the common power supply system. It is possible to suppress the voltage rise of the circuit of the independent power supply system.

[0024]

By the way, in each of the above-mentioned conventional semiconductor devices, an electrostatic discharge protection circuit or a diode is added as a countermeasure against electrostatic discharge, so that the area for forming these additional circuits is large. There is a problem in that the circuit area is enlarged because it is required in an extra amount.

For example, in the conventional layout example shown in FIG. 6, since one pad needs an area for two transistors, it is assumed that these pads are formed on each side of the semiconductor chip. , An area for four transistors is required in each of the vertical direction and the horizontal direction.

Further, as can be seen from the sectional view of FIG. 9, in the conventional layout example shown in FIG. 8, circuits such as the regions A7 and A9 are provided in order to provide regions for diodes to be inserted between different power supply systems. A useless area where no gap is formed is created between the pads. The number of input / output pins tends to increase year by year as the functionality of ICs increases, and the presence of such a wasteful region between pads increases the circuit area and limits the number of pins. There's a problem.

The present invention has been made in view of the above circumstances, and a first object thereof is to provide a semiconductor device capable of reducing the area of a circuit as compared with the conventional one. The second purpose is to reduce a wasteful area where a circuit is not formed,
An object of the present invention is to provide a semiconductor device capable of improving the degree of integration of circuits.

[0028]

In order to achieve the above-mentioned object, a semiconductor device according to a first aspect of the present invention has a pad for drawing out wiring to the outside of the device and at least a part of the surface of the pad. And an electrostatic discharge protection circuit which is formed on the semiconductor substrate and suppresses the voltage rise of the pad caused by electrostatic discharge.

According to the semiconductor device of the first aspect of the present invention, the electrostatic discharge for suppressing the voltage rise of the pad caused by the electrostatic discharge is provided on the semiconductor substrate facing the pad for drawing out the wiring to the outside of the device. At least a part of the protection circuit is formed. As a result, the area of the semiconductor substrate facing the pad is effectively used, and the circuit area is reduced.

The electrostatic discharge protection circuit is connected between the pad and the power supply line, and has a first transistor which becomes conductive according to the voltage between the pad and the power supply line, the pad and the reference. It may include a second transistor connected between the potential line and the second transistor which is brought into a conductive state according to a voltage between the pad and the reference potential line. Further, the electrostatic discharge protection circuit may include a protection resistor inserted in series on the wiring connected to the pad.

A semiconductor device according to a second aspect of the present invention is
A first pad for drawing out the first power supply line or a reference potential line corresponding to the first power supply line to the outside of the device, and a second power supply line or a reference potential line corresponding to the second power supply line. A second pad for drawing to the outside of the device, and at least a part of the second pad formed on the semiconductor substrate facing the first pad or the second pad, the first pad and the second pad And at least one diode connected between and.

According to the semiconductor device of the second aspect of the present invention, the first pad and the second pad are provided on the semiconductor substrate facing the first pad or the second pad. At least one diode is formed that connects. When the noise is lower than the threshold voltage of the diode, the diode is in a high impedance state,
The noise propagation between the second power supply system and the second power supply system is suppressed. When a large voltage is generated due to electrostatic discharge, the diode becomes conductive, and a surge current flowing into one power supply system also flows into the other power supply system, suppressing an increase in circuit voltage due to the surge current. Further, since it is not necessary to provide a region for forming the diode between the first pad and the second pad, a useless region where a circuit is not formed between the pads is reduced.

The diode is a parallel diode in which a plurality of diodes are connected in parallel in mutually opposite directions,
The first pad connected to the first power supply line;
A parallel diode connecting the second pad connected to the second power supply line, or the first pad connected to the reference potential line corresponding to the first power supply line and the second power supply line. You may have at least one of the parallel diode which connects with the said 2nd pad connected to a corresponding reference electric potential line. Further, the diode is connected to the first power supply line and connected to the first power supply line.
Connecting the second pad to the reference potential line corresponding to the second power supply line, or the first pad connecting to the reference potential line corresponding to the first power supply line. And a diode connecting the second pad connected to the second power supply line.

[0034]

DETAILED DESCRIPTION OF THE INVENTION Two embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a schematic diagram showing an example of a circuit configuration and a layout of a semiconductor device according to a first embodiment of the present invention. The same reference numerals in FIG. 1 and FIG. 6 indicate the same components. 2 is a cross-sectional view of the cross section of the semiconductor device taken along the dotted line CC ′ of FIG. 1 as seen from the direction of arrow c. 2 and FIG. 7 indicate the same components.

As shown in FIGS. 1 and 2, the area A11
Pad 1 and an n-type MOS transistor Qn in the area A1, a p-type MOS transistor Qp in the area A12, and an area A1.
A resistor R is formed in 3 and an internal circuit 2 is formed in the area A14.

In the area A11, a pad is formed on the fourth wiring layer by the rectangular electrode 41, and the pad is formed in the area A11.
The third layer wiring 31 extending from 12 and this electrode 41 are connected via the via 60.

Also, facing the electrode 41 forming the pad,
An n-type MO is formed on the semiconductor substrate 11 adjacent to the region A12.
P-type impurity region 12 of S transistor Qn is formed. A gate electrode 16 is formed on the p-type impurity region 12 via a gate insulating film.
An n-type impurity region 17 serving as a source or a drain of the n-type MOS transistor Qn is formed sandwiching the channel formation region facing the.

The n-type impurity region 17 serving as the source of the n-type MOS transistor Qn is connected via the via 60 to the second layer wiring 23 formed facing the electrode 41 forming the pad. Further, the second-layer wiring 23 includes a third-layer wiring 31 extending below the electrode 41 forming a pad and a via 6
Connected via 0.

The n-type impurity region 17 serving as the drain of the n-type MOS transistor Qn and the gate electrode 16 face the electrode 41 forming the pad, and the second-layer wiring 22 formed adjacent to the second-layer wiring 23. Are connected via the beer 60. Further, the second layer wiring 22 is connected to the fourth layer wiring 42 which is the wiring of the reference potential Vss via the third layer wiring (not shown) and the via 60. The fourth layer wiring 42 is
It is formed adjacent to the electrode 41 forming the pad and extending in the direction perpendicular to the third layer wiring 31.

In the example of FIG. 2, the p-type impurity region 18 formed in the p-type impurity region 12 and the gate electrode 16 are connected to the common second layer wiring 22. As a result, the potential of the p-type impurity region 12 is fixed to the reference potential Vss.

In the region A12, the p-type impurity region 12
P-type MOS transistor Q on the semiconductor substrate adjacent to
A p-type n-type impurity region 13 is formed. A gate electrode 16 is formed on the n-type impurity region 13 via a gate insulating film, and a p-type MOS transistor Qp serving as a source or a drain is sandwiched with a channel forming region facing the gate electrode 16 interposed therebetween. The type impurity region 18 is formed.

The p-type impurity region 18 serving as the source of the p-type MOS transistor Qp is connected to the second layer wiring 21 through the via 60, and the second layer wiring 21 is further connected through the via 60 to the third layer wiring. 31 is connected.

The p-type impurity region 18 serving as the drain of the p-type MOS transistor Qp and the gate electrode 16 are connected to the same second layer wiring 21 via the via 60, and the second layer wiring 21 is not shown. The fourth layer wiring 43, which is the wiring for the power supply Vdd, is provided via the third layer wiring and the via 60.
Connected to. The fourth-layer wiring 43 is formed adjacent to the fourth-layer wiring 42 and extends in the same direction as the fourth-layer wiring 42.

In the example of FIG. 7, the n-type impurity region 17 formed in the n-type impurity region 13 and the gate electrode 16 are connected to the common second layer wiring 21. As a result, the potential of the n-type impurity region 13 is fixed to the power supply Vdd.

In the region A13, one end of the resistor R formed of the polycrystalline silicon film 15 formed on the semiconductor substrate 11 and the third layer wiring 31 are connected via the via 60 and the second layer wiring 21. The other end of polycrystalline silicon film 15 is connected to a wiring extending from internal circuit 2 in region A14.

According to the semiconductor device of FIG. 1 described above, even if the potential of the pad 1 changes due to electrostatic discharge, the p-type MO
S transistor Qp or n-type MOS transistor Qn
Becomes conductive, a surge current flows to the power supply Vdd or the reference potential Vss, and the voltage fluctuation range of the pad 1 is limited, so that the internal circuit 2 is prevented from being damaged by electrostatic discharge.

Further, as can be seen by comparing with the conventional layout examples shown in FIGS. 6 and 7, the n-type M in the conventional example is used.
The area A2 in which the OS transistor Qn is formed and the area A1 in which the pad is formed are shown in FIGS.
In the layout example of, the area A11 is collected. Therefore, according to the layout example described above, the area corresponding to about one transistor can be reduced as compared with the conventional example.

When the area of the pad compared to the area of the transistor is larger than the layout examples of FIGS. 1 and 2, a p-type MOS transistor Qp is formed in the lower layer of the pad in addition to the n-type MOS transistor Qn. can do. If there is more space, the protection resistor R can be formed in the lower layer of the pad. As described above, the circuit area can be reduced by forming the electrostatic discharge protection circuit in the region of the pad lower layer which has not been conventionally used.

Further, since the electrostatic discharge protection circuit is formed closer to the pad than in the conventional case, the surge current can be more effectively passed to the electrostatic discharge protection circuit and the resistance to electrostatic discharge can be improved. .

<Second Embodiment> Next, a second embodiment of the present invention will be described. FIG. 3 is a schematic view showing an example of the layout of a semiconductor device according to the second embodiment of the present invention. The same reference numerals in FIG. 3, FIG. 8 and FIG. 9 indicate the same components.

A power source V is provided in the areas A15 and A19.
A rectangular electrode 41 is formed in the fourth wiring layer as a dd1-based signal pad, and a third-layer wiring 31 that connects the electrode 41 and the internal circuit is formed. Further, a polycrystalline silicon film 15 is formed on the semiconductor substrate 11 as a protective resistance that is inserted in series on the connection line between the signal pad and the internal circuit. On the upper layer of the third layer wiring 31, the fourth layer wiring 45 connected to the power supply Vdd1 and the reference potential Vs of the power supply Vdd1 system.
The fourth layer wiring 44 connected to s1 is formed so as to extend in the vertical direction with respect to the third layer wiring 31.

Similarly, in the area A17, a rectangular electrode 41 is formed in the fourth wiring layer as a signal pad for the power supply Vdd2 system, and a third layer wiring 31 connecting the electrode 41 and the internal circuit is formed. . Further, a polycrystalline silicon film 15 is formed on the semiconductor substrate 11 as a protective resistance that is inserted in series on the connection line between the signal pad and the internal circuit. A fourth layer connected to the power supply Vdd2 is formed on the third layer wiring 31.
The layer wiring 47 and the fourth layer wiring 46 connected to the reference potential Vss2 of the power supply Vdd2 system are formed so as to extend in the vertical direction with respect to the third layer wiring 31.

In the lower layer of the third layer wiring 31 connecting the electrode 41 and the polycrystalline silicon film 15, for example, n in FIG.
Type MOS transistor and p type MOS transistor Q
A circuit for protecting the internal circuit from electrostatic discharge may be formed like p. Further, as shown in the example of FIG. 2, at least a part of this electrostatic discharge protection circuit may be formed in the lower layer of the electrode 41.

In the area A16 sandwiched between the area A15 and the area A17, the reference potential Vss1 is adjacent to the area A15.
Power pad is formed on the fourth-layer wiring 44, and the area A1
7, a power supply pad having the reference potential Vss2 is formed on the fourth-layer wiring 46 adjacent to 7. In the example of FIG. 3, the distance between these two pads is approximately the same as the distance between the pads in the same power supply system. In the example of FIG. 3, the reference potential Vss1
The fourth layer wiring 44 on which the power supply pad is formed is connected to the internal circuit through the second layer wiring 24. Reference potential Vss
The fourth layer wiring 46 on which the second power supply pad is formed is connected to the internal circuit via the third layer wiring 36.

Further, parallel diodes, which are connected in parallel in opposite directions to each other, are formed below the two pads in the region A16. Through this parallel diode, the reference potential Vs
The pad of s1 and the pad of reference potential Vss2 are connected to each other.

Area A sandwiched between areas A17 and A19
18, a power supply pad for the power supply Vdd2 is formed on the fourth layer wiring 47 adjacent to the region A17, and a power supply pad for the reference potential Vss1 is formed on the fourth layer wiring 4 adjacent to the region A19.
4 is formed. In the example of FIG. 3, the distance between the two pads is also the same as the distance between the pads in the same power supply system. In the example of FIG. 3, the fourth-layer wiring 47 on which the power supply pad for the power supply Vdd2 is formed is connected to the internal circuit via the third-layer wiring 37. The fourth layer wiring 44 on which the power supply pad of the reference potential Vss1 is formed is connected to the internal circuit via the second layer wiring 24.

In the lower layer of the two pads in the area A18, a diode for connecting the two pads is formed in the forward direction from the reference potential Vss1 to the power supply Vdd2.

FIG. 4 is a cross-sectional view of the cross section of the semiconductor device taken along the dotted line DD ′ in FIG. 3 as seen from the direction of arrow d, and the same reference numerals in FIG. 4 and FIGS. 7 to 9 denote the same constituent elements. Show. In the area A15, the area A17, and the area A19, the third layer wiring 31 and the second layer wiring 21 are formed in the lower layer of the electrode 41 forming the signal pad, and they are connected via the via 60. In the example of FIG. 4, this second
The layer wiring 31 is connected to the internal circuit.

In the region A16, the semiconductor substrate 11 facing the electrode 44 forming the power supply pad of the reference potential Vss1.
N-type impurity regions 13 are formed on the semiconductor substrate 11 facing the electrode 46 forming the power supply pad of the reference potential Vss2.

In the area A16, the electrode 44 is connected to the third layer wiring 34 via the via 60 and further connected to the second layer wiring 24 via the via 60. The second layer wiring 24 is a part of the upper layer region facing the two n-type impurity regions 13 and is formed in a region on the internal circuit side.
Then, in the p-type impurity region 18 formed on the n-type impurity region 13 facing the electrode 44 and the n-type impurity region 17 formed on the n-type impurity region 13 facing the electrode 46,
Each is connected via a beer 60. In the examples of FIGS. 3 and 4, the second layer wiring 24 is formed so as to extend in the internal circuit direction, whereby the power supply pad of the reference potential Vss1 and the internal circuit are connected.

In the region 16, the electrode 46 is connected to the third layer wiring 36 via the via 60, and the via 6 is further connected.
It is connected to the second layer wiring 26 via 0. The second layer wiring 26 is a part of the upper layer region facing the two n-type impurity regions 13, and is formed adjacent to the second layer wiring 24 in the region on the outer peripheral side of the semiconductor chip. And
N formed on the n-type impurity region 13 facing the electrode 44
The type impurity region 17 and the p-type impurity region 18 formed on the n-type impurity region 13 facing the electrode 46 are connected via vias 60, respectively. In the examples of FIGS. 3 and 4, the third layer wiring 36 is formed so as to extend in the internal circuit direction, whereby the power supply pad of the reference potential Vss2 is connected to the internal circuit.

In the region A18, the semiconductor substrate 11 facing the electrode 44 forming the power supply pad of the reference potential Vss1.
The electrode 4 forming the power pad of the power source Vdd2
N type impurity regions 13 are formed on the semiconductor substrate 11 facing the semiconductor substrate 7.

In the area A18, the electrode 44 is connected to the third layer wiring 34 via the via 60 and further connected to the second layer wiring 24 via the via 60. The second layer wiring 24 is a part of the upper layer region facing the two n-type impurity regions 13 and is formed in a region on the internal circuit side.
Then, in the p-type impurity region 18 formed on the n-type impurity region 13 facing the electrode 44 and the p-type impurity region 18 formed on the n-type impurity region 13 facing the electrode 47,
Each is connected via a beer 60. In the examples of FIGS. 3 and 4, the second layer wiring 24 is formed so as to extend in the internal circuit direction, whereby the power supply pad of the reference potential Vss1 and the internal circuit are connected.

In the region 18, the electrode 47 is connected to the third layer wiring 37 via the via 60, and the via 6 is further provided.
It is connected to the second layer wiring 27 through 0. The second layer wiring 27 is a part of the upper layer region facing the two n-type impurity regions 13, and is formed adjacent to the second layer wiring 24 in the region on the outer peripheral side of the semiconductor chip. And
N formed on the n-type impurity region 13 facing the electrode 44
The type impurity region 17 and the n-type impurity region 17 formed on the n-type impurity region 13 facing the electrode 47 are connected via vias 60, respectively. In the examples of FIGS. 3 and 4, the third layer wiring 37 is formed so as to extend in the internal circuit direction, whereby the power supply pad of the power supply Vdd2 and the internal circuit are connected.

According to the semiconductor device shown in FIGS. 3 and 4, the n formed in the region A16 facing the electrode 44 is n.
A pn junction diode having an anode connected to the electrode 44 and a cathode connected to the electrode 46 is formed on the type impurity region 13. A pn junction diode in which the anode is connected to the electrode 46 and the cathode is connected to the electrode 44 is formed on the n-type impurity region 13 formed facing the electrode 46 in the region A16. That is, parallel diodes connected in parallel in opposite directions are formed, and thereby the power supply pads having the reference potential Vss1 and the reference potential Vss2 are connected.

On the n-type impurity region 13 formed facing the electrode 44 in the region A18, the anode is the electrode 4
4. A pn junction diode whose cathode is connected to the electrode 47 is formed. Also on the n-type impurity region 13 formed facing the electrode 47 in the region A18, the anode is the electrode 44,
A pn junction diode is formed with the cathode connected to the electrode 47. That is, the parallel diodes connected in parallel in the same direction are formed, and as a result, the power source Vdd2
Is connected to the power supply pad of the reference potential Vss1.

If the voltage of the noise component generated in the power supply Vdd1 system is smaller than the forward voltage of this diode, the diode has a high impedance with respect to the noise component, so that noise is mixed from the power supply Vdd1 system to the power supply Vdd2 system. Is prevented.

When electrostatic discharge occurs on the power supply pad of the power supply Vdd2 system, the area A is caused by the large voltage.
The 16 bidirectional parallel diodes become conductive, and the reference potential Vss1 and the reference potential Vss2 are electrically connected. As a result, since the electrostatic discharge protection circuits of both power supply systems are shared, the electrostatic withstand capability of the power supply Vdd2 system, which is weak against electrostatic discharge, can be made approximately the same as that of the power supply Vdd1 system. Further, due to electrostatic discharge, the forward parallel diode in the region A18 becomes conductive, and a part of the surge current of electrostatic discharge flowing from the power supply pad of the power supply Vdd2 system is partially supplied to the power supply Vdd.
Since the current also flows to the first system, it is possible to suppress the voltage increase of the power supply Vdd2 system.

Further, as can be seen by comparing with the above-described conventional layout example, in the example of FIGS. 3 and 4, the pads are connected on the semiconductor substrate facing the adjacent pads of different power supply systems. 8 is formed, there is no useless area where no circuit is formed between pads of different power supply systems, such as areas A7 and A8 in FIGS. Therefore, according to the above-described layout example, it is possible to reduce a wasteful area where a circuit is not formed, a circuit area can be reduced, the degree of integration can be improved, and the number of pins can be increased as compared with the conventional example.

The embodiments described above with reference to FIGS. 1 to 4 are merely examples for explaining the present invention, and the present invention is not limited to this example. For example, in FIG.
The electrostatic discharge protection circuit including the p-type MOS transistor Qp, the n-type MOS transistor Qn, and the resistor R is merely an example, and a part or all of other various electrostatic discharge protection circuits are formed on the semiconductor substrate facing the pad. The present invention can also be realized by doing so.

The number of wiring layers formed on the semiconductor substrate is arbitrary. Further, the shapes of the wirings shown in FIGS. 1 to 4 are examples, and any shape may be used. The selection of the wiring layer used for connecting each circuit is arbitrary, and any wiring layer may be used.

The conductivity type of the semiconductor substrate and the conductivity type of each impurity region are not limited to the examples shown in FIGS. 1 to 4, and can be set arbitrarily. In the example of FIGS. 1 and 2, as an example, MOS
Although a transistor is used, the type of transistor is arbitrary, and for example, a bipolar transistor may be used. Similarly, the type of resistance is arbitrary, and the resistance may be formed using, for example, an impurity region.

In the example of FIG. 4, a pn junction diode is formed as a diode for connecting the pads, but the present invention can be implemented by forming another diode. The number of diodes connected in parallel or in series is also arbitrary. For example, when the noise voltage is high, the number of diodes in series may be increased.

Although the examples of FIGS. 3 and 4 show the case where the reference potentials of different power supply systems are connected by the bidirectional parallel diodes, the different power supply potentials may be connected by the bidirectional parallel diodes. In the example of FIGS. 3 and 4, the diode connecting the reference potential Vss1 and the power supply Vdd2 is formed, but the power supply Vdd1 and the reference potential Vss are formed.
You may form the diode which connects between 2 and. The direction of the diode can be set arbitrarily. Although the bidirectional parallel diode and the forward parallel diode are both formed in the examples of FIGS. 3 and 4, only one of them may be formed.

[0075]

According to the semiconductor device of the present invention, firstly,
The area of the circuit can be reduced as compared with the conventional one. Secondly, it is possible to reduce a wasteful area where a circuit is not formed and improve the degree of integration of the circuit.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an example of a circuit configuration and a layout of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.

FIG. 3 is a schematic diagram showing an example of a layout of a semiconductor device according to a second embodiment of the present invention.

4 is a cross-sectional view of the semiconductor device shown in FIG.

FIG. 5 is a schematic block diagram showing an example of a conventional semiconductor device including an electrostatic discharge protection circuit.

6 is a diagram showing an example of a conventional layout of the semiconductor device shown in FIG.

7 is a cross-sectional view of the semiconductor device shown in FIG.

FIG. 8 is a diagram showing an example of a layout near a pad in a conventional semiconductor device having two power supply systems.

9 is a cross-sectional view of the semiconductor device shown in FIG.

[Explanation of symbols]

1 ... Pad, 2 ... Internal circuit, Qn ... P-type MOS transistor, Qp ... P-type MOS transistor, 11 ... Semiconductor substrate, 12, 18 ... P-type impurity region, 13, 17 ... N-type impurity region, 14 ... N-type Or a p-type impurity region, 15 ...
Polycrystalline silicon film, 16 ... Gate electrode, 21-27 ... Second layer wiring, 31-37 ... Third layer wiring, 41-47 ... Fourth
Layer wiring, 50 ... Interlayer insulating film, 60 ... Via.

Claims (6)

[Claims] 1. A pad for drawing out wiring to the outside of the device, and an electrostatic discharge protection circuit which is formed on at least a part of the semiconductor substrate facing the pad and suppresses a voltage rise of the pad caused by electrostatic discharge. A semiconductor device having. 2. The electrostatic discharge protection circuit includes a first transistor connected between the pad and a power supply line, the first transistor being conductive according to a voltage between the pad and the power supply line, and the pad. 2. The semiconductor device according to claim 1, further comprising a second transistor connected between the pad and the reference potential line, the second transistor being in a conductive state according to a voltage between the pad and the reference potential line. 3. The semiconductor device according to claim 2, wherein the electrostatic discharge protection circuit includes a protection resistor that is serially inserted on a wiring connected to the pad. 4. A first pad for drawing out a first power supply line or a reference potential line corresponding to the first power supply line to the outside of the device, and a second power supply line or the second power supply line. A second pad for drawing out a reference potential line to the outside of the device, and at least a part of the second pad formed on the semiconductor substrate facing the first pad or the second pad, and the first pad. A semiconductor device having at least one diode connected between the second pad and the second pad. 5. The diode is a parallel diode in which a plurality of diodes are connected in parallel in opposite directions to each other, and the first pad connected to the first power supply line,
A parallel diode connecting the second pad connected to the second power supply line, or the first pad connected to the reference potential line corresponding to the first power supply line and the second power supply line. The semiconductor device according to claim 4, further comprising at least one of parallel diodes connected to the second pad connected to a corresponding reference potential line. 6. The diode includes the first pad connected to the first power supply line,
A diode connecting the second pad connected to the reference potential line corresponding to the second power supply line, or the first pad connected to the reference potential line corresponding to the first power supply line; The semiconductor device according to claim 4, further comprising at least one of a diode connected to the second pad connected to the second power supply line.