JPH0553266U - Multilayer printed wiring board - Google Patents
Multilayer printed wiring boardInfo
- Publication number
- JPH0553266U JPH0553266U JP11076391U JP11076391U JPH0553266U JP H0553266 U JPH0553266 U JP H0553266U JP 11076391 U JP11076391 U JP 11076391U JP 11076391 U JP11076391 U JP 11076391U JP H0553266 U JPH0553266 U JP H0553266U
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- multilayer printed
- concave portion
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
(57)【要約】
【構成】 多層印刷配線基板1であって、その下部層
は、端面に電極パタ−ンが形成されている凹部4を有す
る1枚以上の基板1a〜1cより成り、上部層は、前記
下部層の基板1a〜1cに形成されている前記凹部4の
最上面開口端を閉塞するように設けられた1枚以上の基
板1eより成ることを特徴とする。
【効果】 多層印刷配線基板の表面が広く利用出来ると
ともに、その表面に実装された部品や印刷された配線パ
タ−ンと端面の凹部に形成された電極パタ−ンとは、隔
離され、半田付の際に短絡を生じなくなる。
(57) [Summary] [Structure] A multilayer printed wiring board 1 whose lower layer is composed of one or more substrates 1a to 1c each having a concave portion 4 having an electrode pattern formed on an end face thereof, and an upper portion thereof. The layer is formed of one or more substrates 1e provided so as to close the uppermost open end of the concave portion 4 formed in the lower layer substrates 1a to 1c. [Effect] The surface of the multilayer printed wiring board can be widely used, and the components mounted on the surface and the printed wiring pattern are separated from the electrode pattern formed in the concave portion of the end face by soldering. No short circuit will occur.
Description
【0001】[0001]
本考案は、表面実装用電子部品として利用される多層印刷配線基板に関する。 The present invention relates to a multilayer printed wiring board used as an electronic component for surface mounting.
【0002】[0002]
以下、図面に基づいて、従来の表面実装用電子部品として利用される多層印刷 配線基板について説明する。 図2(A),(B)は、第1の従来例である多層印刷配線基板の斜視図および 上面図である。 図2(A),(B)において、1は、4枚の基板1a,1b,1c,1dより なる多層印刷配線基板であり、2は、配線パタ−ンが印刷されたり、電子部品や シ−ルドカバ−が実装される表面である。3は、多層印刷配線基板1が、図示せ ぬマザ−ボ−ド上に実装される場合に、マザ−ボ−ド上に接着される裏面である 。4は、多層印刷配線基板1の端面に設けられ、電極パタ−ンが被着して形成さ れる凹部である。この凹部4の電極パタ−ンは、多層印刷配線基板1が、図示せ ぬマザ−ボ−ド上に実装される場合において、図示せぬマザ−ボ−ド上の電極と 、リフロ−半田付等によって接続されるのに使用される。 Hereinafter, a multilayer printed wiring board used as a conventional surface mount electronic component will be described with reference to the drawings. FIGS. 2A and 2B are a perspective view and a top view of a first conventional example of a multilayer printed wiring board. In FIGS. 2A and 2B, reference numeral 1 is a multilayer printed wiring board consisting of four boards 1a, 1b, 1c and 1d, and 2 is a printed wiring pattern, an electronic component or a printed circuit board. -The surface on which the rudder cover is mounted. Reference numeral 3 denotes a back surface which is adhered to the mother board when the multilayer printed wiring board 1 is mounted on the mother board (not shown). Reference numeral 4 is a concave portion provided on the end face of the multilayer printed wiring board 1 and formed by depositing an electrode pattern. When the multilayer printed wiring board 1 is mounted on a mother board (not shown), the electrode patterns of the recesses 4 are reflow soldered to the electrodes on the mother board (not shown). Used to be connected by etc.
【0003】 5は、表面2上に、接着剤等によって密閉構造を形成して実装されるシ−ルド カバ−である。シ−ルドカバ−5の外形寸法は、凹部4をさける為に、多層印刷 配線基板1の外形寸法より小さくなっている。また、表面2上には、シ−ルドカ バ−5内で、図示せぬ配線パタ−ンが印刷され、図示せぬ電子部品が実装されて いる。Reference numeral 5 is a shield cover which is mounted on the surface 2 by forming an airtight structure with an adhesive or the like. The outer dimension of the shield cover 5 is smaller than that of the multilayer printed wiring board 1 in order to avoid the recess 4. On the surface 2, a wiring pattern (not shown) is printed in the shield cover 5 and electronic parts (not shown) are mounted.
【0004】 図3(A),(B)は、第2の従来例である多層印刷配線基板の斜視図および 上面図である。 図3(A),(B)は、図2(A),(B)に示される第1の従来例の表面2 の面積を最大限に有効利用しようとしたものであり、その為に、凹部4をさける 為にシ−ルドカバ−5の側面に切り欠き6を設け、シ−ルドカバ−5の外形寸法 を、多層印刷配線基板1の外形寸法と同じ寸法まで大きくしている。 なお、切り欠き6は、凹部4に形成されている電極パタ−ンとシ−ルドカバ− 5の短絡を防止する為のものである。 ところで、図3(A),(B)に示す第2の従来例では、図2(A),(B) に示す第1の従来例とちがって、切り欠き6を設けている為、シ−ルドカバ−5 と表面2での密閉構造を形成することが出来ない。FIGS. 3A and 3B are a perspective view and a top view of a second conventional example of a multilayer printed wiring board. 3 (A) and 3 (B) are intended to maximize the effective use of the area of the surface 2 of the first conventional example shown in FIGS. 2 (A) and 2 (B). In order to avoid the recess 4, a notch 6 is provided on the side surface of the shield cover 5 so that the outer dimension of the shield cover 5 is increased to the same as the outer dimension of the multilayer printed wiring board 1. The notch 6 is for preventing a short circuit between the electrode pattern formed in the recess 4 and the shield cover 5. By the way, in the second conventional example shown in FIGS. 3A and 3B, the cutout 6 is provided unlike the first conventional example shown in FIGS. -A closed structure cannot be formed between the surface of the cover 2 and the lid cover 5.
【0005】[0005]
しかしながら、上記の従来の多層印刷配線基板においては、電極パタ−ンを形 成する為の凹部4によって、多層印刷配線基板1の表面2の有効利用面積が小さ くなるという問題がある。 さらに、多層印刷配線基板1をマザ−ボ−ド上へ半田付する際に、表面2上に 形成された配線パタ−ンや電子部品やシ−ルドカバ−と、凹部4に形成された電 極パタ−ンとが、溶融した半田によって短絡し易いという問題もある。 However, in the above-mentioned conventional multilayer printed wiring board, there is a problem that the effective use area of the surface 2 of the multilayer printed wiring board 1 becomes small due to the concave portion 4 for forming the electrode pattern. Furthermore, when the multilayer printed wiring board 1 is soldered onto the mother board, the wiring patterns and electronic components and shield covers formed on the surface 2 and the electrodes formed in the recesses 4 are soldered. There is also a problem that the pattern and the pattern are easily short-circuited by the molten solder.
【0006】 本考案の目的は、上記の問題を解決し、多層印刷配線基板表面を有効利用出来 、かつマザ−ボ−ド上への半田付の際に、多層印刷配線基板の端面の凹部に設け られる電極パタ−ンと多層印刷配線基板の表面に印刷される配線パタ−ンや実装 される電子部品やシ−ルドカバ−との短絡の生じない多層印刷配線基板を提供す ることにある。An object of the present invention is to solve the above problems, to effectively utilize the surface of a multilayer printed wiring board, and to make a recess on the end surface of the multilayer printed wiring board when soldering on a mother board. It is an object of the present invention to provide a multilayer printed wiring board which does not cause a short circuit between the provided electrode pattern, the wiring pattern printed on the surface of the multilayer printed wiring board, the mounted electronic parts and the shield cover.
【0007】[0007]
上記の課題を解決する為に、本考案は、多層印刷配線基板であって、該多層印 刷配線基板の下部層は、端面に電極パタ−ンが形成されている凹部を有する1枚 以上の基板より成り、 前記多層印刷配線基板の上部層は、前記下部層の基板に形成されている前記凹部 の最上面開口端を閉塞するように設けられた1枚以上の基板より成ることを特徴 とする。 In order to solve the above-mentioned problems, the present invention is a multilayer printed wiring board, wherein the lower layer of the multilayer printed wiring board has one or more recesses having electrode patterns formed on the end faces. A substrate, wherein the upper layer of the multilayer printed wiring board is composed of one or more substrates provided so as to close the uppermost opening end of the recess formed in the substrate of the lower layer. To do.
【0008】[0008]
上記の本考案の多層印刷配線基板においては、上部層の基板の端面には、凹部 がないので、表面が広くなるとともに、 この上部層によって、その最上表面に印刷された配線パタ−ンや実装された電子 部品やシ−ルドカバ−と下部層の基板の端面の凹部に形成される電極パタ−ンと が確実に隔離される。 In the above-mentioned multilayer printed wiring board of the present invention, since the end face of the substrate of the upper layer does not have a recess, the surface becomes wide, and the wiring pattern and mounting printed on the uppermost surface of the upper layer are achieved by this upper layer. The electronic components and shield cover thus formed are reliably separated from the electrode pattern formed in the concave portion of the end surface of the lower substrate.
【0009】[0009]
以下、図面に基づいて、本考案の実施例を説明する。 なお、図において、従来例と対応する部分には、同一の符号をつけて説明を省 略する。 図1(A),(B)は、本考案の一実施例である多層印刷配線基板を示す斜視 図および上面図である。 An embodiment of the present invention will be described below with reference to the drawings. Incidentally, in the figure, the portions corresponding to those of the conventional example are designated by the same reference numerals and the description thereof will be omitted. 1A and 1B are a perspective view and a top view showing a multilayer printed wiring board according to an embodiment of the present invention.
【0010】 図1(A)において、従来例と異なる点は以下の通りである。すなわち、多層 印刷配線基板1の最上部に配される基板1eは、その端面に凹部を有しない。 これによりシ−ルドカバ−5は、その側面に切り欠きを設けることなく、その 外形寸法を多層印刷配線基板1の外形寸法と同じ寸法まで大きくすることが出来 る。In FIG. 1A, the points different from the conventional example are as follows. That is, the substrate 1e arranged on the uppermost part of the multilayer printed wiring board 1 does not have a recess on its end face. As a result, the shield cover 5 can have its outer dimensions increased to the same as the outer dimensions of the multilayer printed wiring board 1 without providing a notch on its side surface.
【0011】 ところで、基板1eは、端面に電極を有していないが、もし、電極が必要な場 合は、基板内部にスルホ−ルを設け、これによって、他の基板の電極と接続すれ ば、端面に電極パタ−ンを設ける必要はない。 図1(B)の上面図において、凹部4は、シ−ルドカバ−5の外形の内側に位 置している為、破線にて、透視図で示されている。 なお、上記の本考案の一実施例においては、多層印刷配線基板1の表面には、 シ−ルドカバ−が実装されたもので説明されているが、多層印刷配線基板1の表 面に実装されるものは、シ−ルドカバ−に限らず、電子部品であってもよいし、 また、表面には、配線パタ−ンが印刷されてあるものでもよい。By the way, the substrate 1e does not have an electrode on the end face, but if an electrode is required, a sulfol is provided inside the substrate so that it can be connected to an electrode of another substrate. It is not necessary to provide an electrode pattern on the end face. In the top view of FIG. 1 (B), since the recess 4 is located inside the outer shape of the shield cover 5, it is shown by a broken line in a perspective view. Although the shield cover is mounted on the surface of the multilayer printed wiring board 1 in the above-described embodiment of the present invention, it is mounted on the surface of the multilayer printed wiring board 1. The material is not limited to the shield cover, and may be an electronic component, or a wiring pattern may be printed on the surface.
【0012】[0012]
以上説明したように、本考案の多層印刷配線基板は、上部層の基板の端面には 、凹部がないので、表面をその外形寸法まで広く利用できるという効果を有する とともに、 この上部層の基板によって、その最上表面に印刷された配線パタ−ンや実装さ れた電子部品やシ−ルドカバ−と下部層の基板の端面の凹部に形成される電極パ タ−ンとが隔離される為に、マザ−ボ−ド上への半田付等の際に、表面に印刷さ れた配線パタ−ンや実装された電子部品やシ−ルドカバ−と下部層の基板の端面 の凹部に形成される電極パタ−ンとが溶融半田等によって、短絡することがない という効果も有する。 As described above, the multilayer printed wiring board of the present invention has an effect that the surface can be widely used up to its outer dimensions because the end surface of the substrate of the upper layer does not have the concave portion. , The wiring pattern printed on the uppermost surface thereof, the mounted electronic components and shield cover are separated from the electrode pattern formed in the concave portion of the end face of the lower layer substrate, Electrodes formed on wiring patterns printed on the surface, mounted electronic components and shield covers, and recesses on the end surface of the lower substrate when soldering onto the mother board. It also has the effect of not causing a short circuit with the pattern due to molten solder or the like.
【図1】本考案の一実施例である多層印刷配線基板を示
す斜視図および上面図。FIG. 1 is a perspective view and a top view showing a multilayer printed wiring board according to an embodiment of the present invention.
【図2】第1の従来例である多層印刷配線基板を示す斜
視図および上面図。FIG. 2 is a perspective view and a top view showing a multilayer printed wiring board which is a first conventional example.
【図3】第2の従来例である多層印刷配線基板を示す斜
視図および上面図。FIG. 3 is a perspective view and a top view showing a multilayer printed wiring board which is a second conventional example.
1 多層印刷配線基板 2 表面 3 裏面 4 電極パタ−ンの形成される凹部 5 シ−ルドカバ− 6 切り欠き DESCRIPTION OF SYMBOLS 1 Multilayer printed wiring board 2 Front surface 3 Back surface 4 Recesses where electrode patterns are formed 5 Shield cover 6 Notches
Claims (1)
配線基板の下部層は、端面に電極パタ−ンが形成されて
いる凹部を有する1枚以上の基板より成り、 前記多層印刷配線基板の上部層は、前記下部層の基板に
形成されている前記凹部の最上面開口端を閉塞するよう
に設けられた1枚以上の基板より成ることを特徴とする
多層印刷配線基板。1. A multi-layer printed wiring board, wherein a lower layer of the multi-layer printed wiring board comprises one or more substrates each having a recess having an electrode pattern formed on an end face thereof. The multilayer printed wiring board according to claim 1, wherein the upper layer comprises one or more substrates provided so as to close the uppermost opening end of the recess formed in the lower substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11076391U JPH0553266U (en) | 1991-12-18 | 1991-12-18 | Multilayer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11076391U JPH0553266U (en) | 1991-12-18 | 1991-12-18 | Multilayer printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0553266U true JPH0553266U (en) | 1993-07-13 |
Family
ID=14543955
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11076391U Withdrawn JPH0553266U (en) | 1991-12-18 | 1991-12-18 | Multilayer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0553266U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020005922A (en) * | 2000-07-11 | 2002-01-18 | 이형도 | Multilayer circuit board |
JP2002164658A (en) * | 2000-11-29 | 2002-06-07 | Sharp Corp | Module board |
-
1991
- 1991-12-18 JP JP11076391U patent/JPH0553266U/en not_active Withdrawn
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020005922A (en) * | 2000-07-11 | 2002-01-18 | 이형도 | Multilayer circuit board |
JP2002164658A (en) * | 2000-11-29 | 2002-06-07 | Sharp Corp | Module board |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19960404 |