JP2002164658A - Module board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a module board which can be manufactured at a low cost without lowering its reliability. SOLUTION: With respect to the module board 1, no continuity groove 21 is formed on the side surfaces of a top-surface-layer board 5 having mounted semiconductor integrated-circuit elements 11 thereon and mounted passive elements 12 thereon, while the continuity grooves 21 are formed on the side surfaces of an intermediate-layer board 6 and a bottom-surface-layer board 7. Therefore, when coating with a sealing resin 3, the semiconductor integrated- circuit elements 11 and the passive elements 12, etc., mounted on the top-surface- layer board 5, no sealing resin 3 flows into the continuity grooves 21. The soldering areas of the continuity grooves 21 can be secured not to reduce the reliability of the electric connections of the module board 1 with the external, and it can be manufactured at a low cost without the problem of its increased cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a module substrate having an electronic component mounted on a surface and a conductive groove formed on a side surface as an electrode used for electrical connection to the outside.

[0002]

2. Description of the Related Art Conventionally, a module substrate having electronic components (hereinafter, referred to as chip components) such as semiconductor integrated circuit elements, resistors, inductors, and capacitors mounted on a substrate has been used as a kind of integrated circuit. This module board is mounted on a wiring board together with other components, for example, another module board and a packaged integrated circuit.
As the module substrate, a ceramic substrate or a glass epoxy substrate is often used.

[0003] The electrical connection between the wiring pattern formed on the substrate and the terminal of the chip is performed by wire bonding for connecting the terminal of the chip component mounted face up to the wiring pattern of the substrate with a wire, or mounted face down. It is performed by direct connection or the like in which the terminals of the chip component are connected to the wiring pattern of the substrate with solder or the like. In order to protect the mounted chip components and the wiring patterns on the substrate, these are covered with a metal cap or a sealing resin.

The above-mentioned module substrate is particularly effective when handling a high-frequency integrated circuit device operating in the gigahertz band using GaAsIC or the like as a material. As is well known, the characteristic impedance changes depending on the arrangement position of the chip component on the substrate, the wire shape of the wire bonding, the shape of the wiring pattern formed on the substrate, and the like. However, since the characteristic impedance can be matched on the module substrate, the high-frequency characteristics of the high-frequency integrated circuit element can be easily and stably extracted.

[0005] The module substrate is obtained by mounting chip components on a very small substrate of several millimeters by several millimeters. Recently, a multilayer substrate has been used, and not only double-sided wiring but also internal wiring has been utilized.

In the module substrate on which the above-described high-frequency integrated circuit element is mounted, in order to match the characteristic impedance between the high-frequency integrated circuit element and the input / output signal line, the width of the signal line is adjusted and the insulating substrate is mounted. There has been proposed a device in which a ground plane pattern and a microstrip transmission line are formed via a ground. It has also been proposed to arrange a signal line or a ground pattern on an internal wiring layer of a multilayer substrate to shield a radio wave from a high-frequency signal.

In the module substrate, bumps provided on the lower portion of the substrate, lead terminals extending from the lower portion or the side surface, end surface electrodes provided on the side surface of the substrate, and the like are used as connection terminals used for electrical connection to the outside. In particular, the above-mentioned end face electrodes are often used. The end surface electrode is a conductive groove formed on the side surface of the substrate as described later. The reason is,
When the module board is mounted on the wiring board, for example, when it is electrically connected with solder, the quality of the soldered state can be easily checked by a silent inspection of the side of the mounted module board, and the soldering area is relatively large, so the This is because the reliability of the dynamic connection is high.

Hereinafter, a process of manufacturing a module substrate having the above-mentioned end face electrodes will be briefly described. The module board forms multiple module boards on a large area board,
It is separated by dicing.

First, in the case of a single-layer substrate, a plurality of wiring patterns corresponding to a module substrate manufactured by etching or the like are formed on a large-area substrate. When the wiring patterns are formed on both surfaces of the substrate, through holes for electrically connecting the wiring patterns on both surfaces of the substrate are formed as necessary. On the other hand, in the case of a multi-layer substrate, a plurality of wiring patterns corresponding to the module substrate to be manufactured are formed on the substrate of each layer, these substrates are bonded, and if necessary, wiring patterns not formed on the same surface are electrically connected. To form through holes.

Further, a through hole (through hole for an end face electrode) is formed at a position where an end face electrode is provided on each module board cut by dicing with respect to the large area board.

The through-holes formed in the above steps are formed by plating Ni-Sn on the inner surface, Ni-Au
The conductor layer is formed by plating or solder plating.

Chip components such as semiconductor integrated circuit elements and passive elements are mounted on a large-area substrate. At this time, the wiring on the board and the chip component are electrically connected by the above-described wire bonding, soldering or the like.

The mounted chip components, wiring on the substrate, and the like are covered with a sealing resin.

The individual module substrates are separated by dicing or the like (separated by a line passing through substantially the center of the end surface electrode through hole formed above). Therefore, a semi-cylindrical end surface electrode (conductive groove) is formed on the end surface of each separated module substrate.

[0015]

Incidentally, when the chip components mounted as described above and the wiring on the substrate are covered with a sealing resin, the sealing resin may flow into the through-holes for the end face electrodes and solidify. The sealing resin adheres to the end surface electrodes formed on the side surfaces of the module substrate separated as described above. For this reason, the soldering area of the end surface electrode is small, and the reliability of the electrical connection between the module substrate and the outside is reduced.

Therefore, it has been proposed to prevent the inflow of the sealing resin into the through-holes for the end face electrodes by masking the through-holes for the end face electrodes with an insulating tape or a film before covering with the sealing resin. (Japanese Patent Laid-Open No. 11-2514)
No. 87).

However, a step of masking the through-holes for the end face electrodes with an insulating tape, a film or the like must be added to the above-mentioned manufacturing steps (1) to (4), and there is a problem of an increase in cost.

An object of the present invention is to provide a module substrate which can be manufactured at low cost without reducing reliability.

[0019]

A module board according to the present invention has the following arrangement to solve the above-mentioned problems.

(1) A module substrate, wherein electronic components are mounted on the surface of the multilayer substrate, and conduction grooves are formed on side surfaces of the multilayer substrate as electrodes used for electrical connection to the outside. The conductive groove is not formed on at least one of the layers.

In the above configuration, the conductive groove formed on the side surface of the multilayer substrate is used as a so-called end surface electrode for electrical connection to the outside. Here, since at least one layer of the multilayer substrate does not have the conductive groove formed on the side surface, when the electronic component mounted on the surface of the multilayer substrate is covered with a sealing resin, a layer where the conductive groove is not formed is formed. The sealing resin does not flow into the conductive groove formed in the layer on the bottom surface side. For this reason, the soldering area of the end surface electrodes formed on the side surface of the module substrate can be secured, and the reliability of the electrical connection between the module substrate and the outside is not reduced. In addition, since it is not necessary to mask with an insulating tape or a film in order to prevent the inflow of the sealing resin as in the related art, it is possible to manufacture the semiconductor device at low cost without increasing the cost.

Further, the higher the layer in which the conductive groove is not formed, the larger the soldering area of the end face electrode. Therefore, the layer in which the conductive groove is not formed is a layer such as a surface layer on which electronic components are mounted.
It is better to make it relatively high.

(2) electronic components are mounted on the surface of the substrate,
A module substrate having a conductive groove formed on a side surface of the substrate as an electrode used for electrical connection with the outside, wherein a height of the conductive groove is less than a thickness of the substrate.

In this configuration, the height of the conductive groove formed on the side surface of the substrate is set to be less than the thickness of the substrate, so that the same effect as (1) is obtained.

In the present invention, the substrate may be a multi-layer substrate or a single-layer substrate.

Further, by forming an internal wiring layer between the layers of the multilayer substrate, it is possible to obtain a module substrate which is small in size and in which characteristic impedance can be easily matched.

In particular, the present invention is effective for a module substrate on which a high-frequency circuit element is mounted and a module substrate in which a mounted electronic component is covered with a sealing resin.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a module board according to an embodiment of the present invention will be described. As this type of module substrate, for example, there is a power amplifier of a mobile phone.

FIG. 1 is a diagram showing a module substrate according to an embodiment of the present invention. FIG. 2 is a view showing a state in which the sealing resin is removed in FIG.

In the module substrate 1 of this embodiment, the electronic components mounted on the surface of the substrate 2 and the wiring patterns formed on the surface of the substrate 2 are covered with a sealing resin 3. The substrate 2 is a three-layer substrate in which three substrates 5, 6, and 7 are bonded. For example, the substrates 5 to 7 are 6.0 mm long and 6.0 mm wide.
0 mm and a thickness of 0.2 mm (the thickness of the substrate 2 is about 0.3 mm).
6 mm. ). Hereinafter, the substrate 5 is referred to as a surface layer substrate 5, the substrate 6 is referred to as an intermediate layer substrate 6, and the substrate 7 is referred to as a bottom layer substrate 7.

As shown in FIG. 2, a semiconductor integrated circuit element 11 and passive elements 12 such as a resistance element, an inductor element and a capacitor element are mounted on the surface layer substrate 5. The semiconductor integrated circuit element 11 and the passive element 12 correspond to an electronic component according to the present invention. The sealing resin 3 covers the semiconductor integrated circuit element 11 and the passive element 12 mounted on the surface layer substrate 5 and the wiring pattern formed on the surface of the surface layer substrate 5. This module substrate 1 is a power amplifier of a mobile phone. The semiconductor integrated circuit element 11 is G
This is a high-frequency integrated circuit device that operates in the gigahertz band using aAsIC as a material.

Although the semi-cylindrical conductive grooves 21 are formed on the side surfaces of the intermediate layer substrate 6 and the bottom layer substrate 7, the conductive grooves 21 are not formed on the side surfaces of the surface layer substrate 5.
The conduction groove 21 is, for example, a semi-cylindrical shape having a diameter of 0.5 mm. Ni-Sn plating, Ni-
The conductor layer is formed by Au plating, solder plating, or the like.
The conduction groove 21 is an end face electrode used for electrical connection with the outside.

FIG. 2 shows the semiconductor integrated circuit element 11 mounted face-up on the surface layer substrate 5. This semiconductor integrated circuit element 11 is electrically connected to a wiring pattern 15 formed on the surface layer substrate 5 by wires 16. Wiring pattern 1 formed on surface layer substrate 5
5 has a line width of 0.8 mm and a line thickness of 30 μm, for example, and can be formed by well-known etching.

The wiring pattern 15 is also formed on a surface other than the surface of the surface layer substrate 5 (the back surface of the surface layer substrate 5, the front and back surfaces of the intermediate layer substrate 6 and the bottom layer substrate 7). However,
There may be a surface on which the wiring pattern 15 is not formed.

Wiring pattern 1 formed on different surface
5 is electrically connected by a through hole 17 (or a via hole) formed in the substrate 2. A conductor layer is formed on the inner surface of the through hole 17 by Ni-Sn plating, Ni-Au plating, solder plating, or the like.

The conductive groove 21 is an end face electrode used for electrical connection with the outside as described above. In the module substrate 1 of this embodiment, lands 18 are formed on the surface of the bottom layer substrate 7. The land 18 is formed around the conduction groove 21 and is for ensuring electrical connection between the conduction groove 21 and the inside of the module substrate 1. In addition,
The lands 18 may be formed on a plurality of surfaces.

The land 18 is connected to the semiconductor integrated circuit device 1.
1 and the passive element 12 are formed on a surface other than the mounting surface,
Since the size of the land 18 does not affect the mounting area of the electronic component on the substrate 2, electrical connection between the conduction groove 21 and the inside of the module substrate 1 can be ensured.
The module substrate 1 can be prevented from being enlarged.

Hereinafter, the manufacturing process of the above-described module substrate 1 will be described.

The large area surface layer substrate 5A shown in FIG. 3A has a plurality of wiring patterns of the surface layer substrate 5 formed thereon, and the large area intermediate layer substrate 6A shown in FIG. A plurality of wiring patterns of the substrate 6 are formed.
A plurality of wiring patterns of the bottom layer substrate 7 are formed on the large area bottom layer substrate 7A shown in FIG. These wiring patterns can be formed by well-known etching.

The large-area intermediate layer substrate 6A and the large-area bottom layer substrate 7A are bonded together with the position of the wiring pattern formed on the surface aligned. Thereafter, a through hole 21A is formed at a position where the conductive groove 21 is to be formed in the module substrate 1 described above. N on the inner surface of through hole 21A
A conductor layer is formed by i-Sn plating, Ni-Au plating, solder plating, or the like (see FIG. 4). FIG. 4 is a view in which the wiring pattern formed on the surface is omitted.

Next, with respect to the large-area intermediate layer substrate 6A and the large-area bottom layer substrate 7A in which the through holes 21A are formed,
The large-area surface layer substrate 5A is bonded (see FIG. 5). FIG. 5 is also a view in which the wiring pattern formed on the surface is omitted. Thereafter, through holes 17 for electrically connecting the wiring patterns formed on the front and back surfaces of the large-area surface layer substrate 5A, the large-area intermediate layer substrate 6A, and the large-area bottom layer substrate 7A are formed. Then, the semiconductor integrated circuit element 11 and the passive element 1 are formed by wire bonding or soldering.
2 is mounted on the surface of the large-area surface layer substrate 5A (see FIG. 6).

Next, the mounted semiconductor integrated circuit device 1
1. In order to protect the passive element 12 and the wiring pattern 15 on the surface of the large-area surface layer substrate 5A, the large-area surface layer substrate 5A
Is covered with a sealing resin 3 (see FIG. 7). The coating with the sealing resin 3 can be performed by well-known printing sealing.

The opening of the through hole 21A is covered with the large area surface layer substrate 5A. Therefore, the sealing resin 3 does not flow into the through-hole 21A in the above-described coating with the sealing resin 3.

Then, the individual module substrates 1 are cut off by dicing or the like. At this time, it is separated by a line passing through the center of the through hole 21A. Thereby, the semi-cylindrical conductive grooves 21 are formed on the side surfaces of the intermediate layer substrate 6 and the bottom layer substrate 7 shown in FIGS. 1 and 2, and the conductive grooves 3 are formed on the side surfaces of the surface layer substrate 5. An unformed module substrate 1 is obtained.

As described above, the module substrate 1 is provided with the sealing resin 3 in the through holes 21A in the above steps.
Does not flow, so that the sealing resin 3 does not adhere to the conductive groove 21. Therefore, the soldering area in the conductive groove 21 is reduced, and the reliability is not reduced.

In addition, since it is not necessary to mask the through hole 21A with an insulating tape or a film in order to prevent the inflow of the sealing resin 3 as in the prior art, the cost can be suppressed.

Further, since the wiring patterns are formed on the intermediate layer substrate 6 and the bottom layer substrate 7, that is, since the internal wiring is utilized, it is possible to easily shield the radio wave from the radio wave signal.

In the above embodiment, the substrate 2 is a three-layer substrate, but may be a two-layer, four-layer, five-layer substrate, or the like. Further, in the above-described embodiment, an example in which the conduction groove 21 is not formed only in the surface layer substrate 5 has been described, but the layer in which the conduction groove 21 is not formed is not limited to the surface layer substrate 5 and may be the intermediate layer substrate 6. . Further, the layer in which the conduction groove 21 is not formed is not limited to one layer, but may be a plurality of layers.

Further, as shown in FIG. 8, the substrate 2 may be constituted by a single-layer substrate. In this case, when the above-described through hole 21A is formed in the substrate 2, instead of forming a through hole, a hole that does not reach the surface from the bottom surface side of the substrate 2 may be formed. Note that the land 18 may be formed on the bottom side of the substrate 2.

Further, the module substrate 1 is a surface layer substrate 5
Also, a conduction groove 21 as shown in FIG. 9 may be formed. As shown in the drawing, the conductive grooves 21 of the surface layer substrate 5 are formed at positions shifted from the conductive grooves 21 formed on the intermediate layer substrate 6 and the bottom layer substrate 7.

In this case, before bonding the large-area surface layer substrate 5A to the large-area intermediate layer substrate 6A and the large-area bottom layer substrate 7A in which the through holes 21A are formed, the large-area surface layer substrate 5A is A through hole 21A is formed.

In this module substrate 1, the intermediate layer substrate 6
The conductive groove 21 formed in the bottom layer substrate 7 is used as an end face electrode used for electrical connection to the outside similarly to the above-described embodiment. On the other hand, the conduction groove 21 provided in the surface layer substrate 5 is used as a mounting portion of a metal cap 25 that covers these in order to protect chip components mounted on the surface layer substrate 5 and wiring patterns on the substrate.

More specifically, a projection 26 is provided on the metal cap 25 at a position corresponding to the conduction groove 21 provided on the surface layer substrate 5. Thereby, the mounting position of the metal cap 25 with respect to the module substrate 1 can be adjusted only by aligning the protrusion 26 of the metal cap 25 with the conductive groove 21 provided in the surface layer substrate 5.

Further, the metal cap 25 can be fixed to the module substrate 1 by soldering the projection 26 of the metal cap 25 to the conductive groove 21 provided in the surface layer substrate 5.

[0055]

As described above, according to the present invention, it is possible to reliably prevent the sealing resin from adhering to the conductive groove used for the electrical connection with the outside, so that the reliability of the electrical connection with the outside can be improved. Does not lower the performance. Further, an increase in cost for preventing the inflow of the sealing resin into the conductive groove is suppressed, and the device can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a diagram showing a module substrate according to an embodiment of the present invention.

FIG. 2 is a diagram showing a module substrate according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a manufacturing process of the module substrate according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a manufacturing process of the module substrate according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a manufacturing process of the module substrate according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a manufacturing process of the module substrate according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating a manufacturing process of the module substrate according to the embodiment of the present invention.

FIG. 8 is a diagram showing a module substrate according to another embodiment of the present invention.

FIG. 9 is a diagram showing a module substrate according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1-module substrate 2-substrate 3-sealing resin 5-surface layer substrate 6-interlayer substrate 7-bottom layer substrate 11-semiconductor integrated circuit 12-passive element 15-wiring pattern 21-conduction groove 25-metal cap

Claims (7)

[Claims] An electronic component is mounted on a surface of a multilayer substrate,
A module substrate in which a conductive groove is formed on a side surface of the multilayer substrate as an electrode used for electrical connection with the outside, wherein the module substrate does not have the conductive groove formed in at least one layer of the multilayer substrate. 2. A module substrate having an electronic component mounted on a surface of a substrate and a conductive groove formed on a side surface of the substrate as an electrode used for electrical connection with the outside, wherein the height of the conductive groove is A module substrate that is less than the thickness of the substrate. 3. The module substrate according to claim 1, wherein the conductive groove is not formed in a surface layer on which the electronic component is mounted. 4. The module substrate according to claim 2, wherein said substrate is a multilayer substrate. 5. The module substrate according to claim 1, wherein an internal wiring layer is formed between layers of the multilayer substrate. 6. The module substrate according to claim 1, wherein the electronic component includes a high-frequency circuit element. 7. The module substrate according to claim 1, wherein the electronic component is sealed with a resin.