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JPH07254766A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH07254766A
JPH07254766A JP6191167A JP19116794A JPH07254766A JP H07254766 A JPH07254766 A JP H07254766A JP 6191167 A JP6191167 A JP 6191167A JP 19116794 A JP19116794 A JP 19116794A JP H07254766 A JPH07254766 A JP H07254766A
Authority
JP
Japan
Prior art keywords
wiring pattern
mounting component
surface mounting
inner layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6191167A
Other languages
Japanese (ja)
Inventor
Shigeki Shiino
重樹 椎野
Katsuhiko Inoue
勝彦 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Akai Electric Co Ltd
Original Assignee
Akai Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Akai Electric Co Ltd filed Critical Akai Electric Co Ltd
Priority to JP6191167A priority Critical patent/JPH07254766A/en
Publication of JPH07254766A publication Critical patent/JPH07254766A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To increase the packaging density by a method wherein the first surface packaging part is packaged on an inner layer wiring pattern exposed by a notch while the second surface packaging part is packaged on the surface of the wiring pattern so as to cover the first surface packaging part so as to laminatedly package the first second packaging parts. CONSTITUTION:A notch 12 is partly made on a board 2 having a wiring pattern exceeding two layers thereon so as to expose an inner layer wiring pattern 13 so that the first surface packaging part 19 may be packaged on this exposed inner layer wiring pattern 13 as well as to package the second surface packaging part 20 is to be packaged on the surface of the wiring patterns 7, 8 so as to cover the first surface packaging part 19.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、二層以上の配線パタ
ーン(多層配線パターン)を有する印刷配線基板に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board having a wiring pattern of two or more layers (multilayer wiring pattern).

【0002】[0002]

【従来の技術】一般に、多層配線パターンを有する印刷
配線基板として、図2に示すものが知られている。図2
において、1は印刷配線基板であり、積層された3枚の
基板2、3、4よりなる。基板2には配線パターン5、
6、7、8が設けられ、基板3、4にも図示していない
配線パターンが設けられている。配線パターン5、6に
はリード型部品9が半田付けされ、配線パターン7、8
には面実装部品10がクリーム半田11により実装され
ている。前記した配線パターン6、7、8はスルーホー
ルにより前記基板2または3の配線パターンに接続され
ている。
2. Description of the Related Art Generally, a printed wiring board having a multilayer wiring pattern shown in FIG. 2 is known. Figure 2
In FIG. 1, reference numeral 1 is a printed wiring board, which is composed of three stacked substrates 2, 3, and 4. The wiring pattern 5 on the substrate 2
6, 7, and 8 are provided, and wiring patterns (not shown) are also provided on the substrates 3 and 4. The lead type component 9 is soldered to the wiring patterns 5 and 6, and the wiring patterns 7 and 8
The surface mount component 10 is mounted on the board with the cream solder 11. The wiring patterns 6, 7 and 8 described above are connected to the wiring patterns of the substrate 2 or 3 by through holes.

【0003】[0003]

【発明が解決しようとする課題】上記のように従来の多
層配線パターンを有する印刷配線基板では、表面の配線
パターン5、6、7、8にしか部品9、10を実装する
ことができなかったため、部品を積み重ねて実装するこ
とができず、このため実装密度を充分に高くすることが
できなかった。この発明は上記の欠点を除去することを
目的とするものである。
As described above, in the conventional printed wiring board having the multilayer wiring pattern, the components 9, 10 can be mounted only on the wiring patterns 5, 6, 7, 8 on the surface. However, the components cannot be stacked and mounted, and therefore the mounting density cannot be increased sufficiently. The present invention aims to eliminate the above-mentioned drawbacks.

【0004】[0004]

【課題を解決するための手段】上記の目的を達成するた
めに、この発明の印刷配線基板は、二層以上の配線パタ
ーンを有する印刷配線基板において、表面の配線パター
ンが設けられた基板を部分的に切り欠いて内層配線パタ
ーンを露出せしめ、この露出された内層配線パターンに
第1の面実装部品を実装すると共に、第1の面実装部品
を覆うように第2の面実装部品を前記表面の配線パター
ンに実装したことを特徴とするものである。
In order to achieve the above object, the printed wiring board of the present invention is a printed wiring board having a wiring pattern of two or more layers, in which the substrate provided with the wiring pattern on the surface is partially formed. Are cut out to expose the inner layer wiring pattern, the first surface mounting component is mounted on the exposed inner layer wiring pattern, and the second surface mounting component is provided on the surface so as to cover the first surface mounting component. It is characterized by being mounted on the wiring pattern.

【0005】[0005]

【作用】前記露出された内層配線パターンに第1の面実
装部品を実装すると共に、第1の面実装部品を覆うよう
に第2の面実装部品を前記表面の配線パターンに実装す
ることにより、第1の面実装部品と第2の面実装部品を
積み重ねて実装することができるので、実装密度を大き
くすることができる。
By mounting the first surface mounting component on the exposed inner layer wiring pattern and mounting the second surface mounting component on the surface wiring pattern so as to cover the first surface mounting component, Since the first surface mounting component and the second surface mounting component can be stacked and mounted, the mounting density can be increased.

【0006】[0006]

【実施例】以下に、この発明の一実施例を図1を用いて
説明する。図1は印刷配線基板を示す概略断面図であ
る。この図において、前記図2と同一符号のものは同効
のものを示す。12は切り欠きであり、表面の配線パタ
ーン7、8が設けられた基板2を部分的に切り欠いてい
る。この切り欠き12より基板3に設けられた内層配線
パターン13、14が露出されている。19は第1の面
実装部品、20は第2の面実装部品であり、前記切り欠
き12により露出された内層配線パターン13、14に
第1の面実装部品19を実装すると共に、第1の面実装
部品19を覆うように第2の面実装部品20が前記表面
の配線パターン7、8に実装されている。16はクリー
ム半田を示すものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a schematic sectional view showing a printed wiring board. In this figure, the same symbols as those in FIG. 2 have the same effect. Reference numeral 12 denotes a cutout, which partially cuts out the substrate 2 on which the surface wiring patterns 7 and 8 are provided. The inner layer wiring patterns 13 and 14 provided on the substrate 3 are exposed from the notches 12. Reference numeral 19 is a first surface mounting component, and 20 is a second surface mounting component. The first surface mounting component 19 is mounted on the inner layer wiring patterns 13 and 14 exposed by the cutouts 12 and the first surface mounting component 19 is mounted. A second surface mount component 20 is mounted on the surface wiring patterns 7 and 8 so as to cover the surface mount component 19. Reference numeral 16 denotes cream solder.

【0007】上記実施例では、切り欠き12として、基
板2に開口部を設けたものについて説明したが、切り欠
き12は基板2の縁部近傍を切り欠くものであってもよ
い。また、この切り欠き12を基板2、3に設けてもよ
い。
In the above-described embodiment, the cutout 12 is provided with the opening in the substrate 2, but the cutout 12 may be a cutout near the edge of the substrate 2. Further, the cutout 12 may be provided in the substrates 2 and 3.

【0008】[0008]

【発明の効果】この発明は以上説明したように構成され
ているため、前記露出された内層配線パターンに第1の
面実装部品を実装すると共に、第1の面実装部品を覆う
ように第2の面実装部品を前記表面の配線パターンに実
装することにより、第1の面実装部品と第2の面実装部
品を積み重ねて実装することができるので、実装密度を
大きくすることができる。
Since the present invention is configured as described above, the first surface mounting component is mounted on the exposed inner layer wiring pattern, and the second surface mounting component is covered with the second surface mounting component. By mounting the surface mounting component of (1) on the wiring pattern on the surface, the first surface mounting component and the second surface mounting component can be stacked and mounted, so that the mounting density can be increased.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例を示す印刷配線基板の概略
断面図である。
FIG. 1 is a schematic sectional view of a printed wiring board showing an embodiment of the present invention.

【図2】従来の印刷配線基板を例示する斜視図である。FIG. 2 is a perspective view illustrating a conventional printed wiring board.

【符号の説明】[Explanation of symbols]

2,3 基板 7,8 表面の配線パターン 12 切り欠き 13,14 内層配線パターン 16 クリーム半田 19 第1の面実装部品 20 第2の面実装部品 2, 3 Substrate 7, 8 Surface wiring pattern 12 Notch 13, 14 Inner layer wiring pattern 16 Cream solder 19 First surface mounting component 20 Second surface mounting component

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 二層以上の配線パターンを有する印刷配
線基板において、表面の配線パターンが設けられた基板
を部分的に切り欠いて内層配線パターンを露出せしめ、
この露出された内層配線パターンに第1の面実装部品を
実装すると共に、第1の面実装部品を覆うように第2の
面実装部品を前記表面の配線パターンに実装したことを
特徴とする印刷配線基板。
1. In a printed wiring board having a wiring pattern of two or more layers, the substrate on the surface of which the wiring pattern is provided is partially cut out to expose the inner layer wiring pattern,
The first surface mounting component is mounted on the exposed inner layer wiring pattern, and the second surface mounting component is mounted on the wiring pattern on the surface so as to cover the first surface mounting component. Wiring board.
JP6191167A 1994-07-21 1994-07-21 Printed wiring board Pending JPH07254766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6191167A JPH07254766A (en) 1994-07-21 1994-07-21 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6191167A JPH07254766A (en) 1994-07-21 1994-07-21 Printed wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3203352A Division JPH0529747A (en) 1991-07-19 1991-07-19 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH07254766A true JPH07254766A (en) 1995-10-03

Family

ID=16270020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6191167A Pending JPH07254766A (en) 1994-07-21 1994-07-21 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH07254766A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6178005A (en) * 1984-09-26 1986-04-21 株式会社村田製作所 Dielectric ceramic composition for high frequency
JPH02301183A (en) * 1989-05-15 1990-12-13 Toshiba Corp Manufacture of mounting type circuit component

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6178005A (en) * 1984-09-26 1986-04-21 株式会社村田製作所 Dielectric ceramic composition for high frequency
JPH02301183A (en) * 1989-05-15 1990-12-13 Toshiba Corp Manufacture of mounting type circuit component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same
US6324067B1 (en) 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same

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