JPH0536271A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To realize a semiconductor memory which inputs and outputs serial data having >=8 bits with single access without impairing its high speed performance. CONSTITUTION:The memory is provided with eight write-in amplifiers WA1-WA8, read-out amplifiers RA1-RA8 and data input/output lines IOb1-IOb8. The memory is also provided with a serial switching circuit SSW and a serial decoder SD which output serially the data in the data input/output lines IOb1-IOb8 to the outside successively and fetch the data from outside to the data input/output lines IOb1-IOb8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory capable of serial access.

[0002]

2. Description of the Related Art A conventional semiconductor memory such as DRAM is
There is a system that realizes a kind of serial access called nibble mode. First, the operation of this nibble mode will be described.

FIG. 4 shows the structure of a nibble mode semiconductor memory. This semiconductor memory has 16 memory cell arrays.
It is divided into blocks, and 4 blocks of them operate simultaneously. That is, one of the memory cell array blocks MCA1 to MCA4, MC
One of A5 to MCA8, one of MCA9 to MCA12, and one of MCA13 to MCA16 operate simultaneously, respectively.

From the memory cell array block, one first data input / output line IOai (i = 1 to 1) is provided.
6) is out. Memory cell array block MCA1 to
The data input / output to / from the MCA 16 is the data input / output line I.
This is done through Oai.

Each data input / output line IOai has four read amplifiers RAj (j = 1) through a switch circuit SWc.
~ 4) and write amplifier WAj. The switch circuit SWc connects the input / output data line IOai from the operating memory cell array block to the corresponding read amplifier RAj and write amplifier WAj.

The read amplifier RAj functions to amplify the data of IOai and send it to the data output circuit via the second data input / output line IObj during the data read operation from the memory cell array block. Write amplifier WAj
Serves to amplify the data supplied from the data input circuit and send the amplified data to the data input / output line IOai during the data write operation to the memory cell array block. The above is
This is a function that ordinary semiconductor memories also have,
In addition to this, in the nibble mode, the nibble switch circuit NS
The feature is that W and a nibble decoder ND are attached.

The nibble switch circuit NSW is a changeover switch circuit for continuously transferring all four data appearing on the data input / output line IObj during a read operation, for example. The signal for this switching is an address signal generated by the nibble decoder ND. Temporarily, the data input / output line I
If the address that distinguishes the data of Obj is (Xk, Yk), the nibble decoder ND determines that this address (Xk, Yk).
Yk) is received as a start address, and hereinafter, including the received start address, (Xk, Yk) = (0,
Addresses 0), (0, 1), (1, 0), and (1, 1) are successively generated one after another. This nibble switch circuit N
The nibble mode semiconductor memory can serially access 4-bit data by using the SW and the nibble decoder ND.

FIG. 5 is a waveform diagram showing the operation timing of this semiconductor memory. There is no signal dedicated to the nibble mode, and FIG. 5 shows a row address strobe signal RAS and a column address strobe signal C which are usually used in a DRAM or the like.
AS, address signal AD, write enable signal WE,
The relationship of the data output DO is shown.

After the row address strobe signal RAS falls, the addresses are first fetched in X and then in Y. When the column address strobe signal CAS falls, the data output circuit is activated and DO is output. Up to this point, the operation is the same as that of the random access mode DRAM.

After this, the row address strobe signal R
While AS is kept at a low level, the column address strobe signal CAS is toggled as shown in FIG. 5 to start from the previously fetched X and Y addresses, and 4-bit data of different addresses determined by Xk and Yk. Access continuously.

The above is the outline of the operation of the nibble mode semiconductor memory. In this nibble mode, the operation of returning the row address strobe signal RAS to the high level once and then to the low level again for the second and subsequent data is not necessary, and therefore the continuous 4-bit data access is performed at high speed. it can.

In the nibble mode, since the semiconductor memory has a bit width of 4 bits such as 256 K words × 4 bits, it is possible to simultaneously access 4-bit data inside the semiconductor memory. By utilizing this, when the bit width is 1 bit such as 1 M words × 1 bit, the above 4-bit data can be continuously input / output.

[0013]

However, in the conventional nibble mode semiconductor memory, as described above,
The length of serially accessible data is limited to 4 bits, which has been a limitation in application of this semiconductor memory.

An object of the present invention is to solve the above problems and to provide a semiconductor memory in which the length of data that can be serially accessed is increased while taking advantage of the high speed access in the nibble mode.

[0015]

A semiconductor memory according to the present invention writes data to a designated address and reads stored data from the designated address.
M (M is an integer of 4 or more) memory cell array blocks, and 2N (N is an integer of 4 or more, N ≦ M, the same applies hereinafter) write amplifiers for amplifying write data of these memory cell array blocks, 2N read amplifiers for amplifying the data read from the memory cell array block, and 2N of the 2M memory cell array blocks are selected to select the selected memory cell array block, the write amplifiers, and the read amplifiers. And a serial data input / output circuit for sequentially supplying write data to be serially input to the write amplifiers and serially outputting data from the read amplifiers. have.

[0016]

According to the present invention, the number of data input / output lines drawn from the memory cell array block is increased, and at the time of reading, the data on the data input / output lines that have been read in parallel are collectively output. On the other hand, at the time of writing, first, the data from the outside is sequentially taken in, and then the data is collectively written in the corresponding memory cell array block. By doing so, serial access with a longer data length becomes possible as compared with the conventional nibble mode semiconductor memory.

[0017]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In this embodiment, like the conventional semiconductor memory of FIG. 4, the entire memory cell array is divided into 16 blocks,
It adopts a method in which four blocks of them operate simultaneously.

Each memory cell array block MCA1 to M
From CA16 to the first data input / output line IOam (m = 1 to 1
32) is out. Different from FIG. 4, two data input / output lines are formed from each of the memory cell array blocks MCA1 to MCA16. This is because the number of second data input / output lines IObn described later is eight.

A switch circuit S for selecting the data input / output line IOam from the operating memory cell array block.
Through W, there are a read amplifier RAn (n = 1 to 8) and a write amplifier WAn. A second data input / output line IObn is output from the read amplifier RAn and the write amplifier WAn. The function of each component described above is almost the same as that of FIG.

Here, since the data of the eight data input / output lines IObn are continuously input / output, the data input / output line IO
A serial switch circuit SSW connected to b is provided.

Further, there is provided a serial decoder SD which generates a signal for selecting which data input / output line IObn data is input / output. These correspond to the nibble switch circuit NSW and the nibble decoder ND in FIG. In this case, by using eight data input / output lines IObn,
8 consecutive data can be accessed.

In the recent megabit class DRAM,
In order to reduce the test time, IEICE Transactions C, Vol. J70-C, No. 10, 1391-13
It is equipped with the multi-bit test function described on page 98. With this function, the inside of the semiconductor memory is usually divided into a plurality of blocks, and data can be input / output simultaneously for each block. Currently, the number of divisions is about 8 to 32. By using this function in combination with the present invention, it is possible to minimize the overhead of the control circuit or the like required for the divided operation inside the semiconductor memory. Under such circumstances, the length of data that can be serially accessed in the present invention is about 8 to 32, which is suitable for the number of divided memory cell arrays for a multi-bit test. Absent.

FIG. 2 is a block diagram showing a second embodiment of the present invention. In this embodiment, the serial switch circuit S as in the first embodiment is used for controlling serial data input / output.
Instead of using the SW and the serial decoder SD, a register RG that stores the data of each data input / output line IObn
1 to RG8 are provided, and these registers RG1 to RV8 are connected in cascade to sequentially shift data as a shift register SR and input / output serial data.

As described above, by using the shift register SR, the system shown in FIG. 3 can be adopted.

In the third embodiment, the shift register is divided into two groups of shift registers SRa and SRb, and the other constituent elements are also divided into two groups. For example, the shift register SRa uses a switching circuit SX to transfer data to and from the outside. While the input / output is being performed, the shift register SRb causes the read amplifier RAn (during reading) or the write amplifier WAn to operate.
During writing (during writing), data is exchanged with the memory cell array block via the switch circuit SWD and the data input / output circuit IOam, and when the shift register SRb inputs / outputs data to / from the outside, the shift register SRa
The so-called interleaving operation of exchanging data with the memory cell array block becomes possible. By doing so, it becomes possible to serially access data of any length within the same X address.

[0027]

As described above, according to the present invention, 4
The nibble mode memory access method, which has been limited to bits, can be expanded to a long bit width of 8 bits or more, which has the effect of expanding the application range of this type of semiconductor memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional semiconductor memory.

5 is a timing waveform chart of signals of respective parts for explaining the operation of the semiconductor memory shown in FIG.

[Explanation of symbols]

MCA1 to MCA16 memory cell array block IOa1 to IOa32 First data input / output line IOb1 to IOb8 Second data input / output line SW, SWa-SWc switch circuit RA1 to RA8 readout amplifier WA1 to WA8 write amplifier SSW serial switch circuit SD serial decoder SR, SRa, SRb shift register RG1 to RG8 registers SX switching circuit NSW nibble switch circuit ND nibble decoder

Claims (3)

[Claims] 1. A memory cell array block of 2M (M is an integer of 4 or more) for writing data to a specified address and reading data stored from the specified address, and writing to these memory cell array blocks. 2N (N is an integer of 4 or more and N
≤M, the same applies hereinafter), 2N read amplifiers for amplifying data read from the memory cell array block, and 2N of the 2M memory cell array blocks are selected to select the selected memory. A switch circuit that connects the cell array block to each of the write amplifiers and the read amplifiers, respectively, and serially input write data to each write amplifier, and to sequentially supply data from each read amplifier. A semiconductor memory having a serial data input / output circuit for sequentially outputting serially. 2. A serial data input / output circuit is configured to include a shift register having 2N registers, and serially input write data is sequentially taken into the registers and supplied to each write amplifier, 2. The semiconductor memory according to claim 1, wherein the semiconductor memory is a circuit for fetching data from each read amplifier into each corresponding register and sequentially shifting and outputting the serial data. 3. 2M memory cell array blocks, 2
Each of the N write amplifiers, the read amplifiers, and the registers is divided into two groups, and one of these two groups is caused to perform a predetermined operation in a series of write operations and read operations, and the other is subjected to the series of write operations. 2. The semiconductor memory according to claim 1, wherein an operation different from a predetermined operation among the operation and the read operation is executed.