JP2932790B2 - Dynamic random access memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a technology for increasing a data rate.

[0002]

2. Description of the Related Art A conventional dynamic random access memory device (hereinafter referred to as a DRAM) is provided with a serially accessed page operation by limiting addresses that can be continuously accessed in order to increase the data rate. A two-stage pipeline operation for simultaneously executing address latch and data output is adopted.

[0003]

However, a motion detection memory for moving image compression / decompression (hereinafter, referred to as an MPEG memory) is provided under three types of specified access procedures.
Since a data rate that is four times or more the current data rate is required, there has been a problem that the high-speed technology employed in the conventional DRAM is insufficient.

On the other hand, the use of a high-speed static RAM for an MPEG memory has a shortage of storage capacity, and the static RAM is a DRAM in terms of cost performance.
There was a problem that it was inferior.

[0005]

A first gist of the present invention is to provide a four-stage pipe in a memory used for MPEG processing.
Divided into 16 or more blocks when accessing the line
A memory cell array and a four-stage
Means for performing an pipeline operation.
Write the written image pixels to any of the MPEG specifications
That is, pipeline reading is also performed in the output order .

A second gist of the present invention resides in that 16 memory cell sub-arrays, a plurality of address registers for supplying addresses to the respective memory cell sub-arrays, and a plurality of leads for transmitting / receiving data to / from each memory cell sub-array. A write amplifier, a data input / output unit provided between the read / write amplifier and the data input / output terminal, and a control signal generation circuit for generating a series of control signals in synchronization with a clock signal; The signal is a latch of an address signal into an address register, a balance of a digit line of a memory cell sub-block specified by the address signal, and a supplied read of data read from the memory cell sub-block specified by the address signal.・ Activation of write amplifier and input / output of data supplied from read / write amplifier The output from unit is to control in a pipelined manner.

[0007]

The control signal latches the address signal and outputs 4
One memory cell sub-block in order,
Pipeline control of digit line balance, sensing operation, and data output.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a block diagram showing a first embodiment of the present invention. The memory cell array 1 includes 16 sub-arrays A to P, each of which is connected to an address register 3 and a write / read amplifier 4. A control signal generating circuit 6 to which a clock signal is supplied from a clock input 5 forms a series of control signals to enable pipeline control. The control signal is address input 7
From the transfer to the address register 3 to the input of data via the input / output buffer 8.

By the way, the access means of the MPEG memory specifies an area having 16 × 16 pixels as one unit in three patterns shown in FIG. That is, in the first pattern 21, each row shifts from the leftmost pixel to the rightmost pixel, in the second pattern 22, the pixel is designated while being folded, and in the third pattern 23, the pixel is designated while being folded in an oblique direction. ing. On the other hand, as shown in FIG. 3, data of 4.times.4 = 16 pixels are allocated on the memory cell array 1 to each of the four separate sub-arrays A to P, thereby enabling a four-stage pipeline operation.

Next, a four-stage pipeline operation of this embodiment will be described with reference to FIGS. 4 and 5, taking a read operation as an example.

At time t1, row address strobe signal RA
Lower S (overline) and latch row address X.
From time t2 to time t5, the column address strobe signal CAS (over line) is lowered, and the column addresses YA, YB, Y
When C and YD are sequentially latched in the address register 3, data (X, YA) (X, YB) (X, YC) (X, Y
D) is read from the sub-arrays A to D, and the data rate can be increased.

That is, as shown in FIG. 5, the operation of each of the four stages is as follows: (1) address latch, decoder operation (2) digit line balance (3) data sense latch (4) output for four sub-arrays A to D Will repeat.
Also, a page operation is performed for speeding up, and the four-stage operation is performed in synchronism with CAS (overline). For example, when t = T in FIG. 5, data of the subarray A is output, data of the subarray B is latched by the sense amplifier, digit lines of the subarray C are balanced, addresses of the subarray D are latched, and a decoder operation is performed. You are doing.

However, if the same subarray is accessed at different stages during the four-stage pipeline operation, a problem occurs. Therefore, a detection circuit for detecting an inconvenient access may be provided. For example, when the address input for selecting the sub-array A is latched again at the timing t = T in FIG. 5, the address latch and the decoding are performed for the sub-array A regardless of the data output from the sub-array A. Become. In order to detect the occurrence of such a problem, an address input in synchronization with the column address strobe signal CAS (over line) is compared with an address input in synchronization with the preceding three clocks, and the same sub-array is compared. Can be realized by determining whether or not is selected.

More specifically, as shown in FIG. 6, the address fetched by the address input buffer 10 is sequentially latched by the shift register 11 in synchronization with the column address strobe signal CAS (over-line), and is output by the preceding three clocks. Is compared with the latest address by the address comparison circuit 12. The comparison result is input to the OR circuit 13, and the output of the OR circuit is output as the mismatch output signal 14.

[0015]

As described above, the present invention provides an MPEG
Under the access means peculiar to the memory, the page operation can be realized as a four-stage pipeline, and the current page operation can be performed in four stages.
Double the speed can be realized. Therefore, the dynamic RAM having this function is excellent in terms of increase in capacity and cost performance, and has an effect that the applicable range of the dynamic RAM can be expanded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing access means of an MPEG memory.

FIG. 3 is a diagram showing allocation of subarrays according to the first embodiment.

FIG. 4 is a timing chart showing the operation of the first embodiment.

FIG. 5 is a diagram showing a time-series change of the operation content of each sub-array at the timing of FIG. 4;

FIG. 6 is a block diagram showing a mismatch signal generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell array 3 Address register 4 Write / read amplifier 5 Clock input 6 Control signal generation circuit 7 Address input 8 I / O buffer 9 Data input / output 10 Address input buffer 11 Shift register 12 Address comparison circuit 13 OR circuit 14 Mismatch output signal

Claims (3)

(57) [Claims] 1. A memory used for MPEG processing,
When accessing a 4-stage pipeline, 16 or more blocks
Memory cell array divided into
Means for operating the pipeline in four stages,
Image pixels written to the array
A dynamic random access memory device which performs pipeline reading in such a reading order . 2. A memory system comprising: 16 memory cell sub-arrays; a plurality of address registers for supplying addresses to the respective memory cell sub-arrays; a plurality of read / write amplifiers for transmitting / receiving data to / from each memory cell sub-array; A data input / output unit provided between the data input / output terminal and a data input / output terminal; and a control signal generating circuit for generating a series of control signals in synchronization with a clock signal. Latch, the digit line balance of the memory cell sub-block specified by the address signal, and the activation of the read / write amplifier supplied with the data read from the memory cell sub-block specified by the address signal. The output from the data input / output unit of the data supplied from the read / write amplifier. 2. The control method according to claim 1,
A dynamic random access memory device according to claim 1. 3. The memory block being processed during pipeline processing.
Means for storing an address, the address and the address
Means for comparing with the address supplied to the register.
When the comparing means detects a match between the two addresses,
3. The dynamic random access memory device according to claim 2, wherein said comparing means outputs a coincidence signal .