JPS581891A - Monolithic storage device - Google Patents

Abstract

PURPOSE:To decrease the access time, by dividing a memory cell array into blocks and setting a parallel-series converting circuit to deliver the output in series from each block. CONSTITUTION:A memory array 100 is divided into blocks 100-1-100-4. An address buffer circuit 4CA produces the internal address signals 14CA and 14CA' in the rise mode of an address buffer control signal 12 which is generated in response to a column selection control clock signal 1C. In response to these internal address signals, a bit line selecting circuit 5CA selects a bit line pair with each blocks 100-1-100-4 and feeds the signal to the data line pairs I/01- 4. These signals are supplied to a selecting circuit 201 respectively. On the other hand, a decoder 5ZS selects a line Z1 in accordance with the output of an address buffer 4C's. Then the output of a circuit 6C1 is selected and supplied to an output amplifying circuit 7CS to be delivered to a terminal 8. When the operation of a circuit 7CS is over, the next column address is supplied via a line 3 to repeat the same operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to monolithic memories such as MO8 dynamic memories.

Figure 1 shows how the address signal is divided into two parts: a row address and a column address.
A so-called address multiplex method is adopted in which these signals are time-divisionally input through the same input terminal, and a page mode is adopted in which only the column address is continuously changed while the row address is fixed. 1 shows a schematic circuit configuration of a dynamic memory using a conventional N-type MO8) transistor having a function of FIG. 1st
In the figure and other drawings, reference symbols with suffixes R and C are attached to circuit portions related to row selection and column selection operations, respectively. IR, IC is 18116 from outside
The former mainly controls the start of the row selection operation, and the latter mainly controls the start of the column selection operation. 2C and 2C are circuits that receive inputs from the IR and IC, respectively, and generate a plurality of timing pulses necessary for operation inside the memory. In the figure, only the representative outputs 11R, 12R, 13L and 12C are shown, and the others are omitted.The 0 circuit 2C is the signal 11R.
It responds to the signal IC only under the condition where is input. 3
consists of a plurality of rounded signal lines that input row or column addresses consisting of a plurality of bits in parallel.

Address buffer circuits 4R and 4 (address buffer control signal 1 supplied from circuits 2R and 2C respectively for the row address and column address input in a time-sharing manner via jlla
2R and 12C, and output an internal row address signal 14R and its inverted signal 14 and an internal column address signal 14C and its inverted signal 14C, respectively. 14 signals.

14R is a row decoder (not shown), word lines Wt to W,
The signal is supplied to a word line selection circuit 5R consisting of a drive circuit (not shown), etc., and the other signal 14C.

14C is supplied to a bit line selection circuit 5c comprising a column decoder (not shown) and a drive circuit (not shown) for bit line selection line Yl=Y-. 100 is a part of the memory cell array, so-called folding bit, lil (p
old bit 1ine) It has a pair of bit lines Bl to Bm, and a memory cell MC made of a 1MO8 transistor is arranged at one of two intersections between each of the pairs of bit lines Bl to B and the word line Wl-W. ing. Each bit line is also connected to a Dan cell (not shown). This is a detection circuit for a minute signal from the 6RFi memory cell MC, and is composed of transistors fi Qlm Q*, and operates according to the instructions of the detection circuit drive signal 13 supplied from the circuit 2RK. The gate circuit 101 has a pair of MOS (MOS) transistors provided for each data line pair, and connects the bit line pair corresponding to the input/output data line pair I10 to MYt"Y@
60 is a detection circuit, 7C is an output amplification circuit, and 8 is an output terminal. 9 is a data input terminal, and 10 is a data capuffer. In addition,
Each circuit in FIG. 1 is of a dynamic type. Hereinafter, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG. 2.

First, when the row selection control clock IR becomes low level, 12B clocks among the plurality of internal clocks necessary for internal operations are generated by the circuit 2R, and inputted via line 3 in synchronization with the falling edge of signal 1. A circuit 4 takes in the column address 1 and generates internal address signals 14 and 14R. Since this memory operates in a multi-address system, only the row address ■ is first input to line 3. 6 CEP-CI>...◎ in FIG. 2 is a column address that will be input later.

The circuit 5R operates in response to the internal address signal 14, rll, and the word line WI=W, 01, for example, Wl, is selected. In this way, a plurality of memory cells connected to the selected word line W1 are read out. Each bit line is provided with a dummy cell (not shown), and the circuit 5R reads out the dummy cell connected to the bit line that is paired with the bit line to which the four selected memory cells are connected. In this way, minute signals are read out onto the %n bit line pairs. After that, the signal 13R becomes a low potential, each detection circuit 6 operates, and the voltage of each data line pair is differentially amplified. With this operation, the row selection operation is generally completed.

When the column selection control clock IC then traps low, circuit 2C generates signal 12C. Note that the signal 11R is an inverted signal of the signal IR, and the circuit 2C is configured such that the fall of the signal IC responds to seconds only when the signal 11R is at a high level. The circuit 2d responds regardless of the level of . The fall of the signal IC is synchronized with seconds, and the circuit 4C takes in the column address O input via the line 3 in response to the signal 12C, and generates internal address signals 14C and 14C1-. Signal 14C, 14C
In response to KZ, one of the bit line selection lines Ys''Y-, for example Yl, is selected by the circuit 5C.
OS) The transistor QseQ4 is turned on, and the signal on the data line pair Bs is transferred to the input/output data line pair l10K, where it is differentially amplified by the detection circuit 6C, and its output is further amplified by the output amplifier circuit 70, and output. Read data to terminal 8■
is output.

In the normal mode, both signals IR and IC are then returned to high potential, and the memory returns to its original standby state. At this time, the memory signal takes the level shown by the dotted line in FIG.

That is, the circuit 2R is a circuit that supplies a signal to the circuits related to the row selection operation, such as 4R15R, 6R, and the cell array part 100, to put them in the standby state II (that is, the precharge state 0) when the signal IR becomes high level. (
(not shown).

On the other hand, the circuit 2C is a circuit involved in column selection operation when the signal IC becomes high level, for example, the circuit 4C.

It has a circuit (not shown) for supplying a round signal to precharge each of 5C, 6C, 7C, IOC, and data line pair 10 and put them in a standby state.

On the other hand, in the page mode operation, after the output appears at the output terminal 8, the signal l remains at a low potential state and only the signal IC is turned on and off, as shown by the solid line in FIG. Only column selection operations are performed continuously.

In this page mode, one signal is in a low level state, so the circuit related to the row selection operation is in the previous state, that is,
In this example, word line W1 is selected, so the signal IC
For example, when becomes a high potential state.

For example, only the circuits related to the column selection operation, such as circuits 2C, 40, 5C, 6G, and 70, enter a standby state from a predetermined tie ζ blow and prepare for the L-th operation. When the signal IC then goes low, circuits 2C and 4C operate in the same manner as described before, and circuit 4C receives the next column address O input via line 3.
The 0 circuit 5C that takes in the signals 140 and 140 and supplies the signals 140 and 140 to the circuit 5CK selects one of the bit line pair selection lines Y1 to Y corresponding to the signals 140 and 140, and selects the corresponding bit line. The paired signals are transferred to the input/output data line pair l10K, and the data is output to the output terminal 8 via the circuit 7C. After that, the same operation continues and the column address O1O
. . . Nine data corresponding to the QK force are continuously output to the terminal 8. Page 7, - With the end of the code, the signal IC,
Both IBs are returned to high level, and the memory is returned to its original standby state. As mentioned above, in page mode, the row selection operation is not repeated repeatedly, so 1. faster operation than normal is possible; The access time is equal to the time from column address input to data output, 1 cm, and this time teA is approximately 1 to - - of the access time (time from row address input to data output) 1 mi during normal operation. ! The maximum number of data j that can be continuously read in page mode is, in principle, the number of bit line pairs that can be specified by the column address, assuming that data from memory cells with different addresses are to be read under normal pressure. 0 equal to n Normally, in a multi-address memory, the number n of bit line pairs and the number m of word lines are made equal, so if the storage capacity of the entire memory is N, it becomes j-8. This value is a theoretical value and may be changed as appropriate in relation to other characteristics, but it is usually in the range of tens to hundreds of j - in page mode, different data of this quantity are successively displayed as above. It can be read in an access time of

However, K used as the main memory of the four child computers has a slow access speed even in the page mode described above.

An object of the present invention is to provide a memory that can operate in a mode with an even shorter access time than the conventional page mode.For this reason, in the present invention, the memory cell array is divided into blocks, and for each block, An input/output data line is provided, and a selection circuit is provided to send the output from each block to the input/output data line corresponding to each block in response to the same column address, and the signal on the input/output data line is output in series. A parallel-to-serial conversion circuit was provided.

The present invention will now be illustrated in detail with reference to Examples.

(1) Continuous mode In FIG. 3, the same reference numerals as in FIG. 1 indicate the same components as in FIG. 1. The memory cell array 100 is the first
In this embodiment, which consists of an array of memory cells having the same structure as that shown in the figure, four input/output data lines, pairs I10--I10-, are provided, and the cell array is partially selected during column selection operation. Because of C, the cell array 100 is divided into fourth blocks 100--100-- and each block has the same right-weight bit line pair. Block j (l≦j≦4
) bit line pairs are represented by numbers B■1 to BQ)i, and the column addresses of -33 (ik (l≦≦i) are the same except for the lower two bits. It is attached.

In this embodiment as well, the address 1 multiplex method is used as in FIG.

The address buffer circuit 4CA takes in only the upper bits other than the lower two bits of the column address input via @3, and the internal column address signal 14 corresponding to these bits is taken in.
This circuit differs from the circuit 4c in FIG. 1 in that it outputs CA and its inverted signal 14-0A.

Along with this, the 1 selection circuit 5CAri is different from the 11g bit @ selection circuit in that it responds to the internal address signals 14A and 14CA. Note that, for the sake of simplicity, a signal line connecting the bit NJ selection circuit 5CA and the gate circuit 101 is not shown.

Further, detection circuits 6C■ to 6C■ are provided connected to the four data line pairs I10■ to I10■, and furthermore, a circuit 201 for selecting these outputs, a circuit 5zs for 1tilUtl, and a circuit 5Z8 for selecting the outputs of these circuits. A buffer 4C'8 for giving an address to select the circuit 5ZS for the circuit 7C8 for amplification, a circuit 20' for generating a pulse to start this, a circuit 203 for selecting write data, and a write data buffer 10C8 are provided. The memory of FIG. 3 differs from that of FIG. 1 in that the memory shown in FIG.

The 8% selection circuit SZS and the output amplification circuit 7C8 are constituted by static type circuits, and the respective circuit configurations are shown in FIGS. 4A to 4C.

Buffer 1ocs is also of static type. Circuits other than these are dynamic types.

9. Since the output widening type circuit 7c shown in Fig. 1 is a dynamic type, a signal is sent to the circuit 2CFi and the circuit 70 to precharge it and put it in a standby state every time the signal 1'C becomes high level. It had a supply circuit (not shown). In FIG. 3, since the output amplifying circuit 7C8Fi is a static type, there is no need to supply this signal from the circuit 2CA to the circuit 7C8, and the only difference from the circuit 2C in FIG. 1 is that it does not have this supply circuit.

The circuit 2C' outputs the signal I every time the level of the signal IC is inverted.
This circuit outputs an inverted signal 12C' of C.

In addition, in Figure 3,! The detection circuit 6R in figure s1 is
However, this is not shown for simplicity and is assumed to be included within memory cell array portion 100.

The operation of the embodiment will be described below with reference to FIG.

In response to signal IR, a row selection operation is performed based on row address [F] in exactly the same manner as in FIG. Then signal I
In response to C, a column selection operation based on column address O is performed.

Almost synchronously with the falling edge of the signal IC, or
Column address O is input to ls3 before the fall of , and is input to buffer 4CA. Buffer 4CA receives signal I
At the rising edge of the signal 12C generated in response to the signal 12C, the upper bits of this address () other than the lower 2 bits are taken in, internal address signals 14CA and 14CAt are generated, and then the signal IC becomes high level and the buffer 4CA A change in the address on line 3 will not change the output until such time as is precharged.

The 50 bit line selection circuits use this internal address signal 14C.
A, 14CA, one bit line pair for each block 100■-■, e.g., B■1°B■1. B■1.
The gate circuit 101 is controlled to simultaneously select B.sub.1, and a signal is sent to the data line pairs I10.about.I10. These signals are differentially amplified by detection circuits 6C--6C-, respectively, and supplied to a selection circuit 201 consisting of a MOS transistor Qs=Q-. 2C' is a circuit that generates a plurality of timing pulses in response to the signal ICK for operation according to the present invention (hereinafter referred to as continuous mode operation). Only the signal 120' is shown, and the others are omitted. Address buffer 4C'8 outputs internal address signal 14C' and its inverted signal 140' in response to the lowest two bits of column address O input via @3 when signal 12C' is at high level. The circuit consists of a static type circuit.

Figure 4A is an example of the part related to 1 address bit in the address buffer 4C'S, in which Qtt* Q14 is driven by MO8) transistor, Qt + Qts is loaded by MO8).
It is a two-stage inverter circuit using transistors.

Signal 140' is a 1-bit non-inverted signal of the address input to line 3, and 14C' is an inverted signal of this address. Here, the gates of the load transistors Q1 and Qts are controlled by the signal 120' when the signal IC is not input, that is, in the standby state, these loads MO
8) This is to turn off the transistor and reduce power consumption.

The portion of the buffer 40' relating to the other one bit of the column address is constructed in exactly the same manner. In addition, buffer 4C'
Although 8 is a static type circuit, it starts operating from the time when the signal 120' becomes a high potential, so that the lower two bits of the first column address O are taken in in synchronization with the signal 120'. When the signal 120' is held at a high potential and in the 9 state, the output 14C is output after a circuit-specific delay time (1 to several naec) in response to a change in the address input from line 3.
, 14C changes.

The decoder 5zS responds to the output of the buffer 4C'8 by
One of IIz■ to Z■ is selected. Here, the case where Z■ is selected according to the address QK is exemplified. Figure 4B shows the part of the decoder 5zS that selects the output line 2■, and the transistor A NOR circuit is configured for the lower 9112 bits of the column address input to the gate of Q ■・Q t s, and when the internal input is in a low potential state, the load transistor Ql? Since the 0 line circuit that outputs a high potential via is also a static type, the signal 120
When ' is at a high level, the output changes immediately in response to a change in the level of the input address.

A portion of the decoder 5Z8 that selects the output line Z■ is similarly configured. In the fourth BIW, the load transistor Q
The reason why the gate of ty is controlled by signal 12C' is the same as in the case of FIG. 4A.

When No. 1 of the data line pairs I10■ to I10■ is differentially amplified by the detection circuits 6C■ to 6C■, respectively,
Decoder 5Z8 already has #il corresponding to column address 0.
Z■ is selected, and the output of circuit 6C■ is selected by transistor Qs (MO8) and supplied to output amplification circuit 7C8 via line 202t-.

As shown in Figure 1J4c, the output amplifier circuit 708
The 0-line circuit, which is composed of an inverter circuit consisting of an S transistor Qtss Qt and a push-pull circuit consisting of a Q*oa Qts, is also a static type, and after a certain delay time, the signal on line 202 is transferred to terminal 8. Output to. Signal 12C' is applied to load transistor QI- for the same reason as in FIG. 4A.

In this way, as in the conventional case, after the signal IR or IC becomes low level, the IR mode is activated.

After the IBO time has elapsed, the first data {circle around (2)} corresponding to addresses [F] and O are output to terminal 8.

Thereafter, the signals IR and IC are maintained at a low potential, and the memory maintains its original operating state. Therefore, data line pair I1
Four data read from the four blocks of the memory are held in 0■ to I10■, and the detection circuits 6C■ to 6C also output signals obtained by amplifying these four data.

The next column address O is input via the line 3 at the timing when the operation of the output amplification circuit 7C8 is completed and the data ■ is output. This column address O differs from column address O only in its lower two bits. Outputs 14C', 14C' of circuit 4C'8 in response to the lower two bits of address O
changes, and the 1 circuit 528 selects the output line corresponding to the lower two bits of the address O, for example, 2. This turns on the transistor Q-, and the contents of the detection circuit 6C-- are outputted to the terminal 8 through the output amplification circuit 708 as data . Thereafter, the column address O9O is input every time the operation of the output amplification circuit 708 is completed, and the same operation is repeated to sequentially output the corresponding data (1) and (2). During this time, the signal 12Ct'i remains high V pel, so the address O
Buffer 4CA does not read the upper bits of ~(), and its outputs 14CA and 14CA remain as those for address 0. Therefore, for Jin, the upper bits of address O~() are #! Therefore, in FIG. 5, the signal #J3J: is shown assuming that the upper bits of addresses () to () are not input.

After this continuous mode ends, the signal IC11 is returned to a high level and the memory returns to the standby state. That is, static type circuits 4C'8.5Z8.7C8Fi become deaf due to the input signal 120' to them going low. Each of the other dynamic type circuits in the memory
According to the embodiments described above, the access time in continuous mode, i.e., the second and subsequent column addresses 0 to
The time tglm from inputting 0 to outputting data 2 to 2 is determined by the operating speed of the circuit 4C'8.5Z8゜7C8, and moreover, these circuits are dyna Unlike the Tsuk type circuit, it is a static type that does not require precharging, allowing for high-speed continuous operation of 5 seconds, which is extremely small compared to the page mode access time of conventional memory (tcm). Become. In addition, this high-speed operation cycle time t gle is also approximately the same as the access time tglA, and is shorter by 1 to IK than in the prior art.

5. The read operation has been described above, but as shown in FIG. , through the selection circuit 203 controlled by the circuit 5Z8, the data line pairs I10■ to I
A pair of differential write data is continuously supplied to 10■,
High-speed continuous writing is performed.

(2) 51 more than the combination mode of continuous mode and page mode! In the example, four or more different data are read/
When writing i1t, four data are handled in continuous mode, and then the signals IR and IC are processed as shown in Figure 5.
It is necessary to return the power supply to the high state, return all circuits to the standby state, and restart continuous mode operation. Therefore, since the continuous mode is only executed intermittently, there is room for further improvement in the speed at which data is read at multiple ends. Several embodiments capable of continuous mode operation with multiple data will be described below. FIG. 6 shows an embodiment of a memory operating in a mode that combines continuous mode and page mode, and in FIG. 6, the same reference numbers as in FIG. In this case, parts related to data writing are not shown for the sake of simplicity.

Figure 6 differs from Figure 3 mainly in the following points.

MO8) for disconnection transistor Q 1 ? ~ Q14 and a dyna (tsuku type latch circuit 6C) that temporarily stores data
A circuit 2C'A is provided in place of the circuit 2C' in the circuit shown in FIG.

Various configurations can be considered for the latch circuits 6C'' to 6C'', examples of which will be explained later with reference to FIG. 13.

Circuit 2C'A is similar to circuit 2 in FIG. 3 in that it outputs its inverted signal 12C' in response to the first falling edge of signal IC.
It is the same as circuit 2C', but differs from circuit 2C' in FIG. 3 in that it does not respond to subsequent changes in the level of signal IC while signal 11 is at a high level.

Furthermore, the circuit 2C'AFi differs from the circuit 2C' shown in FIG. 3 in that it outputs a signal 15C which becomes high level after a predetermined period has elapsed after the fall of the signal IC.

Transistor Q - Q 14 is the detection circuit 6C - 6C
After the detection data of ■ is captured in the latch circuit 6C■"~6C■", it is turned off under the control of the signal 15C, and the function is to disconnect the latch circuit 6C■"~6C■" from the detection circuit 6C■~6C■. have

The operation of the memory shown in FIG. 6 will be explained with reference to FIG.

Data line pair I by address O after the first set of addresses
The operation until the data is read out to I10■ to I10■ is the same as the embodiment shown in FIG.

Detection circuit/6C■~6C■Fi corresponding data line pair I1
The voltages from 0■ to ■ are differentially amplified, and a pair of signals t? of different levels are generated according to the amplification result. Output as detection data.

At the point when the differential amplification operation by the detection circuits 6C■ to 6C■ is completed, the signal 15C becomes a high potential state, and the latch circuits 6C■" to 6C■" are connected to the detection circuits 6C■ to 6C■ through the transistors Qsy to Q ports. It is latched into a state corresponding to a pair of signals output from each of 6C■. Latch circuit 6C■“~
One of the outputs of 6C■'', for example, the output of 6C■'' is selected by a selection circuit responsive to address 0, and outputted from output amplification circuit 708 as data ■. After this, line 3
By sequentially changing the column address inputted through the address 0 to address 0, the continuous mode is predicted based on the output of the latch circuit 6C.

In this embodiment, in order to start the page mode operation in parallel with this continuous mode operation, the latch circuit M6C■"~6
After completion of the latching operation to C■", the signal IC is set to a high potential state. As a result, the signal 15C is returned to the original low potential by the circuit 2C'A, and the latch circuit is turned off by turning off the transistors Ql? to Q14. 6C■"~6C■" is disconnected from the detection circuits 6C■~6C■, and at the same time, as in the case of the conventional page mode, the circuits related to the column selection operation are activated by the circuit 2CA in response to the high level of the signal IC. That is, the 40 buffers, the bit line selection circuit 5CA, the data line pairs I10--I10, and the detection circuits 6C--I are returned to the memory standby state.

When the return operation of this column selection circuit is started, the output amplification circuit 7C8 outputs the data ■ and the data is sent via the line 3 at the 9th timing in order to perform continuous mode operation regarding the address QVc regardless of this return operation. Enter the next column address C2. 9, so you only need to input the lower 2 bits of address 0. This is because buffer 4CA is in a standby state as signal ICO goes up, and does not respond to the address on line 3. . Therefore, address O
It is not necessary to input the upper bits of , as will be explained later. This also applies when inputting 1 and subsequent column addresses Q, (0, and as a result, the upper bits of each of addresses () to () It is only necessary to input the upper bits of the internal address (p), so that circuit 2C'A
maintains the signal 12C' at a high level while the signal 11R is at a low level even if the signal IC returns to a high level.

In this way, in parallel with the return operation of the column selection circuit, a continuous mode operation is performed based on the lower two bits of address C2, and data 2 is read out. Assuming that the return operation of the circuit related to the column selection operation is completed at the time when the output amplification circuit 7C8 outputs data ■ and starts continuous mode operation based on address (), the next column selection will be made to the friend from the point of %. At this point, the signal IC starts to take in the first address e of the low voltage again, which is dangerous. It is necessary to import address O at the same time.Since only the lower 2 bits of the column address need to be used for continuous mode operation, the lower 1m2 bits of σ) are transferred to the address via the lower two bits of %a3. is sent from the outside, and the upper bits other than the lower 112 bits of address e are input through the remaining lines of s3. ゛When the continuous operation using the lower 12 bits of address O is completed, the same applies to address C) IK. Only its lower @2 bits are input via @3.

perform column selection operation, input/output data line pairs l100~■
The voltage changes, and the detection circuits 6C■ to 6C operate. After returning the signal IC to a low level and until the operation of the detection circuits 6C■ to 6C is completed, the data for addresses Q and C31 is
Assuming that the output amplification circuit 7C8 completes the output of the detection circuits 6C■ to 6C, the old signal IC is set to a high level when the operation of the detection circuits 6C■ to The data on lines I10■ to ■ are taken into latch circuits 6C■' to 6C■''.

The continuation operation is started, and data σ), 0, . . . are read out to the terminal 8.

□ To do this, the signal IC is set to low level, and the same operation is repeated from the beginning of this third set of addresses on the address line of the network 3.

In this way, when data is read out continuously in a mode that is a combination of continuous mode and page mode, the signal IC is activated.

1R are both brought high and all circuitry in memory is returned to standby.

As stated above, in this embodiment, each time the signal IC becomes low level, the operation of the thrift circuits 6C■ to 6C is performed until the operation is completed, and every time 4 pieces of data are generated by the above operation, These are continuously output to terminal 8. In this way, data can be extracted continuously from the terminal 8 without interruption.

The above operation is for reading only, but the same can be done for writing as well.In addition, in the case of writing, it would be bad if the address of the bit to be written changes during the operation, so the write address is set to the next page. All you have to do is input it into the mode cycle.

The lower 1j1112 bits of i, 1, and 112 bits are captured at the time of acquisition, but this varies depending on the operating speed or design of the memory, and is not limited to this embodiment. However, it is not limited to 4 cases,
It goes without saying that various changes can be made.If we keep in mind the relationship tcc<k++t,,c between the cycle time tea in page mode and the cycle time 'gge in continuous operation, the time can be changed. % consecutively without gaps
More than k pieces of data can be retrieved consecutively. Incidentally, even if 1 ee>k-'zse, it would only create a slight time gap and would not impair the effectiveness of this embodiment.

With this S example, the amount of data that can be read/viewed continuously at high speed is j, where J is the number of page modes.
xk, which is significantly increased compared to the previous embodiment.

That is, this embodiment enables high-speed continuous read/write of 1 and i-100 in an operation format substantially similar to the conventional page mode.

The operation in the combination mode of the continuous mode and the page mode described above can be realized in a memory configured with a dynamic circuit.

To begin with the explanation of this embodiment, an outline of a memory that consists only of dynamic circuits and operates only in continuous mode like the memory shown in FIG. 3 will be explained.

FIG. 8 shows the buffer 4C'8. of FIG. Selection circuit 5Z8
．． The output amplifying circuit 708 includes a buffer 4C' and a selection circuit 5Z each having a dynamic type.

The point where the output amplification circuit 7C trap is replaced and the pulse generation circuits 2CA and 2C' in Figure 3 are replaced by the pulse generation circuits 2CD and 2C'BK [fll! ! In that it is
This is mainly different from the memory shown in FIG. Note that the input data buffer 1008 shown in FIG. 3 is also replaced with a dynamic circuit, but the portion related to data writing is not shown in FIG. 8 for the sake of simplicity.

In circuit 2CD, signal IB is low level, that is, signal 11)
This circuit is the same as the circuit 2CA in FIG. 3 in that it outputs an inverted signal 12C of the signal IC in response to the fall of the signal IC only when L is at a high level.

In response to the rise of the signal IC, the signal 11R performs the operation of inverting the level of the signal 12 and the operation of generating a signal for precharging the circuits related to the column selection operation.
The 0 circuit 2C'B differs from the circuit 2CA in FIG. 3 in that the circuit 2CA' in FIG. 3 changes the level of the inverted output 12C' every time the level of the signal IC is inverted. However, each time the signal IC increases, the buffer 4C'% selection circuit 5Z1 output amplification circuit 7C
The main difference from the circuit 2C' of FIG. 3 is that it generates a precharge signal to put the circuit into a standby state.

As can be seen from the time chart in Figure 9, the memory operation in Figure 8 is a column selection operation using column address [F], a row selection operation using row address (), and the first data ■ is output. The operation up to this point is exactly the same as that of the memory shown in FIG.

In this memory, the signal IC is raised when the output amplification circuit 7c outputs the data (2). Along with this, circuit 2C'BK, strange buffer 4C', J? The selection circuit 5Z and the output amplification circuit are precharged and returned to the standby state. At this time, since the signal 11R is at a high level, the circuit 2CD does not respond to the rising edge of the signal IC. Therefore, the buffer 4CA is not recharged and maintains its previous state.

At the time when the first data ■ is output from the output amplifying circuit 7C, the signal IC is raised, and in response to the rising edge of the signal IC, the circuit 2C'B is connected to the circuits 4C' and 5Z related to the continuous mode.
, 7C to precharge it into a standby state (the signal line for this is not shown), and the signal 12
C' goes low - The lower two bits of the next column address ◎ are input via line 3 before these circuits return to the standby state. At this time, even if the upper bits of address Q are input from 93, circuit 4CAri is in a state where it does not respond to this, so it is clear that there is no point in inputting these upper bits via line 3. It is. When the return to the above standby state ends at rLf, the signal IC is set to a low level. In response, circuit 2C'B sets the dispensing stop of the precharge signal, signal 12G''!-, to a high level.

Buffer 4C takes in the lower two bits of address ω) when signal 120' rises and outputs corresponding internal address signals 14C' and 14C'.

Thereafter, in the same manner as in the case of address (), the output of the detection circuit 6C■ is selected by the selection circuit 5Z, and the data ■ is output from the output amplification circuit 7C. Similarly, the lower two bits of the address (Q, ■) are inputted to the +l1st order, and the Il1st order data -■, -■ are output. After that, both the signals IC and IR are set to the positive level, and the circuit 2R receives the signal IR.
Notate, i: In response to Gin, the circuit 5R related to the row 4 selection,
The cell array 100 etc. is precharged and returned to the standby state. At this time, the signal 11R becomes low level, and the circuit 2CDF
'In response to the low level of the i signal 11R and the high level of the signal IC, the circuits 4CA, 5C, and 6C related to column selection
It generates a signal to precharge tZC, and also sets the signal tZC to a low level.

In this way, data 1 to 2 can be read out in continuous mode using a dynamic circuit. In Figure 3,
It can be considered that this memory is different from a continuous mode memory using a static type circuit in that the circuit related to the continuous mode is precharged and returned to the standby state each time one piece of data is output. A memory operating in a combination of continuous mode and page mode can also be easily constructed based on the structure shown in FIG. 6, as shown in FIG.

The memory in FIG. 10 uses the dynamic type cold buffer 4C' used in FIG. 8, the selection circuit 5Z% output amplification circuit 7C, and the pulse generation circuit 2CD in FIG.
Instead, the pulse generating circuit 2CA used in FIG. 6 and the circuit 2CE whose details are shown in FIG. 11 are used, and the pulse generating circuit 2C'A in FIG.
A pulse generating circuit 2C' generates a signal 120' etc.
It differs from the memory of FIG. 6 only in that a circuit 2C'D is used which generates a signal 15C in response to the output of circuit 20E.

Circuit 2CE is a trap signal IC when the signal IR is at a low level.
As shown in FIG. 13, the signal IC' falls in response to the first α fall of the signal IC (period I) and 1 including this first fall. The signal IC falls once within period 1... in which the signal IC falls four times (periods ■ to ■).As will be described later, if the signal IC' falls 174 times, which is the total number of times the signal IC falls. Well, a fall in period ■ is not necessarily necessary. Here, 4 or 1/4f'i each represents the number k of data to be read in continuous mode or its reciprocal.

In FIG. 11, 202 and 203 are circuits for dividing the signal IC into 1/4 (that is, 1/k);
Nine examples are shown using a known JK type flip-flop; it is of course possible to use other types, such as a D type flip-flop. In addition, the above J
The K flip-flop uses a flip-flop whose state is inverted at the downstream end of IC0t input as the clock pulse Cp (Negative)judge 'l'rigg
er Type).

8. With SR type rough flip-flop to recognize when 204Fi operation starts. The convergence tube is inverted at the rising edge of the H input signal. 1. In each of the 7 lip-flops, even if memory operation is interrupted midway, it is possible to reset them to their initial state so that they will resume normal operation in the next cycle. Omitted.

The same applies to the following examples. 205 is an inverter, 206 to 209 are AND circuits, and 210 is an OR circuit.

Non-inverted output 218fl signal I of clip-flop 204
Are R and IC both at high potential? When the signal IC rises (at the end of the operation) and starts the operation (IR is at a low potential), the signal IC rises for the first time and falls by t. 7 flip-flop 2020 inverted output 212, flip-flop 2030 non-inverted output 213, and gates 208-21 for signal 218 and flip-flop 204 inverted output 219.
A logic operation is performed with 0 to form signal IC'.

As a result, as shown in FIG.
．． Period from when the signal IC becomes low level at 1.2...) to when the signal IC starts to become low level at the 5+4α time ■～■
At this point, the signal IC' goes low.

This signal IC' is input to circuit 2CA. In Fig. 619, the signal IC was manually input to the circuit 2CA, but in Fig. 1O, instead of this signal, the signal IC' is input to the circuit 2CA.

Sono #182C'D differs from circuit 2C'B in FIG. 8 only in that it does not have a circuit part that generates signal 15C.
Circuit 2C'E is the signal 15C of circuit 2CA in FIG.
It is connected to the circuit 20H so as to generate the signal 15C in response to the output 1C' of the circuit 2CE. -Now, Figure 13 shows the latch circuit 6C.
It goes without saying that the other 6C■"-6C■" can also be constructed in the same way.The circuit shown here is one of the configuration examples of , can also be applied to the memory shown in FIG. As shown in FIG.
L1. QL! It consists of capacitors Ctl and CLI. Here, when the signal 15C becomes high potential, the transistor Q
! II Q** turns on and node ■.

The output signal of 6(DI) is transmitted to [F], and when the signal 150 becomes a low potential, the transistor Qms*Qt* is turned off, and the above signal is confined in the node ■, [F], and the capacitance CLl e Ct, * are respectively held in the form of charges, that is, they latch the output signal of Sol.

At this time, the [Yes] and [F] signals are each an inverted signal of the other, and according to the ■ and [F] signals, one of the transistors QLI @ QLI is turned on, and ■
When is at a high potential (that is, [F] is a low potential), the transistor QLI is on %QL is turned off and 201 has a high potential.
When , transistor QLI is off %Q1. ! is turned on and a low potential is output to zol.

As explained above, the transistors QLIIQLI are not turned on at the same time, so as not to waste power. In addition, the latched signal changes only by the signal 1scc, and no special signal is required to return this circuit to the standby state.In order to operate this latch circuit normally, the 6C ■〜6C■
Needless to say, the circuit needs to have the driving ability necessary for charging and discharging the capacitor CLII Ct,*.

5 The operation of the memory shown in FIG. 10 will be explained with reference to FIG. 14.

When the signal IC goes low for the first time when the signal IR is at a low level, the signal IC' goes low in synchronization with it. In response to the first falling edge of this signal IC',
The column selection operation is performed in exactly the same manner as in the case of FIG. 6, and the detected data is set in the latch circuits 6C''-6C''. On the other hand, in response to the falling of the signal IC, the circuit 2C
'D is buffer 40'% selection circuit 5Z1 output amplification circuit 7
The precharge of C is interrupted and the signal 12C' is set to high level. In response to the rise of this signal 120', a continuous mode operation based on the lower two bits of addresses (■-()) is started in exactly the same way as in the case of FIG.

6M08) In order to turn on/off the transistors QIT to Qs4 at the time when data is read to the data line pairs I10■ to ■, a circuit 2C'E is provided to set the signal 150 to a high level in synchronization with the start of the column selection operation. In order to perform the row selection, the signal IC' is raised when the signal 10 first rises, and in response to this, the circuits 4CA and 5CA regarding the column selection operation of the circuit 2CAd.

Outputs a signal to return 6C■ to ■ to the grid charge standby state.

During the execution of the return operation to the standby state, the signal IC is repeatedly changed, and the address () to
The continuous mode operation based on ( ) continues. Here, it is assumed that the above-mentioned return operation is completed before starting the continuous mode operation based on the column address O. The lower 2 bits of address O are 11i! Three bits are input via the upper line of line 3.

Then, continuous mode operation using address O is performed in parallel. Thereafter, the page mode and continuous mode are executed in parallel as in the case of FIG. In the case of FIG. 10, circuits 4C', 5Z, 7 regarding continuous mode operation
Since 0 is a dynamic type circuit, the column address o-Q
Each time continuous mode operation is completed in response to the lower two bits of each of
The operation of the memory shown in FIG. 10 differs from that shown in FIG. 6 in that it is necessary to charge the memory from DK and put it into standby state IFBK.

Therefore, the memory shown in Fig. 10 has a slower operating speed than the memory shown in Fig. 6 due to the time required for this precharge operation, but since all the circuits are dynamic type, it has a lower erase N torque than the memory shown in Fig. 6. Can be made small. This also applies to the comparison of the memories in FIGS. 3 and 6.

(3) Row continuous mode With the above embodiments, as mentioned earlier, jxk data can be stored continuously at high speed, but this amount of data can be stored in one row selection address. Limited to the specified range - The next example further expands the above concept, that is, the concept of operating other circuits during continuous operation and simply operating continuously without interruption, to perform both row selection and column selection operations. This section describes a system that allows all data in memory to be read out continuously at high speed. FIG. 15 shows an example of this, and, like the example of FIG. 10, it is an example of a memory configured with a dynamic circuit.

In the same figure, the pulse generation circuit 20EK in FIG.
A circuit 20F is used, the details of which are shown in FIG.
The signal IC" formed by F.

20 pieces each, 2FLK signal IC in Figure 10
', is input instead of IR, which is different from the memory shown in FIG. 10.

The circuit 20F outputs the signal IC when the signal IR is at a low level.
As shown in FIG. 17, the signal IR' falls in response to the first falling edge of the signal IR (period I-1) and ,
Including this first fall, the signal IC falls once every four times during the period c (--------------------------).

Similarly to IR', the signal IC'' falls in response to the first fall of IC (c period I-C), and once within the period in which the signal IC falls four times including this first fall. The C period (■-c to V-R) that falls gradually is the signal IR'
As is clear from FIG. 17, the period at which the signal is at a low level is two cycles of the IC, whereas the period at which the signal is at a low level is equivalent to two cycles of the IC.
" is different from the lli!a pronunciation of the No. 1 IC. This time relationship is an example of the case of high-speed continuous operation (O ~ 0) crab = 4, and the number of k is KN Needless to say, it will be changed as appropriate.

Just to be sure, the signals 1'R' and IC' only need to fall 1/4 of the number of times of the total falling edge circuit of the signal 1c, and the period V-)t
, C are not necessarily required to fall.

Note that here, 4 or 1/4 is k or 1/k, respectively.
represents.

In FIG. 16, the same parts as the 20E circuit shown in FIG. 11 are indicated by the same numbers, and an AND circuit 222 and an OR circuit 224 are added, and a two-man powered OR circuit 210 is replaced by a three-man powered zero circuit 210'. The difference is that it is replaced with .

Flip-flops 202-204 perform the same operations as described above, and for their outputs, gate 20
8 to 210', 222, 224 perform logical operations,
The already explained signals IR' and IC" are formed. As a result, as shown in FIG.几, and the signal IC for the (3004α)th time (α=0.
1.2-), the IC becomes (5+4α)
) Period until it starts to reach a low level If-R~■
At -R, the level is low. In addition, the signal IC# is
Initial low level period of signal IC 1-C and IC 4
After the IC becomes low level at the 1,000th and 4th time, the IC starts to go down to a low level at the 5,000th and 4th time.
- In -C, the level becomes low.

The signal 1' formed as above is input to circuit 2, and the signal IC' is input to circuit 2CA. In other words, in FIG. 10, signal 1 is input to circuit 2R, and signal IC' is input to circuit 2CAK.
In response to the input OK, the signal IR' is output to circuit 2 in FIG.
A signal IC" is input to the circuit 2CA.

FIG. 18 shows detailed operation waveforms of this memory.
In the memory shown in Figure 10, continuous mode and page mode are performed in parallel, whereas in this memory, continuous mode and normal row and column selection operations are performed in parallel and continuously. It is different from the memory of the first Ogaku. transistor Q
, 7 to QI4, normal row and column selection memory operations are performed in parallel and continuous mode thereafter.

When the signal IR becomes low level, 1) t' becomes low level, and in response, the address manual operation is performed in the same manner as in FIG.
A row selection operation is performed based on .

Next, when IC becomes a low level, a column selection operation based on the upper bits of the ADDREPROM is performed as in FIG.
The data detected in is set. After that, when the IC first starts up, IR'llC" stops,
In response to this, the circuits 2R, 2CA perform the primary row and column selection operations, and in order to perform the primary row and column selection operations, the circuits related to these operations are made similar to the 1st cause, and the return operation to the standby state is executed. .

On the other hand, in response to signal IC, continuous mode operation based on the lower two bits of ◎ to q) is performed in the same manner as in FIG.

Here, as in FIG. 10, when Moe (assuming that the return operation of the circuits related to the row and column selection operations described above has been completed) is input to the continuous mode operation start Moe based on IR' falls in response to ICK, and a row selection operation is started based on the row selection address Φ' of the next set of four addresses input via line 3 at the same time as 9. At this time, e Continuous mode operation is performed in parallel with 0. Then when address 0 is input, IC'
In response to the falling edge, a column selection operation based on the column selection address O' is started in the same way as on the falling edge. At this time, the continuous mode operation by the koto is performed in parallel. In this way, [F]′.

When the row and column selection operation based on O' is completed, the detected data is set in 6C■"-6C■" in the same way as the target.

Thereafter, similarly, row and column selection operations and continuous mode operations are performed in parallel.

Now, in this embodiment, if the row address is input in a phase such as O, it becomes impossible to input the address necessary for continuous operation that should be input in (). There is no problem if you configure memory that is less than the number of memory, but if you need to match the number of both,
In other words, in the embodiments described so far, addresses for continuous operation are sequentially input. However, this method is to input all of this information into the -employment field.

Furthermore, regarding the data addressing method, in the embodiments described above, the data to be retrieved consecutively has a common row address and only the column address is different. However, this is the essence of the present invention. For example, instead of a typical sound,
The column addresses are common and only the row addresses are different; therefore, (■ to (■) addresses can be changed in any embodiment, such as by inputting them as row addresses or by mixing row and column addresses. Needless to say.

] The embodiment described here allows continuous operation without any limit on the number of data (within the total capacity of the memory). This allows the memory to be used like a high-speed shift register. Here, we have described the Ginazuk type method, but based on the same idea, it is possible to combine not only the page mode but also ordinary memory operation and continuous operation in the static type as explained in Fig. 6. ``It doesn't matter.

(4) Modification In the continuous mode in the above embodiments, the order in which the four data are read can be specified randomly using the lower two bits of address ()-(), but this order is fixed in advance. This is possible.

For this purpose, for example, instead of the selection circuit 5Z in FIG.
For example, the 0 selection circuit 5ZA may be configured to use a decoder 5ZA configured to select the output lines in order from output MZ■ to ■ every time the input signal 120' becomes high level. pulse, to indicate each selection.

A four-stage shift register in which the signals are sequentially transferred, and each stage is directly connected to the lines 20 to ■, or the signal 12
There is a flip-flop circuit which separates C' and outputs all signals for sequentially selecting lines Z2 to Z2. As another example of displaying four pieces of data in a fixed order in the continuous mode as shown in No. 191g, the outputs of the detection circuits 6C■ to 6C■ are set in parallel to the decoder 5Z and the selection circuit 201,
It is also possible to use a four-stage shift register SR that performs a shift operation in response to the signal 12C' and connect its output to the output amplification circuit 7C.This also allows the output to be sent to the output amplification circuit 7C every time the signal 12C' is generated. Data is transferred in a fixed order, and data can be taken out continuously from the output terminal 8.

In the above example, the four data handled in continuous mode @
The number is fixed, rounded, and in tlX8 diagrams, etc., the lower two bits of the column address required to specify this order are no longer necessary, which contributes to reducing the number of memory input/output terminals (/(number of pins in the package). To specify the first of the four data to be read in continuous mode, input only the lower two bits of the column address of the first data, and then input the three data following this first data to a fixed value. It is also possible to configure the decoder 5Z and the selection circuit 201 so that they are read out in sequence. For example, the shift register SR in FIG. All you have to do is output it from the specified location.

In these modified examples, since the order of data to be output is fixed in advance, higher speed operation is possible than in the embodiment shown in FIG. 8 described above.

Now, in each of the above embodiments, the read and write operations were performed individually, but by simple improvement, operations consisting of various combinations of read and write operations are possible. For example, it is possible to perform both operations at the same time, or to write only to some addresses during continuous operations. These will be explained below based on examples.

In FIG. 20, the signal IWr! This is an external control clock that performs read/write control. Here, reading is performed in a high potential state, and reading is performed in a low potential state. 2W is the pulse generation circuit 2R or 2C (
Both are circuits that generate a plurality of timing pulses necessary for the internal operation of one memory, similar to the circuit shown in FIG. Here, the following buffer G■
A signal 12W supplied to G■ to G■ is shown as a representative example.

The buffers G~G~ take the logical product of the signal 12W and the outputs Z~Z~ of the decoder 5Z (FIG. 8) described in Moe, and select the selection MO8) transistor Qss~ of the selection circuit 203.
(In the AND circuit that controls hs, the input data coming from the hexagonal terminal 9 through the buffer IOC is supplied to one of the common input/output data line pairs 101-10 by the control pressure of this circuit.

In addition, in the same figure, the ninth common input/output data line pair I1 is simplified.
Signals such as 0■ to ■, narrow data line 204 are displayed as one line, and each data line pair I10■ to
Selection MO8 for ■) The transistor is also Q! 3~Q!・Only one item is displayed as shown in . -11 Referring to the operating waveforms in Fig. 21, the good signal I is indicated by () to O in the figure.
During the low level period of C, column addresses () to () are respectively input as in FIG. When the signal IW is at a low potential, the circuit 2W outputs the signal I in synchronization with the falling edge of the signal IC in seconds.
Generates 1 word 12W of inversion of C. Now, the signal 12W and the signals Z■~Z■ are logically ANDed by AND circuits G■~G■, and when the signal 12W is generated, the buffer 4 is
One of MZ■' to Z■' is selected corresponding to the lower two bits of the column address input to C (Fig. 8), and the contents of the buffer IOC are selected. The data is transferred to one of the output data line pairs I10--I10, and the voltage of the data line pair is changed depending on the write data. Thereafter, data is written into the memory cell based on the voltage of this data line pair in the same manner as in the prior art.

When signal IW is high, signal 12W is low and no writing is performed; therefore, either writing or reading can be performed in continuous mode by simply changing the level of signal IW.

For example, when the signal IW is held at the low level of the column address Q-Q as shown by the solid line in FIG. As shown by the chain line in FIG. 21, when a low level voltage is applied only when one address QO is input, writing based on address (0, 6) and address () are performed.

(Reading based on () is mixed and performed in continuous mode.

Furthermore, when the signal IW is input with a certain fixed time delay from the signal IC, a so-called read-modify-write operation is also possible in which data is read from a certain memory cell and then written to the same memory cell. In addition,
It is easy to understand that when this operation is possible, it means that read/write operations for each memory cell can be performed simultaneously.In addition, in FIG. Depending on the circuit configuration of the memory, it may be necessary to electrically disconnect between the circuit 6C and the detection circuit 6C. M O8 for switches like
T Qmm may be provided.

Furthermore, in the partial modify write operation described above, there is also a method in which writing to four memory cells is performed simultaneously. FIG. 22 shows an example of this, in which write data is sequentially written from the selection circuit 203 trap to the latch circuit (or flip 70 tube) IOC'■-100'■ provided corresponding to each data line pair l100-■. , signal 1 after writing to latch circuit 1°C'■~100'■
The control 11C of 2W' transfers these write data to the common input/output data lines I10--I10 in parallel for writing. Here, the signal 12W' is generated by the circuit 2W.

In FIG. 20, when reading and writing address (), it is necessary to perform the write operation after completing the read operation of the common input/output data line pairs I10■ to ■, so the speed may be slightly slower depending on the memory design. Although there is a concern that it will be slow, in this embodiment, there is no problem because writing is performed to the common input/output data line for which reading has already been completed.

Furthermore, in the above practical example, the so-called folded bit line format in which the bit lines are folded over each other has been explained, but the so-called □penbit # is arranged in which the bit lines are arranged to spread left and right across six horizontally thin amplifier circuits. It is also applicable to I-format memory.

1+, In this case, the data to be handled as continuous operation has a fixed row address and only a different column address, as described above, but when the column address is fixed and the row address is different, or both addresses are combined. It can also be applied to things. Although we have disclosed a memory that performs mode and page mode, certain rules and regulations apply to the method of supplying ICs.
If 1 is provided, the signal IR does not need to be used, for example,
If the signal IC is input only once, only operations related to row address selection are performed, and then a refresh operation specific to dynamic memory is performed.If the signal IC is input twice in succession, normal read/write operations are performed. If such a rule is established, the signal IR will not be necessary, and it will be effective in reducing the number of pins of the package that accommodates the memory chip.

Moreover, although the case where the input/output terminals 8.9 are individually provided has been described here, the present invention can also be applied to a memory commonly used for input/output of one terminal. It is unlikely that the present invention can be similarly applied to a memory in which a plurality of 9s are prepared.

(5) Cell Array Arrangement In the embodiments described so far, the memory cell array is consolidated into one memory cell array. In concrete memories, the word line is divided into several parts to minimize the delay time of the word line, or the parasitic capacitance of the bit line is reduced.
In order to increase the read signal from the memory cell, it becomes necessary to divide the bit line. Therefore, in the following, an embodiment will be described in which the memory cell array is divided into several arrays (memory divided).

This book is applicable to any of the embodiments described in FIGS. 8, 10, and 13. Therefore, only the portion related to the array arrangement will be explained below. Further, in the following, reference numbers with a subscript such as R refer to the same reference numbers as those without a subscript in the above embodiments.

In FIG. 23, only the bit line is divided into two, consisting of 92 arrays 100L, 100R, and arrays 100L, 100
R is 100■L~100■L51e'j100 respectively
(11R-100(1)Rt7) Divided into 4 books.

8 input/output data line pairs I10■L-I10■L% I
10■R to I10■R are provided, each corresponding to one pro or tsuku. One of the detection circuits 6CL to 60 (L and 6CR to 6C) is connected to each input/output data line pair.Word line selection circuits 5RL and 5RR
is provided corresponding to each array, and selects one word line in the corresponding array in response to the row address.In this way, one word line is selected in each of the left and right arrays 10OL and 100 lines. The bit line pair selection circuit 5CA is provided between the two arrays, and controls the gate circuit 101L in response to the upper bits other than the lower two bits of the column address.
One bit line pair is selected from each block of array 100L, and similarly, four bit line pairs selected in array 100L are selected from each block of array 100R.
One of the four bit line pairs corresponding to each bit line is selected from each block in array 100R. Eight outputs, including four outputs from the array with the word #ilt selected by the
)L~6C■L is increased in width. Detection circuit 6c ■ Among the eight outputs from L4I, the selection circuit 300 selects four outputs corresponding to either array 100L or 10OR based on the lowest 1 bit of the row address, and serves as a selection circuit for continuous mode. 201. As shown in Figure 6, the trap to operate in both page mode and continuous mode is
There is a latch 6C between the two selection circuits 300 and 201.
6C■" and MOS) Just provide a transistor Q!γ~Qsat.

This embodiment enables continuous mode operation when the data line is divided into two.

@ In Figure 23, four input/output data line pairs I10■~■ and horizontal adding circuits 6C■~6C are connected to the same two arrays as in Figure 83.
■ is provided.

In each block, the intermediate data line pair A L (R1 to 80L (R)
are provided, and each intermediate data line pair is connected to a switch circuit 301R and MO8 consisting of a corresponding input/output data line pair I10■ to ■ (MOS in the connected round) run raster 9 ports to Q4m.
Switch circuit 3 consisting of transistors Q41 to Qsa
01L is provided, as in Fig. 23, Av-10OL, 1
A bit line selection circuit 5CA (not shown) provided between 00R selects left array 10OL or right array 10OR.
4' pieces of data are read out to intermediate data line pair A(1) L-A*L or A*R-A*R, respectively.

If the row addresses of the word lines of arrays 10OL and 100R are even and odd numbers, respectively, the least significant bit of the row address and its inverted bit are given to lines 302R and 302L, and one of the selection circuits 301L and 301R is turned on. View. Thus, 4
1 output is input to 4 pairs of data lines I10■-〇,
It is detected by four detection circuits 6C--6C.

According to this embodiment, the number of input/output data line pairs and detection circuits required for continuous mode operation, that is, four in this case, is sufficient, and the chip area does not increase. The connections between the intermediate data line pairs AL(R) to AL(R) are the same and simple as in the prior art, and pattern design is also facilitated.

FIG. 25 shows a memory in which both word lines and data lines are divided into two, that is, the array is divided into four.
The word lines 00L and 100 are each block 100.
This corresponds to the case of division between ■L and 100■L and between 100■R and 100■R.

Word &! between the divided word lines! selection circuit 5RL,
5RR is provided, and as the word line is divided, gate circuits 101L, 10IR and switch circuits 301L, 30
1B is divided into upper and lower halves. The same applies to the bit line pair selection circuit (not shown) in 41.

In order to simplify the drawing, here, intermediate data line pair A■I, (R)-A■L(R) input/output data line pair I10
■~■ Other signals that form a set of two lines are also represented by one line.

FIG. 26 shows an example in which word lines are divided into two and data #i is divided into four, that is, the whole is divided into eight.

In FIG. 26, one cell array 1 having the same configuration as the cell array 100 shown in FIG. 25 when both word lines and data lines are divided into two is provided.
00. “OOK common input/output data line pair I10■～■
is a first portion provided between both cell arrays in a direction parallel to the word line, and a block 10G in the cell array 100.
A 212) part provided in a direction parallel to the data line between the OR and 100R and between the blocks 1000L and 100L in the cell array 100, and this second part and the selection circuit 301L or 301R.

Selection circuits 301L and 301RK in cell arrays 100 and 100 are connected to lines 302L and 302, respectively.
Two bits of the R row address are given. For example, the lowest two bits of the row addresses of the left word line group and right word line group in the cell array 100 are 00 and 1, respectively.
Assume 0°01.11. Line 3 in cell array 100
02L, 302R, line 302L in cell array 100,
302RK is given from the outside, and a high level signal is given when the 9 addresses are 00, 10, and 01.11, respectively.

In addition, instead of the embodiment, the input/output data line pair I10■~゛■
It is also possible to further extend the second portion to the right and provide the detection circuits 6C (1) to (6) there. At this time, the above-mentioned first portion of the input/output data line pairs I10--I10 is unnecessary. In addition, as shown in FIG. 25 provided in the cell arrays 100, 100, there is a portion extending in the word line direction, and a nine portion lying above the cell arrays 100 and 100 in the data line direction is a human output data line pair. It is also possible to configure I10■ to ■. In this case, it goes without saying that the first and second parts of the description will be unnecessary.

In FIG. 27, the positions of the selection circuits 301L and 301R in the cell arrays 100 and 100 in the word line direction are set between blocks 100■L and 100■L, and the positions of the selection circuits 301L and 301R in the data line direction are set as the selection circuit 5f ( , L, and 5R in that it is placed between the holes. This position is a place where the layout design has a relatively large margin for the top surface injection, and the layout design of the selection circuits 301L and 301B is facilitated. .

Application examples of the present invention in various memory cell array configurations have been described above. The method introduced here in which an intermediate input/output data line pair is provided between the bit line pair and the common input/output data line pair, and this is selected by a switch, contributes to reducing the parasitic capacitance of the input/output data line pair, and operates in continuous mode. It is applicable not only to conventional memories but also to conventional memories.

@28 Figure shows an example of this, in which all bit line pairs are B
■1-B(1)i, B■x~Bot, B■1~BOi,
It is divided into four blocks each consisting of B■1 to B■l, and intermediate input/output data line pairs A■ to A■ are provided corresponding to each block, and intermediate input/output data line pairs A■ A selection circuit 301 consisting of transistors Qsx to Qss is provided for connecting ~A■ to the common input/output data line pair I10, and responds to the upper bits of the column address except for the lower two bits as in FIG. The main difference from FIG. 1 is that a bit line selection circuit 5CA is provided. The bit line selection circuit 5C controls the gate circuit 101 to select one bit line pair from each block, and connects the selected bit line pair to one corresponding intermediate input/output data line pair. Of the four pairs of transistors in the Jl selection circuit 301, only one pair is turned on by a circuit (not shown) K that responds to the lower two bits of the evening address. In this way, only one desired bit@pair is connected to the common data line pair l10K.
Connected.

Now, Fi, which is the most dominant parasitic capacitance of the common input/output data line pair I10, is located between the source or drain diffusion layer of the MOS transistor (see FIG. 1), which is a component of the gate circuit 101, and the silicon substrate. This is the resulting depletion layer capacitance.

In this embodiment, all MOS in the gate circuit 101)
Only 1/4 of the transistors are connected to data line pair 301 at a time. Therefore, in this embodiment, the parasitic capacitance due to the MOS transistor in the gate circuit 101 is significantly reduced to 1/4 of the conventional one, and the parasitic capacitance is significantly reduced by one parasitic capacitance, which is 1/4 of that of the conventional one. 1
As is clear from the above explanation,! The layouts shown in FIGS. 24 to 27 can also be applied to a memory having a pair of common input/output data lines as shown in FIG. 28. Note that in FIG. 28, three bit line pairs other than the bit line pair to be selected are selected, and these are connected to the three corresponding intermediate data line pairs.

Since each of these three intermediate data line pairs is driven by K only by a sense amplifier (not shown) provided for each bit line pair, the operation of these sense amplifiers may be slow. . In order to avoid this, the gate circuit is controlled so that the bit line pair selection circuit 5C selects only one of the bit line pairs B1 to B2 in response to all bits of the column address. A circuit (that is, the same circuit as circuit 5C in FIG. 1) may be used.

[Brief explanation of drawings]

Fig. 1 is a schematic circuit diagram of a dynamo zeta memory using conventional M08 transistors, Fig. 2 is a time chart showing the operation of the memory shown in Fig. 1, and Fig. 3 shows a part of the static type circuit according to the present invention. Example used, IE4 figure (A) t'
jA circuit configuration diagram of a buffer used in the circuit of FIG. 3; FIG. 4(B) is a configuration diagram of a selection circuit used in the circuit of FIG. 3;
Fig. 4 (C) shows the configuration of the output amplification circuit used in the circuit shown in Fig. 3, Fig. 5 shows a time chart showing the operation of the circuit shown in Fig. 3, and Fig. 6 shows the combination of continuous mode and page mode. FIG. 7 is a time chart showing the operation of the memory shown in FIG. A time chart showing the operation of the memory shown in FIG. 8, FIG. 1θ is an embodiment of the present invention that operates in a combination of continuous mode and page mode, and FIG. Figure 12 is a time chart showing the operation of the circuit in Figure 11, and Figure 13 is a time chart showing the operation of the circuit in Figure 11.
Fig. 14 is a time chart showing the operation of the memory shown in Fig. 10. Fig. 15 shows the configuration of the latch circuit used in the memory shown in Fig. Example, FIG. 16 is a block diagram of a pulse generation circuit used in the memory of FIG. 15, and FIG. 17 is a time chart of the operation of the circuit of FIG. 16.
B@ is the time chart of memory operation in Figure 15, 1st
Figure 9 is a modification of the selection circuit for continuous mode operation, the second
0 shows a modification of the data writing circuit, FIG. 21 shows a time chart of the circuit of FIG. 20, FIG. 22 shows another modification of the data writing circuit, and FIG. 23 shows the layout of a memo according to the present invention. , FIG. 24 shows another layout of the memory according to the invention, FIG. 25 shows still another layout of the memory according to the invention, FIG. 26 shows still another layout of the memory according to the invention, and FIG. 28 shows still another layout of the memory according to the present invention, and FIG. 28 shows still another layout of the memory according to the present invention. Kudzu 3 Crocodile 7 ￥J q Fig'･J tOFig. ) ■ ■ ■ Q Riatsu 19 Figure % ZZ Figure 'fJ23 Figure

Claims (1)

[Claims] 1. In a monolithic storage device that includes a pit line group to which a plurality of memory cells are connected, and an I10 line group that connects an external data input/output terminal and a bit line group, and performs data exchange between the input/output terminal and the bit line, The above bit line group is divided into a plurality of groups each having I10@, and each of the above I
A monolithic storage device with a parallel-to-serial conversion circuit between the 10 wire and the input terminal.