JPS6333739B2 - - Google Patents

Description

Detailed Description of the Invention The present invention relates to a phase-locked circuit (hereinafter referred to as PLL) for converting an input signal frequency to an arbitrary frequency. Instead of the two counters m and n required in the case of conversion, one counter and a voltage controlled oscillator that oscillates in a limited frequency range and its output can be used.
It is constructed using a gate circuit that selects one pulse.

A conventional PLL for arbitrary frequency conversion had a configuration as shown in FIG. 1 is an input signal of frequency f _i , 2 is a 1/m counter, 3 is a phase comparator (hereinafter referred to as PSD), 4 is a low pass filter (hereinafter referred to as LPF), 5 is a voltage controlled oscillator (hereinafter referred to as VCO) ,
6 is a 1/n counter, and 7 is an output signal of frequency f _p .

Next, the operation will be explained.

First, input signal 1 with frequency f _i is input to 1/m counter 2.
The frequency is divided into 1/m by On the other hand, the output signal 7 having the frequency f _p is frequency-divided by 1/n by the 1/n counter 6 . The phases of both are compared by the PSD 3, and when phase error is detected, the output is smoothed by the LPF 4 and then applied to the VCO 5, which adjusts the phase of the output signal 7 so that the phase error becomes 0. Control. In this way, in this circuit, the circuit elements 3 to 6 constitute an automatic phase control loop, and as a result, the following equation holds true between the input signal frequency f _i and the output signal frequency f _p .

f _i ×1/m=f _p ×1/n ∴f _p =n/mf _i (1) From this formula, if m and n are arbitrary integers, the input frequency f _i can be converted to any frequency f _p I understand.

In the conventional PLL for arbitrary frequency conversion, f _i ,
1/m with clocks of two different frequencies f _p
Since the counter and 1/n counter are operating,
These two clocks enter the phase comparator placed nearby as noise and generate phase jitter. Furthermore, if the value of the frequency division ratio m is changed to m' in order to change the output frequency, a large step input will be input to the phase comparator, resulting in the disadvantage that the PLL will once become out of synchronization.

This invention was made to eliminate the drawbacks of the conventional ones as described above, and it replaces the 1/n counter with a simple gate circuit to reduce the generation of noise components, and also allows one pulse of the VCO to be used in the gate circuit. By selecting the PLL according to the above, it is possible to replace a large phase step of the input with a small phase step equivalent to the clock interval of the oscillation frequency of the VCO, thereby providing a PLL for arbitrary frequency conversion that does not lock off in response to a large phase step input. The purpose is

FIG. 2 shows an embodiment of the present invention. In the figure, 1 to 4, 7 indicate the same thing as in Figure 1, and 8 indicates 1/
A gate circuit that is triggered by the output 2a of the m counter 2 and generates a gate, and selects one pulse at an appropriate position from the output of the VCO 5' by this gate, 5' oscillates within a limited frequency range.
For example, it is a VCO such as a voltage controlled crystal oscillator.

FIG. 3 shows the waveforms of each part of the circuit shown in FIG. 2, and the operation will be explained using FIG.

First, input signal 1 with frequency f _i is input to 1/m counter 2.
The frequency is divided into 1/m by , and the output 2 of 1/m counter 2
The frequency of a is f _i /m. Using this output signal 2a as a trigger, a suitable time (f _p /n in the case of Fig. 1)
The gate circuit 8 generates a gate 8a at a time corresponding to . Note that this gate 8a is “0”
It is a gate that allows a signal to pass when it is "1" and blocks the signal from passing when it is "1". And this gate 8a
selects a pulse of f _p /n from the output 7 of the VCO 5' and outputs it as the output 8b of the gate circuit 8.
Input to PSD3.

The operation after this is the same as the conventional one, and PSD3
The outputs 2a and 8b are compared in phase, and if there is a phase error, it is smoothed by the LPF 4, and then automatic phase control is performed to correct the oscillation frequency of the VCO 5' to eliminate the phase error. However, the only difference is that the range of change in the oscillation frequency of the VCO 5' is limited so that the two pulses of the output signal 7 do not enter the gate 8a.

Here, in order to change the m:n ratio, if m is changed to m', the output of 1/m counter 2 will be the frequency
The signal 2a' is f _i /m', and the gate 8 in that case
a' is as shown in FIG. 3g, and the output 8b' of the gate circuit 8 is as shown in FIG. 3h. In this case, in the conventional circuit, the phase step is the width W ₁ in Fig. 3.
However, in the case of the present invention, the width is _W2 , which is very small. This effect is significant when m and n are close to each other.

As described above, according to the present invention, the conventional
Replacing the n counter with a simple gate circuit reduces noise generation, and also selects one pulse of the VCO using the gate circuit, converting the large phase step of the input into a small phase equivalent to the clock interval of the VCO's oscillation frequency. By replacing it with a step, a large step input is applied to the PLL, which has the great effect of not causing synchronization loss, and it is smooth even when such a PLL is used in two stages to configure a digital phase shifter. A phase shift effect can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional PLL for arbitrary frequency conversion, and Figure 2 is a PLL according to an embodiment of the present invention.
FIG. 3 is an operating waveform diagram of FIG. 2. 1...Input signal, 2...1/m counter, 3...
...PSD, 4...LPF, 5'...VCO, 8...gate circuit.

Claims (1)

[Claims] 1. A counter that divides the input signal at a predetermined frequency division ratio, a gate circuit that generates a gate based on the output of this counter and selects one pulse from the output of a voltage controlled oscillator, which will be described later, and a A phase comparator that compares the phase with the output, a low-pass filter to which the output of the phase comparator is input, and a voltage-controlled oscillator to which the output of the low-pass filter is input and oscillates in a limited frequency range. Phase-locked circuit for arbitrary frequency conversion.